static void __init whistler_uart_init(void)
{
int i;
struct clk *c;
for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
c = tegra_get_clock_by_name(uart_parent_clk[i].name);
if (IS_ERR_OR_NULL(c)) {
pr_err("Not able to get the clock for %s\n",
uart_parent_clk[i].name);
continue;
}
uart_parent_clk[i].parent_clk = c;
uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
}
whistler_uart_pdata.parent_clk_list = uart_parent_clk;
whistler_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
tegra_uarta_device.dev.platform_data = &whistler_uart_pdata;
tegra_uartb_device.dev.platform_data = &whistler_uart_pdata;
tegra_uartc_device.dev.platform_data = &whistler_uart_pdata;
if (!is_tegra_debug_uartport_hs())
uart_debug_init();
platform_add_devices(whistler_uart_devices,
ARRAY_SIZE(whistler_uart_devices));
}
static void __init pluto_uart_init(void)
{
struct clk *c;
int i;
for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
c = tegra_get_clock_by_name(uart_parent_clk[i].name);
if (IS_ERR_OR_NULL(c)) {
pr_err("Not able to get the clock for %s\n",
uart_parent_clk[i].name);
continue;
}
uart_parent_clk[i].parent_clk = c;
uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
}
pluto_uart_pdata.parent_clk_list = uart_parent_clk;
pluto_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
pluto_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
pluto_loopback_uart_pdata.parent_clk_count =
ARRAY_SIZE(uart_parent_clk);
pluto_loopback_uart_pdata.is_loopback = true;
tegra_uarta_device.dev.platform_data = &pluto_uart_pdata;
tegra_uartb_device.dev.platform_data = &pluto_uart_pdata;
tegra_uartc_device.dev.platform_data = &pluto_uart_pdata;
tegra_uartd_device.dev.platform_data = &pluto_uart_pdata;
/* Register low speed only if it is selected */
if (!is_tegra_debug_uartport_hs())
uart_debug_init();
platform_add_devices(pluto_uart_devices,
ARRAY_SIZE(pluto_uart_devices));
}
int main(void)
{
// At this stage the microcontroller clock setting is already configured,
// this is done through SystemInit() function which is called from startup
// file (startup_stm32f40_41xxx.s) before to branch to application main.
// To reconfigure the default setting of SystemInit() function, refer to
// system_stm32f4xx.c file.
// Update the system clocks.
SystemCoreClockUpdate();
// Event initialization.
event_init();
// LED initialization.
leds_init();
// Debugging UART initialization.
uart_debug_init();
// Initialize the LED blinker.
blink_init();
// Process events.
event_loop();
}
int device_init_platform(struct sys_config *cfg) {
/* Initialize debug first */
uart_debug_init(0, 0);
uart_redirect_debug(cfg->debug.mode);
cs_log_set_level(cfg->debug.level);
return do_wifi(cfg);
}
static void __init roth_uart_init(void)
{
/* Register low speed only if it is selected */
if (!is_tegra_debug_uartport_hs())
uart_debug_init();
platform_add_devices(roth_uart_devices,
ARRAY_SIZE(roth_uart_devices));
}
int main(void){
uart_debug_init();
while(1)
uart_debug_putString("TEMPLATE\r\n");
}
/*
* SmartJS initialization; for non-RTOS env, called as an SDK timer callback
* (`os_timer_...()`). For RTOS env, called by the dispatcher task.
*/
void sjs_init(void *dummy) {
/*
* In order to see debug output (at least errors) during boot we have to
* initialize debug in this point. But default we put debug to UART0 with
* level=LL_ERROR, then configuration is loaded this settings are overridden
*/
uart_debug_init(0, 0);
uart_redirect_debug(1);
cs_log_set_level(LL_ERROR);
#ifndef V7_NO_FS
#ifndef DISABLE_OTA
fs_init(get_fs_addr(get_current_rom()), get_fs_size(get_current_rom()));
finish_update();
#else
fs_init(FS_ADDR, FS_SIZE);
#endif
#endif
init_v7(&dummy);
/* disable GC during further initialization */
v7_set_gc_enabled(v7, 0);
#if !defined(NO_PROMPT)
uart_main_init(0);
#endif
#ifndef V7_NO_FS
init_smartjs();
#endif
#if !defined(NO_PROMPT)
sj_prompt_init(v7);
#endif
#ifdef ESP_UMM_ENABLE
/*
* We want to use our own heap functions instead of the ones provided by the
* SDK.
*
* We have marked `pvPortMalloc` and friends weak, so that we can override
* them with our own implementations, but to actually make it work, we have
* to reference any function from the file with our implementation, so that
* linker will not garbage-collect the whole compilation unit.
*
* So, we have a call to the no-op `esp_umm_init()` here.
*/
esp_umm_init();
#endif
/* SJS initialized, enable GC back, and trigger it */
v7_set_gc_enabled(v7, 1);
v7_gc(v7, 1);
}
static void __init cardhu_uart_init(void)
{
struct clk *c;
int i;
for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
c = tegra_get_clock_by_name(uart_parent_clk[i].name);
if (IS_ERR_OR_NULL(c)) {
pr_err("Not able to get the clock for %s\n",
uart_parent_clk[i].name);
continue;
}
uart_parent_clk[i].parent_clk = c;
uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
}
cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
cardhu_loopback_uart_pdata.parent_clk_count =
ARRAY_SIZE(uart_parent_clk);
cardhu_loopback_uart_pdata.is_loopback = true;
tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
/* UARTE is used for loopback test purpose */
tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
/* Register low speed only if it is selected */
if (!is_tegra_debug_uartport_hs()) {
if(!console_none_on_cmdline){
uart_debug_init();
printk("console_none_on_cmdline+uart_debug_init");
}
/* Clock enable for the debug channel */
if (!IS_ERR_OR_NULL(debug_uart_clk)) {
pr_info("The debug console clock name is %s\n",
debug_uart_clk->name);
c = tegra_get_clock_by_name("pll_p");
if (IS_ERR_OR_NULL(c))
pr_err("Not getting the parent clock pll_p\n");
else
clk_set_parent(debug_uart_clk, c);
clk_enable(debug_uart_clk);
clk_set_rate(debug_uart_clk, clk_get_rate(c));
} else {
pr_err("Not getting the clock %s for debug console\n",
debug_uart_clk->name);
}
}
platform_add_devices(cardhu_uart_devices,
ARRAY_SIZE(cardhu_uart_devices));
}
int __init shuttle_uart_register_devices(void)
{
struct clk *c;
int i;
for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
c = tegra_get_clock_by_name(uart_parent_clk[i].name);
if (IS_ERR_OR_NULL(c)) {
pr_err("Not able to get the clock for %s\n",
uart_parent_clk[i].name);
continue;
}
uart_parent_clk[i].parent_clk = c;
uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
}
shuttle_uart_pdata.parent_clk_list = uart_parent_clk;
shuttle_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
tegra_uarta_device.dev.platform_data = &shuttle_uart_pdata;
tegra_uartb_device.dev.platform_data = &shuttle_uart_pdata;
tegra_uartc_device.dev.platform_data = &shuttle_uart_pdata;
tegra_uartd_device.dev.platform_data = &shuttle_uart_pdata;
tegra_uarte_device.dev.platform_data = &shuttle_uart_pdata;
/* Register low speed only if it is selected */
if (!is_tegra_debug_uartport_hs()) {
uart_debug_init();
/* Clock enable for the debug channel */
if (!IS_ERR_OR_NULL(debug_uart_clk)) {
pr_info("The debug console clock name is %s\n",
debug_uart_clk->name);
c = tegra_get_clock_by_name("pll_p");
if (IS_ERR_OR_NULL(c))
pr_err("Not getting the parent clock pll_p\n");
else
clk_set_parent(debug_uart_clk, c);
clk_enable(debug_uart_clk);
clk_set_rate(debug_uart_clk, debug_uart_port_clk_rate);
} else {
pr_err("Not getting the clock %s for debug console\n",
debug_uart_clk->name);
}
}
return platform_add_devices(shuttle_uart_devices,
ARRAY_SIZE(shuttle_uart_devices));
}
static void __init cardhu_uart_init(void)
{
struct clk *c;
int i;
struct board_info board_info;
tegra_get_board_info(&board_info);
for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
c = tegra_get_clock_by_name(uart_parent_clk[i].name);
if (IS_ERR_OR_NULL(c)) {
pr_err("Not able to get the clock for %s\n",
uart_parent_clk[i].name);
continue;
}
uart_parent_clk[i].parent_clk = c;
uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
}
cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
cardhu_loopback_uart_pdata.parent_clk_count =
ARRAY_SIZE(uart_parent_clk);
cardhu_loopback_uart_pdata.is_loopback = true;
tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
/* UARTE is used for loopback test purpose */
tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
/* Register low speed only if it is selected */
if (!is_tegra_debug_uartport_hs())
uart_debug_init();
#ifdef CONFIG_TEGRA_IRDA
if (((board_info.board_id == BOARD_E1186) ||
(board_info.board_id == BOARD_E1198)) &&
cardhu_irda_pdata.is_irda) {
cardhu_irda_pdata.parent_clk_list = uart_parent_clk;
cardhu_irda_pdata.parent_clk_count =
ARRAY_SIZE(uart_parent_clk);
tegra_uartb_device.dev.platform_data = &cardhu_irda_pdata;
}
#endif
platform_add_devices(cardhu_uart_devices,
ARRAY_SIZE(cardhu_uart_devices));
}
/*
* Sets output for debug messages.
* Available modes are:
* 0 - no debug output
* 1 - print debug output to UART0 (V7's console)
* 2 - print debug output to UART1
*/
static v7_val_t Debug_mode(struct v7 *v7) {
int mode, res;
v7_val_t output_val = v7_arg(v7, 0);
if (!v7_is_number(output_val)) {
printf("Output is not a number\n");
return v7_create_undefined();
}
mode = v7_to_number(output_val);
uart_debug_init(0, 0);
res = uart_redirect_debug(mode);
return v7_create_number(res < 0 ? res : mode);
}
/*
* Sets output for debug messages.
* Available modes are:
* 0 - no debug output
* 1 - print debug output to UART0 (V7's console)
* 2 - print debug output to UART1
*/
ICACHE_FLASH_ATTR static v7_val_t Debug_set_output(struct v7 *v7,
v7_val_t this_obj,
v7_val_t args) {
int mode, res;
v7_val_t output_val = v7_array_get(v7, args, 0);
if (!v7_is_double(output_val)) {
printf("Output is not a number\n");
return v7_create_undefined();
}
mode = v7_to_double(output_val);
uart_debug_init(0, 0);
res = uart_redirect_debug(mode);
return v7_create_number(res < 0 ? res : mode);
}
static void __init enterprise_uart_init(void)
{
int i;
struct clk *c;
for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
c = tegra_get_clock_by_name(uart_parent_clk[i].name);
if (IS_ERR_OR_NULL(c)) {
pr_err("Not able to get the clock for %s\n",
uart_parent_clk[i].name);
continue;
}
uart_parent_clk[i].parent_clk = c;
uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
}
enterprise_uart_pdata.parent_clk_list = uart_parent_clk;
enterprise_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
enterprise_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
enterprise_loopback_uart_pdata.parent_clk_count =
ARRAY_SIZE(uart_parent_clk);
enterprise_loopback_uart_pdata.is_loopback = true;
#ifndef CONFIG_MODEM_ICERA_E450
modem_uart_pdata = enterprise_uart_pdata;
modem_uart_pdata.wake_peer = wake_modem;
modem_uart_pdata.sleep_ctrl = modem_sleep_control;
tegra_uarta_device.dev.platform_data = &modem_uart_pdata;
#else
tegra_uarta_device.dev.platform_data = &enterprise_uart_pdata;
#endif
tegra_uartb_device.dev.platform_data = &enterprise_uart_pdata;
tegra_uartc_device.dev.platform_data = &enterprise_uart_pdata;
tegra_uartd_device.dev.platform_data = &enterprise_uart_pdata;
/* UARTE is used for loopback test purpose */
tegra_uarte_device.dev.platform_data = &enterprise_loopback_uart_pdata;
/* Register low speed only if it is selected */
if (!is_tegra_debug_uartport_hs())
uart_debug_init();
platform_add_devices(enterprise_uart_devices,
ARRAY_SIZE(enterprise_uart_devices));
}
static void __init p1852_uart_init(void)
{
/* Register low speed only if it is selected */
if (!is_tegra_debug_uartport_hs()) {
uart_debug_init();
/* Clock enable for the debug channel */
if (!IS_ERR_OR_NULL(debug_uart_clk)) {
pr_info("The debug console clock name is %s\n",
debug_uart_clk->name);
clk_enable(debug_uart_clk);
clk_set_rate(debug_uart_clk, 408000000);
} else {
pr_err("Not getting the clock %s for debug console\n",
debug_uart_clk->name);
}
}
platform_add_devices(p1852_uart_devices,
ARRAY_SIZE(p1852_uart_devices));
}
/*
* Sets output for debug messages.
* Available modes are:
* 0 - no debug output
* 1 - print debug output to UART0 (V7's console)
* 2 - print debug output to UART1
*/
static enum v7_err Debug_mode(struct v7 *v7, v7_val_t *res) {
enum v7_err rcode = V7_OK;
int mode, ires;
v7_val_t output_val = v7_arg(v7, 0);
if (!v7_is_number(output_val)) {
printf("Output is not a number\n");
*res = v7_create_undefined();
goto clean;
}
mode = v7_to_number(output_val);
uart_debug_init(0, 0);
ires = uart_redirect_debug(mode);
*res = v7_create_number(ires < 0 ? ires : mode);
goto clean;
clean:
return rcode;
}
/**
**===========================================================================
**
** Abstract: main program
**
**===========================================================================
*/
int main(void)
{
int i = 0;
uint8_t msg[2];
uint16_t len;
RCC_ClocksTypeDef RCC_Clocks;
/* Initialize LEDs and User_Button on STM32F4-Discovery --------------------*/
STM_EVAL_PBInit(BUTTON_USER, BUTTON_MODE_GPIO);
STM_EVAL_LEDInit(LED3);
STM_EVAL_LEDInit(LED4);
/* SysTick end of count event each 1ms */
RCC_GetClocksFreq(&RCC_Clocks);
SysTick_Config(RCC_Clocks.HCLK_Frequency / 1000);
#ifdef DEBUG
/* Init Debug out setting(UART2) */
uart_debug_init();
#endif
/* Init Host Library */
USBH_Init( &USB_OTG_Core_dev,
USB_OTG_FS_CORE_ID,
&USB_Host,
&USBH_ADK_cb,
&USR_Callbacks
);
/* Init ADK Library */
USBH_ADK_Init( "ammlab.org",
"HelloADK",
"HelloADK for GR-SAKURA for STM32F4",
"1.0",
"https://play.google.com/store/apps/details?id=org.ammlab.android.helloadk",
"1234567"
);
while (1)
{
/* Host Task handler */
USBH_Process(&USB_OTG_Core_dev, &USB_Host);
/* Accessory Mode enabled */
if ( USBH_ADK_getStatus() == ADK_IDLE)
{
/* --------------------------------------------------------------------------- */
// in
len = USBH_ADK_read(&USB_OTG_Core_dev, msg, sizeof(msg));
if ( len > 0 )
{
if ( msg[0] == 0x1)
{
if ( msg[1] == 0x1)
{
STM_EVAL_LEDOn(LED3);
}
else
{
STM_EVAL_LEDOff(LED3);
}
}
}
// out
if ( STM_EVAL_PBGetState(BUTTON_USER) )
{
msg[0] = 1;
msg[1] = 1;
STM_EVAL_LEDOn(LED4);
}
else
{
msg[0] = 1;
msg[1] = 0;
STM_EVAL_LEDOff(LED4);
}
USBH_ADK_write(&USB_OTG_Core_dev, msg, sizeof(msg));
}
Delay(1);
if (i++ == 100)
{
STM_EVAL_LEDToggle(LED3);
i = 0;
}
}
}
