static void puv3_soc_init(CPUUniCore32State *env) { qemu_irq cpu_intc, irqs[PUV3_IRQS_NR]; DeviceState *dev; MemoryRegion *i8042 = g_new(MemoryRegion, 1); int i; /* Initialize interrupt controller */ cpu_intc = qemu_allocate_irq(puv3_intc_cpu_handler, uc32_env_get_cpu(env), 0); dev = sysbus_create_simple("puv3_intc", PUV3_INTC_BASE, cpu_intc); for (i = 0; i < PUV3_IRQS_NR; i++) { irqs[i] = qdev_get_gpio_in(dev, i); } /* Initialize minimal necessary devices for kernel booting */ sysbus_create_simple("puv3_pm", PUV3_PM_BASE, NULL); sysbus_create_simple("puv3_dma", PUV3_DMA_BASE, NULL); sysbus_create_simple("puv3_ost", PUV3_OST_BASE, irqs[PUV3_IRQS_OST0]); sysbus_create_varargs("puv3_gpio", PUV3_GPIO_BASE, irqs[PUV3_IRQS_GPIOLOW0], irqs[PUV3_IRQS_GPIOLOW1], irqs[PUV3_IRQS_GPIOLOW2], irqs[PUV3_IRQS_GPIOLOW3], irqs[PUV3_IRQS_GPIOLOW4], irqs[PUV3_IRQS_GPIOLOW5], irqs[PUV3_IRQS_GPIOLOW6], irqs[PUV3_IRQS_GPIOLOW7], irqs[PUV3_IRQS_GPIOHIGH], NULL); /* Keyboard (i8042), mouse disabled for nographic */ i8042_mm_init(irqs[PUV3_IRQS_PS2_KBD], NULL, i8042, PUV3_REGS_OFFSET, 4); memory_region_add_subregion(get_system_memory(), PUV3_PS2_BASE, i8042); }
void switch_mode(CPUUniCore32State *env, int mode) { UniCore32CPU *cpu = uc32_env_get_cpu(env); if (mode != ASR_MODE_USER) { cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); } }
void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg, uint32_t cop) { UniCore32CPU *cpu = uc32_env_get_cpu(env); /* * movc pp.nn, rn, #imm9 * rn: UCOP_REG_D * nn: UCOP_REG_N * 1: sys control reg. * 2: page table base reg. * 3: data fault status reg. * 4: insn fault status reg. * 5: cache op. reg. * 6: tlb op. reg. * imm9: split UCOP_IMM10 with bit5 is 0 */ switch (creg) { case 1: if (cop != 0) { goto unrecognized; } env->cp0.c1_sys = val; break; case 2: if (cop != 0) { goto unrecognized; } env->cp0.c2_base = val; break; case 3: if (cop != 0) { goto unrecognized; } env->cp0.c3_faultstatus = val; break; case 4: if (cop != 0) { goto unrecognized; } env->cp0.c4_faultaddr = val; break; case 5: switch (cop) { case 28: DPRINTF("Invalidate Entire I&D cache\n"); return; case 20: DPRINTF("Invalidate Entire Icache\n"); return; case 12: DPRINTF("Invalidate Entire Dcache\n"); return; case 10: DPRINTF("Clean Entire Dcache\n"); return; case 14: DPRINTF("Flush Entire Dcache\n"); return; case 13: DPRINTF("Invalidate Dcache line\n"); return; case 11: DPRINTF("Clean Dcache line\n"); return; case 15: DPRINTF("Flush Dcache line\n"); return; } break; case 6: if ((cop <= 6) && (cop >= 2)) { /* invalid all tlb */ tlb_flush(CPU(cpu), 1); return; } break; default: goto unrecognized; } return; unrecognized: DPRINTF("Wrong register (%d) or wrong operation (%d) in cp0_set!\n", creg, cop); }