static bool udd_ep_interrupt(void)
{
udd_ep_id_t ep;
udd_ep_job_t *ptr_job;
// For each endpoint different of control endpoint (0)
for (ep = 1; ep <= USB_DEVICE_MAX_EP; ep++) {
// Get job corresponding at endpoint
ptr_job = &udd_ep_job[ep - 1];
// Check DMA event
if (Is_udd_endpoint_dma_interrupt_enabled(ep)
&& Is_udd_endpoint_dma_interrupt(ep)) {
uint32_t nb_remaining;
if( udd_endpoint_dma_get_status(ep)
& AVR32_USBB_UDDMA1_STATUS_CH_EN_MASK) {
return true; // Ignore EOT_STA interrupt
}
udd_disable_endpoint_dma_interrupt(ep);
// Save number of data no transfered
nb_remaining = (udd_endpoint_dma_get_status(ep) &
AVR32_USBB_UDDMA1_STATUS_CH_BYTE_CNT_MASK)
>> AVR32_USBB_UDDMA1_STATUS_CH_BYTE_CNT_OFFSET;
if (nb_remaining) {
// Transfer no complete (short packet or ZLP) then:
// Update number of data transfered
ptr_job->nb_trans -= nb_remaining;
// Set transfer complete to stop the transfer
ptr_job->buf_size = ptr_job->nb_trans;
}
udd_ep_trans_done(ep);
return true;
}
// Check empty bank interrupt event
if (Is_udd_endpoint_interrupt_enabled(ep)) {
if (Is_udd_in_send_interrupt_enabled(ep) && Is_udd_in_send(ep)) {
udd_disable_in_send_interrupt(ep);
// One bank is free then send a ZLP
udd_ack_in_send(ep);
udd_ack_fifocon(ep);
udd_ep_finish_job(ptr_job, false, ep);
return true;
}
if (Is_udd_bank_interrupt_enabled(ep) && (0 == udd_nb_busy_bank(ep))) {
// End of background transfer on IN endpoint
udd_disable_bank_interrupt(ep);
udd_disable_endpoint_interrupt(ep);
Assert(ptr_job->stall_requested);
// A stall has been requested during background transfer
ptr_job->stall_requested = false;
udd_disable_endpoint_bank_autoswitch(ep);
udd_enable_stall_handshake(ep);
udd_reset_data_toggle(ep);
return true;
}
}
}
static bool udd_ep_interrupt(void)
{
udd_ep_id_t ep;
udd_ep_job_t *ptr_job;
// For each endpoint different of control endpoint (0)
for (ep = 1; ep <= USB_DEVICE_MAX_EP; ep++) {
// Check DMA event
if (Is_udd_endpoint_dma_interrupt_enabled(ep)
&& Is_udd_endpoint_dma_interrupt(ep)) {
uint32_t nb_remaining;
udd_disable_endpoint_dma_interrupt(ep);
// Save number of data no transfered
nb_remaining = (udd_endpoint_dma_get_status(ep) &
AVR32_USBB_UDDMA1_STATUS_CH_BYTE_CNT_MASK)
>>
AVR32_USBB_UDDMA1_STATUS_CH_BYTE_CNT_OFFSET;
// Get job corresponding at endpoint
ptr_job = &udd_ep_job[ep - 1];
// Update number of data transfered
ptr_job->buf_size -= nb_remaining;
if (!Is_udd_endpoint_in(ep)) {
// Disable autoswitch bank on OUT
udd_disable_endpoint_bank_autoswitch(ep);
} else {
// Wait end of background transfer on IN endpoint before disabled autoswitch bank
udd_enable_endpoint_interrupt(ep);
udd_enable_bank_interrupt(ep);
}
// Call callback to signal end of transfer
udd_ep_finish_job(&udd_ep_job[ep - 1], false);
return true;
}
// Check empty bank interrupt event
if (Is_udd_endpoint_interrupt_enabled(ep)
&& (0 == udd_nb_busy_bank(ep))) {
// End of background transfer on IN endpoint
udd_disable_bank_interrupt(ep);
udd_disable_endpoint_interrupt(ep);
// If no new transfer running then disable autoswitch bank
if (!udd_ep_job[ep - 1].busy) {
udd_disable_endpoint_bank_autoswitch(ep);
}
// If a stall has been requested during backgound transfer then execute it
if (udd_ep_job[ep - 1].stall_requested) {
udd_ep_job[ep - 1].stall_requested = false;
udd_enable_stall_handshake(ep);
udd_reset_data_toggle(ep);
}
return true;
}
}
static void udd_ep_trans_done(udd_ep_id_t ep)
{
uint32_t udd_dma_ctrl = 0;
udd_ep_job_t *ptr_job;
iram_size_t next_trans;
irqflags_t flags;
// Get job corresponding at endpoint
ptr_job = &udd_ep_job[ep - 1];
if (!ptr_job->busy) {
return; // No job is running, then ignore it (system error)
}
if (ptr_job->nb_trans != ptr_job->buf_size) {
// Need to send or receive other data
next_trans = ptr_job->buf_size - ptr_job->nb_trans;
if (UDD_ENDPOINT_MAX_TRANS < next_trans) {
// The USB hardware support a maximum
// transfer size of UDD_ENDPOINT_MAX_TRANS Bytes
next_trans = UDD_ENDPOINT_MAX_TRANS;
// Set 0 to transfer the maximum
udd_dma_ctrl = (0 <<
AVR32_USBB_UDDMA1_CONTROL_CH_BYTE_LENGTH_OFFSET)
& AVR32_USBB_UDDMA1_CONTROL_CH_BYTE_LENGTH_MASK;
} else {
udd_dma_ctrl = (next_trans <<
AVR32_USBB_UDDMA1_CONTROL_CH_BYTE_LENGTH_OFFSET)
& AVR32_USBB_UDDMA1_CONTROL_CH_BYTE_LENGTH_MASK;
}
if (Is_udd_endpoint_in(ep)) {
if (0 != next_trans % udd_get_endpoint_size(ep)) {
// Enable short packet option
// else the DMA transfer is accepted
// and interrupt DMA valid but nothing is sent.
udd_dma_ctrl |= AVR32_USBB_UDDMA1_CONTROL_DMAEND_EN_MASK;
// No need to request another ZLP
ptr_job->b_shortpacket = false;
}
} else {
if ((USB_EP_TYPE_ISOCHRONOUS != udd_get_endpoint_type(ep))
|| (next_trans <= udd_get_endpoint_size(ep))) {
// Enable short packet reception
udd_dma_ctrl |= AVR32_USBB_UDDMA1_CONTROL_EOT_IRQ_EN_MASK
| AVR32_USBB_UDDMA1_CONTROL_BUFF_CLOSE_IN_EN_MASK;
}
}
// Start USB DMA to fill or read fifo of the selected endpoint
udd_endpoint_dma_set_addr(ep, (U32) &ptr_job->buf[ptr_job->nb_trans]);
udd_dma_ctrl |= AVR32_USBB_UDDMA1_CONTROL_EOBUFF_IRQ_EN_MASK |
AVR32_USBB_UDDMA1_CONTROL_CH_EN_MASK;
// Disable IRQs to have a short sequence
// between read of EOT_STA and DMA enable
flags = cpu_irq_save();
if ( !(udd_endpoint_dma_get_status(ep)
& AVR32_USBB_UDDMA1_STATUS_EOT_STA_MASK)) {
udd_endpoint_dma_set_control(ep, udd_dma_ctrl);
ptr_job->nb_trans += next_trans;
udd_enable_endpoint_dma_interrupt(ep);
cpu_irq_restore(flags);
return;
}
cpu_irq_restore(flags);
// Here a ZLP has been received
// and the DMA transfer must be not started.
// It is the end of transfer
ptr_job->buf_size = ptr_job->nb_trans;
}
if (Is_udd_endpoint_in(ep)) {
if (ptr_job->b_shortpacket) {
// Need to send a ZLP (No possible with USB DMA)
// enable interrupt to wait a free bank to sent ZLP
udd_ack_in_send(ep);
if (Is_udd_write_enabled(ep)) {
// Force interrupt in case of ep already free
udd_raise_in_send(ep);
}
udd_enable_in_send_interrupt(ep);
udd_enable_endpoint_interrupt(ep);
return;
}
}
// Call callback to signal end of transfer
udd_ep_finish_job(ptr_job, false, ep);
}
