/*! \brief Main function. Execution starts here.
*/
int main(void)
{
irq_initialize_vectors();
cpu_irq_enable();
// Initialize the sleep manager
sleepmgr_init();
sysclk_init();
board_init();
ui_init();
ui_powerdown();
// Start USB stack to authorize VBus monitoring
udc_start();
// The main loop manages only the power mode
// because the USB management is done by interrupt
while (true) {
sleepmgr_enter_sleep();
if (main_b_cdc_enable) {
// Here CPU wakeup at each SOF (1ms)
for (uint8_t port = 0; port < UDI_CDC_PORT_NB; port++) {
if (!(main_port_open & (1 << port))) {
// Port not open
continue;
}
if (!udi_cdc_multi_is_rx_ready(port)) {
// No data received
continue;
}
int value = udi_cdc_multi_getc(port);
if (value != 'p') {
// Ignore this value
continue;
}
udi_cdc_multi_write_buf(port, "PORT", sizeof("PORT")-1);
udi_cdc_multi_putc(port, port+'0');
udi_cdc_multi_putc(port, '\n');
udi_cdc_multi_putc(port, '\r');
}
}
}
}
static void usart_handler(uint8_t port)
{
Usart* usart = get_usart(port);
uint32_t sr = usart_get_status(usart);
if (sr & US_CSR_RXRDY) {
// Data received
ui_com_tx_start();
uint32_t value;
bool b_error = usart_read(usart, &value) ||
(sr & (US_CSR_FRAME | US_CSR_TIMEOUT | US_CSR_PARE));
if (b_error) {
usart_reset_rx(usart);
usart_enable_rx(usart);
udi_cdc_multi_signal_framing_error(port);
ui_com_error();
}
// Transfer UART RX fifo to CDC TX
if (!udi_cdc_multi_is_tx_ready(port)) {
// Fifo full
udi_cdc_multi_signal_overrun(port);
ui_com_overflow();
} else {
udi_cdc_multi_putc(port, value);
}
ui_com_tx_stop();
return;
}
if (sr & US_CSR_TXRDY) {
// Data send
if (udi_cdc_multi_is_rx_ready(port)) {
// Transmit next data
ui_com_rx_start();
int c = udi_cdc_multi_getc(port);
usart_write(usart, c);
} else {
// Fifo empty then Stop UART transmission
usart_disable_tx(usart);
usart_disable_interrupt(usart, US_IDR_TXRDY);
ui_com_rx_stop();
}
}
}
int udi_cdc_putc(int value)
{
return udi_cdc_multi_putc(0, value);
}
