static int __init handle_display_devices(void)
{
bool video_mode = false;
struct mcde_platform_data *pdata = ux500_mcde_device.dev.platform_data;
pr_debug("%s\n", __func__);
#ifdef CONFIG_FB_MCDE
(void)mcde_dss_register_notifier(&display_nb);
#endif
if (uib_is_u8500uibr3() && sony_port0.mode == MCDE_PORTMODE_VID)
video_mode = true;
/*
* display_initialized_during_boot will have the
* port_video_mode value + 1 if the display was initiated during boot,
* otherwise zero
*/
if (display_initialized_during_boot) {
/* restore video_mode value from boot */
u32 boot_video_mode = display_initialized_during_boot - 1;
/* if boot_video_mode not expected,
* clear already initiated flag */
if ((boot_video_mode == MCDE_PORTMODE_VID) != video_mode)
display_initialized_during_boot = 0;
}
/* Set powermode to STANDBY if startup graphics is executed */
if (display_initialized_during_boot) {
samsung_s6d16d0_display0.power_mode = MCDE_DISPLAY_PM_STANDBY;
sony_acx424akp_display0.power_mode = MCDE_DISPLAY_PM_STANDBY;
sharp_lq043t1_display0.power_mode = MCDE_DISPLAY_PM_STANDBY;
}
/* Display reset GPIO is different depending on reference boards */
if (machine_is_hrefv60() || machine_is_u8520()) {
samsung_s6d16d0_pdata0.reset_gpio = HREFV60_DISP1_RST_GPIO;
samsung_s6d16d0_pdata1.reset_gpio = HREFV60_DISP2_RST_GPIO;
} else {
samsung_s6d16d0_pdata0.reset_gpio = MOP500_DISP1_RST_GPIO;
samsung_s6d16d0_pdata1.reset_gpio = MOP500_DISP2_RST_GPIO;
}
/* Initialize all needed clocks*/
if (!display_initialized_during_boot) {
struct clk *clk_dsi_pll;
struct clk *clk_hdmi;
struct clk *clk_tv;
u32 freq;
/*
* The TV CLK is used as parent for the
* DSI LP clock.
*/
clk_tv = clk_get(&ux500_mcde_device.dev, "tv");
if (TV_FREQ_HZ != clk_round_rate(clk_tv, TV_FREQ_HZ))
pr_warning("%s: TV_CLK freq differs %ld\n", __func__,
clk_round_rate(clk_tv, TV_FREQ_HZ));
clk_set_rate(clk_tv, TV_FREQ_HZ);
clk_put(clk_tv);
/*
* The HDMI CLK is used as parent for the
* DSI HS clock.
*/
clk_hdmi = clk_get(&ux500_mcde_device.dev, "hdmi");
if (HDMI_FREQ_HZ != clk_round_rate(clk_hdmi, HDMI_FREQ_HZ))
pr_warning("%s: HDMI freq differs %ld\n", __func__,
clk_round_rate(clk_hdmi, HDMI_FREQ_HZ));
clk_set_rate(clk_hdmi, HDMI_FREQ_HZ);
clk_put(clk_hdmi);
/*
* The DSI PLL CLK is used as DSI PLL for direct freq for
* link 2. Link 0/1 is then divided with 1/2/4 from this freq.
*/
freq = video_mode ? DSI_PLL_FREQ_HZ_VID : DSI_PLL_FREQ_HZ_CMD;
clk_dsi_pll = clk_get(&ux500_mcde_device.dev, "dsipll");
if (freq != clk_round_rate(clk_dsi_pll, freq))
pr_warning("%s: DSI_PLL freq differs %ld\n", __func__,
clk_round_rate(clk_dsi_pll, freq));
clk_set_rate(clk_dsi_pll, freq);
clk_put(clk_dsi_pll);
}
/* MCDE pixelfetchwtrmrk levels per overlay */
pdata->pixelfetchwtrmrk[0] = video_mode ? 128 : 48; /* LCD 32bpp */
pdata->pixelfetchwtrmrk[1] = video_mode ? 128 : 64; /* LCD 16bpp */
pdata->pixelfetchwtrmrk[2] = 128; /* HDMI 32bpp */
pdata->pixelfetchwtrmrk[3] = 192; /* HDMI 16bpp */
/* Not all STUIBs supports VSYNC, disable vsync for STUIB */
if (uib_is_stuib()) {
/* Samsung display on STUIB */
samsung_s6d16d0_display0.port->sync_src = MCDE_SYNCSRC_OFF;
samsung_s6d16d0_display0.orientation = MCDE_DISPLAY_ROT_90_CCW;
(void)mcde_display_device_register(&samsung_s6d16d0_display0);
} else if (uib_is_u8500uib()) {
/* Samsung display on U8500UIB */
samsung_s6d16d0_display0.orientation = MCDE_DISPLAY_ROT_90_CW;
(void)mcde_display_device_register(&samsung_s6d16d0_display0);
} else if (uib_is_u8500uibr3()) {
/* Sony display on U8500UIBV3 */
sony_acx424akp_display0_pdata.reset_gpio = HREFV60_DISP1_RST_GPIO;
(void)mcde_display_device_register(&sony_acx424akp_display0);
} else {
sharp_lq043t1_display0_pdata.reset_gpio = HREFV60_DISP1_RST_GPIO;
(void)mcde_display_device_register(&sharp_lq043t1_display0);
}
/* Display reset GPIO is different depending on reference boards */
if (uib_is_stuib())
(void)mcde_display_device_register(&samsung_s6d16d0_display1);
#if defined(CONFIG_U8500_TV_OUTPUT_AV8100)
INIT_DELAYED_WORK_DEFERRABLE(&work_dispreg_hdmi,
delayed_work_dispreg_hdmi);
schedule_delayed_work(&work_dispreg_hdmi,
msecs_to_jiffies(DISPREG_HDMI_DELAY));
#endif
return 0;
}
static void mop500_pins_suspend_force(void)
{
if (machine_is_hrefv60() || machine_is_u8520() ||
machine_is_u9540())
sleep_pins_config_pm(mop500_pins_common_power_save_bank0_href60,
ARRAY_SIZE(mop500_pins_common_power_save_bank0_href60));
else
sleep_pins_config_pm(mop500_pins_common_power_save_bank0,
ARRAY_SIZE(mop500_pins_common_power_save_bank0));
sleep_pins_config_pm(mop500_pins_common_power_save_bank1,
ARRAY_SIZE(mop500_pins_common_power_save_bank1));
if (machine_is_hrefv60() || machine_is_u8520() ||
machine_is_u9540())
sleep_pins_config_pm(mop500_pins_common_power_save_bank2_href60,
ARRAY_SIZE(mop500_pins_common_power_save_bank2_href60));
else
sleep_pins_config_pm(mop500_pins_common_power_save_bank2,
ARRAY_SIZE(mop500_pins_common_power_save_bank2));
sleep_pins_config_pm(mop500_pins_common_power_save_bank3,
ARRAY_SIZE(mop500_pins_common_power_save_bank3));
if (pins_for_u9500() && uib_is_u8500uibr3())
sleep_pins_config_pm(mop500_pins_common_power_save_bank4_u9500_uibr3,
ARRAY_SIZE(mop500_pins_common_power_save_bank4_u9500_uibr3));
else
sleep_pins_config_pm(mop500_pins_common_power_save_bank4,
ARRAY_SIZE(mop500_pins_common_power_save_bank4));
if (machine_is_hrefv60() || machine_is_u8520() ||
machine_is_u9540())
sleep_pins_config_pm(mop500_pins_common_power_save_bank5_href60,
ARRAY_SIZE(mop500_pins_common_power_save_bank5_href60));
else
sleep_pins_config_pm(mop500_pins_common_power_save_bank5,
ARRAY_SIZE(mop500_pins_common_power_save_bank5));
if (pins_for_u9500())
sleep_pins_config_pm(mop500_pins_common_power_save_bank6_u9500,
ARRAY_SIZE(mop500_pins_common_power_save_bank6_u9500));
else if (machine_is_hrefv60() || machine_is_u8520() ||
machine_is_u9540())
sleep_pins_config_pm(mop500_pins_common_power_save_bank6_href60,
ARRAY_SIZE(mop500_pins_common_power_save_bank6_href60));
else
sleep_pins_config_pm(mop500_pins_common_power_save_bank6,
ARRAY_SIZE(mop500_pins_common_power_save_bank6));
if (pins_for_u9500())
sleep_pins_config_pm(mop500_pins_common_power_save_bank7_u9500,
ARRAY_SIZE(mop500_pins_common_power_save_bank7_u9500));
else if (machine_is_hrefv60() || machine_is_u8520() ||
machine_is_u9540())
sleep_pins_config_pm(mop500_pins_common_power_save_bank7_href60,
ARRAY_SIZE(mop500_pins_common_power_save_bank7_href60));
else
sleep_pins_config_pm(mop500_pins_common_power_save_bank7,
ARRAY_SIZE(mop500_pins_common_power_save_bank7));
sleep_pins_config_pm(mop500_pins_common_power_save_bank8,
ARRAY_SIZE(mop500_pins_common_power_save_bank8));
}
static int __init handle_display_devices_in_u8500(void)
{
struct mcde_platform_data *pdata = ux500_mcde_device.dev.platform_data;
pr_debug("%s\n", __func__);
#ifdef CONFIG_FB_MCDE
(void)mcde_dss_register_notifier(&display_nb);
#endif
/* Set powermode to STANDBY if startup graphics is executed */
if (display_initialized_during_boot) {
samsung_s6d16d0_display0.power_mode = MCDE_DISPLAY_PM_STANDBY;
sony_acx424akp_display0.power_mode = MCDE_DISPLAY_PM_STANDBY;
}
/* Display reset GPIO is different depending on reference boards */
if (machine_is_hrefv60() || machine_is_u8520() || machine_is_u9540()) {
samsung_s6d16d0_pdata0.reset_gpio = HREFV60_DISP1_RST_GPIO;
samsung_s6d16d0_pdata1.reset_gpio = HREFV60_DISP2_RST_GPIO;
} else {
samsung_s6d16d0_pdata0.reset_gpio = MOP500_DISP1_RST_GPIO;
samsung_s6d16d0_pdata1.reset_gpio = MOP500_DISP2_RST_GPIO;
}
/* Initialize all needed clocks*/
if (!display_initialized_during_boot) {
struct clk *clk_dsi_pll;
struct clk *clk_hdmi;
struct clk *clk_tv;
/*
* The TV CLK is used as parent for the
* DSI LP clock.
*/
clk_tv = clk_get(&ux500_mcde_device.dev, "tv");
if (TV_FREQ_HZ != clk_round_rate(clk_tv, TV_FREQ_HZ))
pr_warning("%s: TV_CLK freq differs %ld\n", __func__,
clk_round_rate(clk_tv, TV_FREQ_HZ));
clk_set_rate(clk_tv, TV_FREQ_HZ);
clk_put(clk_tv);
/*
* The HDMI CLK is used as parent for the
* DSI HS clock.
*/
clk_hdmi = clk_get(&ux500_mcde_device.dev, "hdmi");
if (HDMI_FREQ_HZ != clk_round_rate(clk_hdmi, HDMI_FREQ_HZ))
pr_warning("%s: HDMI freq differs %ld\n", __func__,
clk_round_rate(clk_hdmi, HDMI_FREQ_HZ));
clk_set_rate(clk_hdmi, HDMI_FREQ_HZ);
clk_put(clk_hdmi);
/*
* The DSI PLL CLK is used as DSI PLL for direct freq for
* link 2. Link 0/1 is then divided with 1/2/4 from this freq.
*/
clk_dsi_pll = clk_get(&ux500_mcde_device.dev, "dsihs2");
if (DSI_PLL_FREQ_HZ != clk_round_rate(clk_dsi_pll,
DSI_PLL_FREQ_HZ))
pr_warning("%s: DSI_PLL freq differs %ld\n", __func__,
clk_round_rate(clk_dsi_pll, DSI_PLL_FREQ_HZ));
clk_set_rate(clk_dsi_pll, DSI_PLL_FREQ_HZ);
clk_put(clk_dsi_pll);
}
/* MCDE pixelfetchwtrmrk levels per overlay */
pdata->pixelfetchwtrmrk[0] = 48; /* LCD 32 bpp */
pdata->pixelfetchwtrmrk[1] = 64; /* LCD 16 bpp */
pdata->pixelfetchwtrmrk[2] = 128; /* HDMI 32 bpp */
pdata->pixelfetchwtrmrk[3] = 192; /* HDMI 16 bpp */
/* Not all STUIBs supports VSYNC, disable vsync for STUIB */
if (uib_is_stuib()) {
/* Samsung display on STUIB */
samsung_s6d16d0_display0.port->sync_src = MCDE_SYNCSRC_OFF;
samsung_s6d16d0_display0.orientation = MCDE_DISPLAY_ROT_90_CCW;
(void)mcde_display_device_register(&samsung_s6d16d0_display0);
} else if (uib_is_u8500uib()) {
/* Samsung display on U8500UIB */
samsung_s6d16d0_display0.orientation = MCDE_DISPLAY_ROT_90_CW;
(void)mcde_display_device_register(&samsung_s6d16d0_display0);
} else if (uib_is_u8500uibr3()) {
/* Sony display on U8500UIBV3 */
(void)mcde_display_device_register(&sony_acx424akp_display0);
} else {
WARN_ON("Unknown UI board");
}
/* Display reset GPIO is different depending on reference boards */
if (uib_is_stuib())
(void)mcde_display_device_register(&samsung_s6d16d0_display1);
#if defined(CONFIG_U8500_TV_OUTPUT_AV8100)
INIT_DELAYED_WORK_DEFERRABLE(&work_dispreg_hdmi,
delayed_work_dispreg_hdmi);
schedule_delayed_work(&work_dispreg_hdmi,
msecs_to_jiffies(DISPREG_HDMI_DELAY));
#endif
return 0;
}
