static u32 libfdt_property_len(const char *prop,
u32 address_cells, u32 size_cells, u32 len)
{
u32 lsz, type, reg_cells, reg_count;
/* Special way of handling 'reg' property */
if (strcmp(prop, "reg") == 0) {
reg_cells = len / sizeof(fdt_cell_t);
reg_count = udiv32(reg_cells, address_cells + size_cells);
if (umod32(reg_cells, address_cells + size_cells)) {
reg_count++;
}
reg_cells = sizeof(physical_addr_t) / sizeof(fdt_cell_t);
reg_cells += sizeof(physical_size_t) / sizeof(fdt_cell_t);
reg_count = reg_count * (reg_cells * sizeof(fdt_cell_t));
return reg_count;
}
type = vmm_devtree_estimate_attrtype(prop);
/* Special way of handling non-literal property */
if (!vmm_devtree_isliteral(type)) {
return len;
}
/* Special way of handling literal property */
lsz = vmm_devtree_literal_size(type);
if (umod32(len, lsz)) {
return udiv32(len, lsz) * lsz + lsz;
}
return len;
}
int vmm_fb_pan_display(struct vmm_fb_info *info, struct vmm_fb_var_screeninfo *var)
{
struct vmm_fb_fix_screeninfo *fix = &info->fix;
unsigned int yres = info->var.yres;
int err = 0;
if (var->yoffset > 0) {
if (var->vmode & FB_VMODE_YWRAP) {
if (!fix->ywrapstep || umod32(var->yoffset, fix->ywrapstep))
err = VMM_EINVALID;
else
yres = 0;
} else if (!fix->ypanstep || umod32(var->yoffset, fix->ypanstep))
err = VMM_EINVALID;
}
if (var->xoffset > 0 && (!fix->xpanstep ||
umod32(var->xoffset, fix->xpanstep)))
err = VMM_EINVALID;
if (err || !info->fbops->fb_pan_display ||
var->yoffset > info->var.yres_virtual - yres ||
var->xoffset > info->var.xres_virtual - info->var.xres)
return VMM_EINVALID;
if ((err = info->fbops->fb_pan_display(var, info)))
return err;
info->var.xoffset = var->xoffset;
info->var.yoffset = var->yoffset;
if (var->vmode & FB_VMODE_YWRAP)
info->var.vmode |= FB_VMODE_YWRAP;
else
info->var.vmode &= ~FB_VMODE_YWRAP;
return 0;
}
static int cmd_host_cpu_stats(struct vmm_chardev *cdev)
{
int rc;
char str[16];
u32 c, p, khz, util;
unsigned long hwid;
vmm_cprintf(cdev, "----------------------------------------"
"----------------------------------------\n");
vmm_cprintf(cdev, " %4s %14s %15s %13s %12s %16s\n",
"CPU#", "HWID", "Speed (MHz)", "Util. (%)",
"IRQs (%)", "Active VCPUs");
vmm_cprintf(cdev, "----------------------------------------"
"----------------------------------------\n");
for_each_online_cpu(c) {
vmm_cprintf(cdev, " %4d", c);
rc = vmm_smp_map_hwid(c, &hwid);
if (rc)
return rc;
vmm_snprintf(str, sizeof(str), "0x%lx", hwid);
vmm_cprintf(cdev, " %14s", str);
khz = vmm_delay_estimate_cpu_khz(c);
vmm_cprintf(cdev, " %11d.%03d",
udiv32(khz, 1000), umod32(khz, 1000));
util = udiv64(vmm_scheduler_idle_time(c) * 1000,
vmm_scheduler_get_sample_period(c));
util = (util > 1000) ? 1000 : util;
util = 1000 - util;
vmm_cprintf(cdev, " %11d.%01d",
udiv32(util, 10), umod32(util, 10));
util = udiv64(vmm_scheduler_irq_time(c) * 1000,
vmm_scheduler_get_sample_period(c));
util = (util > 1000) ? 1000 : util;
vmm_cprintf(cdev, " %10d.%01d",
udiv32(util, 10), umod32(util, 10));
util = 1;
for (p = VMM_VCPU_MIN_PRIORITY;
p <= VMM_VCPU_MAX_PRIORITY; p++) {
util += vmm_scheduler_ready_count(c, p);
}
vmm_cprintf(cdev, " %15d ", util);
vmm_cprintf(cdev, "\n");
}
vmm_cprintf(cdev, "----------------------------------------"
"----------------------------------------\n");
return VMM_OK;
}
static void cmd_host_ram_bitmap(struct vmm_chardev *cdev, int colcnt)
{
u32 ite, count, bn, bank_count = vmm_host_ram_bank_count();
physical_addr_t start;
for (bn = 0; bn < bank_count; bn++) {
if (bn) {
vmm_cprintf(cdev, "\n");
}
start = vmm_host_ram_bank_start(bn);
count = vmm_host_ram_bank_frame_count(bn);
vmm_cprintf(cdev, "Bank%02d\n", bn);
vmm_cprintf(cdev, "0 : free\n");
vmm_cprintf(cdev, "1 : used");
for (ite = 0; ite < count; ite++) {
if (umod32(ite, colcnt) == 0) {
vmm_cprintf(cdev, "\n0x%"PRIPADDR": ",
(physical_addr_t)(start + ite * VMM_PAGE_SIZE));
}
if (vmm_host_ram_frame_isfree(start + ite * VMM_PAGE_SIZE)) {
vmm_cprintf(cdev, "0");
} else {
vmm_cprintf(cdev, "1");
}
}
vmm_cprintf(cdev, "\n");
}
}
static int cmd_host_cpu_info(struct vmm_chardev *cdev)
{
int rc;
u32 c, khz;
unsigned long hwid;
char name[25];
vmm_cprintf(cdev, "%-25s: %s\n", "CPU Type", CONFIG_CPU);
vmm_cprintf(cdev, "%-25s: %d\n",
"CPU Present Count", vmm_num_present_cpus());
vmm_cprintf(cdev, "%-25s: %d\n",
"CPU Possible Count", vmm_num_possible_cpus());
vmm_cprintf(cdev, "%-25s: %u\n",
"CPU Online Count", vmm_num_online_cpus());
vmm_cprintf(cdev, "\n");
for_each_online_cpu(c) {
rc = vmm_smp_map_hwid(c, &hwid);
if (rc)
return rc;
vmm_sprintf(name, "CPU%d Hardware ID", c);
vmm_cprintf(cdev, "%-25s: 0x%lx\n", name, hwid);
vmm_sprintf(name, "CPU%d Estimated Speed", c);
khz = vmm_delay_estimate_cpu_khz(c);
vmm_cprintf(cdev, "%-25s: %d.%03d MHz\n",
name, udiv32(khz, 1000), umod32(khz, 1000));
}
vmm_cprintf(cdev, "\n");
arch_cpu_print_info(cdev);
return VMM_OK;
}
void samsung_lowlevel_init(virtual_addr_t base, u32 baudrate, u32 input_clock)
{
unsigned int divider;
unsigned int temp;
unsigned int remainder;
/* First, disable everything */
vmm_out_le16((void *)(base + S3C2410_UCON), 0);
/*
* Set baud rate
*
* UBRDIV = (UART_CLK / (16 * BAUD_RATE)) - 1
* DIVSLOT = MOD(UART_CLK / BAUD_RATE, 16)
*/
temp = udiv32(input_clock, baudrate);
divider = udiv32(temp, 16) - 1;
remainder = umod32(temp, 16);
vmm_out_le16((void *)(base + S3C2410_UBRDIV), (u16)
divider);
vmm_out_8((void *)(base + S3C2443_DIVSLOT), (u8)
remainder);
/* Set the UART to be 8 bits, 1 stop bit, no parity */
vmm_out_le32((void *)(base + S3C2410_ULCON),
S3C2410_LCON_CS8 | S3C2410_LCON_PNONE);
/* enable FIFO, set RX and TX trigger */
vmm_out_le32((void *)(base + S3C2410_UFCON), S3C2410_UFCON_DEFAULT);
/* enable the UART */
vmm_out_le32((void *)(base + S3C2410_UCON), S3C2410_UCON_DEFAULT);
}
static void cmd_host_vapool_bitmap(struct vmm_chardev *cdev, int colcnt)
{
u32 ite, total = vmm_host_vapool_total_page_count();
virtual_addr_t base = vmm_host_vapool_base();
vmm_cprintf(cdev, "0 : free\n");
vmm_cprintf(cdev, "1 : used");
for (ite = 0; ite < total; ite++) {
if (umod32(ite, colcnt) == 0) {
if (sizeof(u64) == sizeof(virtual_addr_t)) {
vmm_cprintf(cdev, "\n0x%016llx: ",
base + ite * VMM_PAGE_SIZE);
} else {
vmm_cprintf(cdev, "\n0x%08x: ",
base + ite * VMM_PAGE_SIZE);
}
}
if (vmm_host_vapool_page_isfree(base + ite * VMM_PAGE_SIZE)) {
vmm_cprintf(cdev, "0");
} else {
vmm_cprintf(cdev, "1");
}
}
vmm_cprintf(cdev, "\n");
}
struct vring_used_elem *virtio_queue_set_used_elem(struct virtio_queue *vq,
u32 head, u32 len)
{
struct vring_used_elem *used_elem;
if (!vq->addr) {
return NULL;
}
used_elem = &vq->vring.used->ring[
umod32(vq->vring.used->idx, vq->vring.num)];
used_elem->id = head;
used_elem->len = len;
/*
* Use wmb to assure that used elem was updated with head and len.
* We need a wmb here since we can't advance idx unless we're ready
* to pass the used element to the guest.
*/
arch_wmb();
vq->vring.used->idx++;
/*
* Use wmb to assure used idx has been increased before we signal the guest.
* Without a wmb here the guest may ignore the queue since it won't see
* an updated idx.
*/
arch_wmb();
return used_elem;
}
u16 virtio_queue_pop(struct virtio_queue *vq)
{
if (!vq->addr) {
return 0;
}
return vq->vring.avail->ring[
umod32(vq->last_avail_idx++, vq->vring.num)];
}
static void cmd_host_cpu_stats(struct vmm_chardev *cdev)
{
u32 c, p, khz, util;
vmm_cprintf(cdev, "----------------------------------------"
"-------------------------\n");
vmm_cprintf(cdev, " %4s %15s %13s %12s %16s\n",
"CPU#", "Speed (MHz)", "Util. (%)",
"IRQs (%)", "Active VCPUs");
vmm_cprintf(cdev, "----------------------------------------"
"-------------------------\n");
for_each_online_cpu(c) {
vmm_cprintf(cdev, " %4d", c);
khz = vmm_delay_estimate_cpu_khz(c);
vmm_cprintf(cdev, " %11d.%03d",
udiv32(khz, 1000), umod32(khz, 1000));
util = udiv64(vmm_scheduler_idle_time(c) * 1000,
vmm_scheduler_get_sample_period(c));
util = (util > 1000) ? 1000 : util;
util = 1000 - util;
vmm_cprintf(cdev, " %11d.%01d",
udiv32(util, 10), umod32(util, 10));
util = udiv64(vmm_scheduler_irq_time(c) * 1000,
vmm_scheduler_get_sample_period(c));
util = (util > 1000) ? 1000 : util;
vmm_cprintf(cdev, " %10d.%01d",
udiv32(util, 10), umod32(util, 10));
util = 1;
for (p = VMM_VCPU_MIN_PRIORITY; p <= VMM_VCPU_MAX_PRIORITY; p++) {
util += vmm_scheduler_ready_count(c, p);
}
vmm_cprintf(cdev, " %15d ", util);
vmm_cprintf(cdev, "\n");
}
vmm_cprintf(cdev, "----------------------------------------"
"-------------------------\n");
}
static void cmd_host_cpu_info(struct vmm_chardev *cdev)
{
u32 c, khz;
char name[25];
vmm_cprintf(cdev, "%-25s: %s\n", "CPU Type", CONFIG_CPU);
vmm_cprintf(cdev, "%-25s: %d\n", "CPU Present Count", vmm_num_present_cpus());
vmm_cprintf(cdev, "%-25s: %d\n", "CPU Possible Count", vmm_num_possible_cpus());
vmm_cprintf(cdev, "%-25s: %u\n", "CPU Online Count", vmm_num_online_cpus());
for_each_online_cpu(c) {
khz = vmm_delay_estimate_cpu_khz(c);
vmm_sprintf(name, "CPU%d Speed", c);
vmm_cprintf(cdev, "%-25s: %d.%d MHz (Estimated)\n", name,
udiv32(khz, 1000), umod32(khz, 1000));
}
arch_cpu_print_info(cdev);
}
void vmm_cfb_imageblit(struct vmm_fb_info *p, const struct vmm_fb_image *image)
{
u32 fgcolor, bgcolor, start_index, bitstart, pitch_index = 0;
u32 bpl = sizeof(u32), bpp = p->var.bits_per_pixel;
u32 width = image->width;
u32 dx = image->dx, dy = image->dy;
u8 *dst1;
if (p->state != FBINFO_STATE_RUNNING)
return;
bitstart = (dy * p->fix.line_length * 8) + (dx * bpp);
start_index = bitstart & (32 - 1);
pitch_index = (p->fix.line_length & (bpl - 1)) * 8;
bitstart /= 8;
bitstart &= ~(bpl - 1);
dst1 = (u8 *)(p->screen_base + bitstart);
if (p->fbops->fb_sync)
p->fbops->fb_sync(p);
if (image->depth == 1) {
if (p->fix.visual == FB_VISUAL_TRUECOLOR ||
p->fix.visual == FB_VISUAL_DIRECTCOLOR) {
fgcolor = ((u32*)(p->pseudo_palette))[image->fg_color];
bgcolor = ((u32*)(p->pseudo_palette))[image->bg_color];
} else {
fgcolor = image->fg_color;
bgcolor = image->bg_color;
}
if (umod32(32, bpp) == 0 && !start_index && !pitch_index &&
((width & (udiv32(32,bpp)-1)) == 0) &&
bpp >= 8 && bpp <= 32)
fast_imageblit(image, p, dst1, fgcolor, bgcolor);
else
slow_imageblit(image, p, dst1, fgcolor, bgcolor,
start_index, pitch_index);
} else
color_imageblit(image, p, dst1, start_index, pitch_index);
}
void imx_lowlevel_init(virtual_addr_t base, u32 baudrate, u32 input_clock)
{
unsigned int temp = vmm_readl((void *)(base + UCR1));
#if 0
unsigned int divider;
unsigned int remainder;
#endif
/* First, disable everything */
temp &= ~UCR1_UARTEN;
vmm_writel(temp, (void *)base + UCR1);
#if 0
/*
* Set baud rate
*
* UBRDIV = (UART_CLK / (16 * BAUD_RATE)) - 1
* DIVSLOT = MOD(UART_CLK / BAUD_RATE, 16)
*/
temp = udiv32(input_clock, baudrate);
divider = udiv32(temp, 16) - 1;
remainder = umod32(temp, 16);
vmm_out_le16((void *)(base + S3C2410_UBRDIV), (u16)
divider);
vmm_out_8((void *)(base + S3C2443_DIVSLOT), (u8)
remainder);
/* Set the UART to be 8 bits, 1 stop bit, no parity */
vmm_out_le32((void *)(base + S3C2410_ULCON),
S3C2410_LCON_CS8 | S3C2410_LCON_PNONE);
/* enable FIFO, set RX and TX trigger */
vmm_out_le32((void *)(base + S3C2410_UFCON), S3C2410_UFCON_DEFAULT);
#else
/* enable the UART */
temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
vmm_writel(temp, (void *)(base + UCR1));
#endif
}
void imx_lowlevel_init(virtual_addr_t base, u32 baudrate, u32 input_clock)
{
unsigned int temp = vmm_readl((void *)(base + UCR1));
#if 0
unsigned int divider;
unsigned int remainder;
#endif
/* First, disable everything */
temp &= ~UCR1_UARTEN;
vmm_writel(temp, (void *)base + UCR1);
#if 0
/*
* Set baud rate
*
* UBRDIV = (UART_CLK / (16 * BAUD_RATE)) - 1
* DIVSLOT = MOD(UART_CLK / BAUD_RATE, 16)
*/
temp = udiv32(input_clock, baudrate);
divider = udiv32(temp, 16) - 1;
remainder = umod32(temp, 16);
vmm_out_le16((void *)(base + S3C2410_UBRDIV), (u16)
divider);
vmm_out_8((void *)(base + S3C2443_DIVSLOT), (u8)
remainder);
/* Set the UART to be 8 bits, 1 stop bit, no parity */
vmm_out_le32((void *)(base + S3C2410_ULCON),
S3C2410_LCON_CS8 | S3C2410_LCON_PNONE);
/* enable FIFO, set RX and TX trigger */
vmm_out_le32((void *)(base + S3C2410_UFCON), S3C2410_UFCON_DEFAULT);
#else
/* disable all UCR2 related interrupts */
temp = vmm_readl((void *)(base + UCR2));
vmm_writel(temp & ~(UCR2_ATEN | UCR2_ESCI | UCR2_RTSEN),
(void *)(base + UCR2));
/* disable all UCR3 related interrupts */
temp = vmm_readl((void *)(base + UCR3));
vmm_writel(temp &
~(UCR3_RXDSEN | UCR3_DTREN | UCR3_FRAERREN | UCR3_TIMEOUTEN |
UCR3_AIRINTEN | UCR3_AWAKEN | UCR3_DTRDEN),
(void *)(base + UCR3));
/* disable all UCR4 related interrupts */
temp = vmm_readl((void *)(base + UCR4));
vmm_writel(temp &
~(UCR4_DREN | UCR4_TCEN | UCR4_ENIRI | UCR4_WKEN | UCR4_BKEN
| UCR4_OREN), (void *)(base + UCR4));
/* trigger interrupt when there is 1 by in the RXFIFO */
temp = vmm_readl((void *)(base + UFCR));
vmm_writel((temp & 0xFFC0) | 1, (void *)(base + UFCR));
/* enable the UART and the receive interrupt */
temp = UCR1_RRDYEN | UCR1_UARTEN;
vmm_writel(temp, (void *)(base + UCR1));
#endif
}
static void libfdt_property_read(const char *prop, void *dst, void *src,
u32 address_cells, u32 size_cells, u32 len)
{
int tlen;
u32 pos, type, lsz, val32, reg, reg_cells, reg_count;
u64 val64;
/* Special way of handling 'reg' property */
if (strcmp(prop, "reg") == 0) {
reg_cells = len / sizeof(fdt_cell_t);
reg_count = udiv32(reg_cells, address_cells + size_cells);
if (umod32(reg_cells, address_cells + size_cells)) {
reg_count++;
}
for (reg = 0; reg < reg_count; reg++) {
if (address_cells == 2) {
*((physical_addr_t *)dst) =
(physical_addr_t)LIBFDT_DATA64(src);
} else {
*((physical_addr_t *)dst) =
(physical_addr_t)LIBFDT_DATA32(src);
}
dst += sizeof(physical_addr_t);
src += address_cells * sizeof(fdt_cell_t);
if (size_cells == 2) {
*((physical_size_t *)dst) =
(physical_size_t)LIBFDT_DATA64(src);
} else {
*((physical_size_t *)dst) =
(physical_size_t)LIBFDT_DATA32(src);
}
dst += sizeof(physical_size_t);
src += size_cells * sizeof(fdt_cell_t);
}
return;
}
type = vmm_devtree_estimate_attrtype(prop);
/* Special way of handling non-literal property */
if (!vmm_devtree_isliteral(type)) {
memcpy(dst, src, len);
return;
}
/* Special way of handling literal property */
lsz = vmm_devtree_literal_size(type);
if (lsz == 4) {
pos = 0;
tlen = len;
while (tlen > 0) {
if (tlen < 4) {
break;
}
val32 = ((u32 *)src)[pos];
((u32 *)dst)[pos] = LIBFDT_DATA32(&val32);
pos++;
tlen -= 4;
}
} else if (lsz == 8) {
pos = 0;
tlen = len;
while (tlen > 0) {
if (tlen < 4) {
break;
} else if (tlen == 4) {
((u64 *)dst)[pos] =
LIBFDT_DATA32(&((u32 *)src)[pos*2]);
break;
}
val64 = ((u64 *)src)[pos];
((u64 *)dst)[pos] = LIBFDT_DATA64(&val64);
pos++;
tlen -= 8;
}
}
}
