void libAICA_TimeStep() { for (int i=0;i<3;i++) timers[i].StepTimer(1); SCIPD->SAMPLE_DONE=1; if (settings.aica.NoBatch) AICA_Sample(); //Make sure sh4/arm interrupt system is up to date :) update_arm_interrupts(); UpdateSh4Ints(); }
//Mainloop void FASTCALL UpdateAICA(u32 Samples) { while(Samples>0) { Samples--; AICA_Sample(); SCIPD->SAMPLE_DONE=1; for (int i=0;i<3;i++) timers[i].StepTimer(); } //Make sure sh4/arm interrupt system is up to date :) update_arm_interrupts(); UpdateSh4Ints(); }
void WriteAicaReg(u32 reg,u32 data) { switch (reg) { case SCIPD_addr: verify(sz!=1); if (data & (1<<5)) { SCIPD->SCPU=1; update_arm_interrupts(); } //Read only return; case SCIRE_addr: { verify(sz!=1); SCIPD->full&=~(data /*& SCIEB->full*/ ); //is the & SCIEB->full needed ? doesn't seem like it data=0;//Write only update_arm_interrupts(); } break; case MCIPD_addr: if (data & (1<<5)) { verify(sz!=1); MCIPD->SCPU=1; UpdateSh4Ints(); } //Read only return; case MCIRE_addr: { verify(sz!=1); MCIPD->full&=~data; UpdateSh4Ints(); //Write only } break; case TIMER_A: WriteMemArr(aica_reg,reg,data,sz); timers[0].RegisterWrite(); break; case TIMER_B: WriteMemArr(aica_reg,reg,data,sz); timers[1].RegisterWrite(); break; case TIMER_C: WriteMemArr(aica_reg,reg,data,sz); timers[2].RegisterWrite(); break; default: WriteMemArr(aica_reg,reg,data,sz); break; } }