static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val) { TCXState *s = opaque; switch (addr) { case 0: s->dac_index = val >> 24; s->dac_state = 0; break; case 4: switch (s->dac_state) { case 0: s->r[s->dac_index] = val >> 24; update_palette_entries(s, s->dac_index, s->dac_index + 1); s->dac_state++; break; case 1: s->g[s->dac_index] = val >> 24; update_palette_entries(s, s->dac_index, s->dac_index + 1); s->dac_state++; break; case 2: s->b[s->dac_index] = val >> 24; update_palette_entries(s, s->dac_index, s->dac_index + 1); s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement default: s->dac_state = 0; break; } break; default: break; } return; }
static void tcx_dac_writel(void *opaque, hwaddr addr, uint64_t val, unsigned size) { TCXState *s = opaque; switch (addr) { case 0: s->dac_index = val >> 24; s->dac_state = 0; break; case 4: switch (s->dac_state) { case 0: s->r[s->dac_index] = val >> 24; update_palette_entries(s, s->dac_index, s->dac_index + 1); s->dac_state++; break; case 1: s->g[s->dac_index] = val >> 24; update_palette_entries(s, s->dac_index, s->dac_index + 1); s->dac_state++; break; case 2: s->b[s->dac_index] = val >> 24; update_palette_entries(s, s->dac_index, s->dac_index + 1); s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement default: s->dac_state = 0; break; } break; default: break; } }
static int tcx_load(QEMUFile *f, void *opaque, int version_id) { TCXState *s = opaque; uint32_t dummy; if (version_id != 3 && version_id != 4) return -EINVAL; if (version_id == 3) { qemu_get_be32s(f, &dummy); qemu_get_be32s(f, &dummy); qemu_get_be32s(f, &dummy); } qemu_get_be16s(f, &s->height); qemu_get_be16s(f, &s->width); qemu_get_be16s(f, &s->depth); qemu_get_buffer(f, s->r, 256); qemu_get_buffer(f, s->g, 256); qemu_get_buffer(f, s->b, 256); qemu_get_8s(f, &s->dac_index); qemu_get_8s(f, &s->dac_state); update_palette_entries(s, 0, 256); if (s->depth == 24) tcx24_invalidate_display(s); else tcx_invalidate_display(s); return 0; }
static int vmstate_tcx_post_load(void *opaque, int version_id) { TCXState *s = opaque; update_palette_entries(s, 0, 256); if (s->depth == 24) { tcx24_set_dirty(s); } else { tcx_set_dirty(s); } return 0; }
static void tcx_reset(DeviceState *d) { TCXState *s = container_of(d, TCXState, busdev.qdev); /* Initialize palette */ memset(s->r, 0, 256); memset(s->g, 0, 256); memset(s->b, 0, 256); s->r[255] = s->g[255] = s->b[255] = 255; update_palette_entries(s, 0, 256); memset(s->vram, 0, MAXX*MAXY); memory_region_reset_dirty(&s->vram_mem, 0, MAXX * MAXY * (1 + 4 + 4), DIRTY_MEMORY_VGA); s->dac_index = 0; s->dac_state = 0; }
static void tcx_reset(DeviceState *d) { TCXState *s = container_of(d, TCXState, busdev.qdev); /* Initialize palette */ memset(s->r, 0, 256); memset(s->g, 0, 256); memset(s->b, 0, 256); s->r[255] = s->g[255] = s->b[255] = 255; update_palette_entries(s, 0, 256); memset(s->vram, 0, MAXX*MAXY); cpu_physical_memory_reset_dirty(s->vram_offset, s->vram_offset + MAXX * MAXY * (1 + 4 + 4), VGA_DIRTY_FLAG); s->dac_index = 0; s->dac_state = 0; }
static void tcx_reset(void *opaque) { TCXState *s = opaque; /* Initialize palette */ memset(s->r, 0, 256); memset(s->g, 0, 256); memset(s->b, 0, 256); s->r[255] = s->g[255] = s->b[255] = 255; update_palette_entries(s, 0, 256); memset(s->vram, 0, MAXX*MAXY); cpu_physical_memory_reset_dirty(s->vram_offset, s->vram_offset + MAXX * MAXY * (1 + 4 + 4), VGA_DIRTY_FLAG); s->dac_index = 0; s->dac_state = 0; }