int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
struct usb_ehci *ehci;
enable_usboh3_clk(1);
mdelay(1);
/* Do board specific initialization */
board_ehci_hcd_init(CONFIG_MXC_USB_PORT);
#if CONFIG_MXC_USB_PORT == 0 || CONFIG_MXC_USB_PORT == 1
/* USB OTG or Host 1 */
usb_power_config(CONFIG_MXC_USB_PORT);
usb_oc_config(CONFIG_MXC_USB_PORT);
usb_internal_phy_clock_gate(CONFIG_MXC_USB_PORT, 1);
usb_phy_enable(CONFIG_MXC_USB_PORT);
#else
#error "MXC USB port not yet supported"
#endif
ehci = (struct usb_ehci *)(USBOH3_USB_BASE_ADDR +
(0x200 * CONFIG_MXC_USB_PORT));
*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
setbits_le32(&ehci->usbmode, CM_HOST);
__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
setbits_le32(&ehci->portsc, USB_EN);
mdelay(10);
return 0;
}
int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
(0x200 * index));
if (index > 3)
return -EINVAL;
enable_usboh3_clk(1);
mdelay(1);
/* Do board specific initialization */
board_ehci_hcd_init(index);
usb_power_config(index);
usb_oc_config(index);
usb_internal_phy_clock_gate(index, 1);
usb_phy_enable(index, ehci);
*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
board_ehci_power(index, (init == USB_INIT_DEVICE) ? 0 : 1);
if (init == USB_INIT_DEVICE)
return 0;
setbits_le32(&ehci->usbmode, CM_HOST);
__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
setbits_le32(&ehci->portsc, USB_EN);
mdelay(10);
return 0;
}
void usb_device_init(
const uint_fast8_t device_ordinal,
usb_device_t* const device
) {
if( device_ordinal == 0 ) {
usb_device_usb0 = device;
usb_phy_enable();
usb_controller_reset();
usb_controller_set_device_mode();
// Set interrupt threshold interval to 0
USB0_USBCMD_D &= ~USB0_USBCMD_D_ITC_MASK;
// Configure endpoint list address
USB0_ENDPOINTLISTADDR = (uint32_t)usb_qh;
// Enable interrupts
USB0_USBINTR_D =
USB0_USBINTR_D_UE
| USB0_USBINTR_D_UEE
| USB0_USBINTR_D_PCE
| USB0_USBINTR_D_URE
//| USB0_USBINTR_D_SRE
| USB0_USBINTR_D_SLE
//| USB0_USBINTR_D_NAKE
;
}
}
int usbotg_init(struct platform_device *pdev)
{
struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
struct fsl_xcvr_ops *xops;
pr_debug("%s: pdev=0x%p pdata=0x%p\n", __func__, pdev, pdata);
xops = fsl_usb_get_xcvr(pdata->transceiver);
if (!xops) {
printk(KERN_ERR "DR transceiver ops missing\n");
return -EINVAL;
}
pdata->xcvr_ops = xops;
pdata->xcvr_type = xops->xcvr_type;
pdata->pdev = pdev;
otg_used = 0;
if (!otg_used) {
pr_debug("%s: grab pins\n", __func__);
if (xops->init)
xops->init(xops);
usb_phy_enable();
}
otg_used++;
pr_debug("%s: success\n", __func__);
return 0;
}
int fsl_usb_host_init(struct platform_device *pdev)
{
struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
struct fsl_xcvr_ops *xops;
u32 tmp;
void __iomem *phy_reg = IO_ADDRESS(pdata->phy_regs);
pr_debug("%s: pdev=0x%p pdata=0x%p\n", __func__, pdev, pdata);
xops = fsl_usb_get_xcvr(pdata->transceiver);
if (!xops) {
printk(KERN_ERR "%s transceiver ops missing\n", pdata->name);
return -EINVAL;
}
pdata->xcvr_ops = xops;
pdata->xcvr_type = xops->xcvr_type;
pdata->pdev = pdev;
if (xops->init)
xops->init(xops);
usb_phy_enable(pdata);
/* enable FS/LS device */
tmp = __raw_readl(phy_reg + HW_USBPHY_CTRL);
tmp |= (BM_USBPHY_CTRL_ENUTMILEVEL2 | BM_USBPHY_CTRL_ENUTMILEVEL3);
__raw_writel(tmp, phy_reg + HW_USBPHY_CTRL);
pr_debug("%s: %s success\n", __func__, pdata->name);
return 0;
}
/* Notes: configure USB clock*/
static int usbotg_init_ext(struct platform_device *pdev)
{
struct clk *usb_clk;
u32 ret;
/* at mx6q: this clock is AHB clock for usb core */
usb_clk = clk_get(NULL, "usboh3_clk");
clk_enable(usb_clk);
usb_oh3_clk = usb_clk;
usb_clk = clk_get(NULL, "usb_phy1_clk");
clk_enable(usb_clk);
usb_phy1_clk = usb_clk;
ret = usbotg_init(pdev);
if (ret) {
printk(KERN_ERR "otg init fails......\n");
return ret;
}
if (!otg_used) {
usbotg_internal_phy_clock_gate(true);
usb_phy_enable(pdev->dev.platform_data);
/*after the phy reset,can not read the readingvalue for id/vbus at
* the register of otgsc ,cannot read at once ,need delay 3 ms
*/
mdelay(3);
}
otg_used++;
return ret;
}
static int fsl_usb_host_init_ext(struct platform_device *pdev)
{
static void __iomem *anatop_base_addr = MX6_IO_ADDRESS(ANATOP_BASE_ADDR);
int ret;
struct clk *usb_clk;
/* The PLL's power and output to usb for host 1
* is totally controlled by IC, so the Software only needs
* to enable them at initializtion. */
__raw_writel(BM_ANADIG_USB2_PLL_480_CTRL_BYPASS,
anatop_base_addr + HW_ANADIG_USB2_PLL_480_CTRL_CLR);
__raw_writel(BM_ANADIG_USB2_PLL_480_CTRL_ENABLE \
| BM_ANADIG_USB2_PLL_480_CTRL_POWER \
| BM_ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS, \
anatop_base_addr + HW_ANADIG_USB2_PLL_480_CTRL_SET);
usb_clk = clk_get(NULL, "usboh3_clk");
clk_enable(usb_clk);
usb_oh3_clk = usb_clk;
ret = fsl_usb_host_init(pdev);
if (ret) {
printk(KERN_ERR "host1 init fails......\n");
clk_disable(usb_oh3_clk);
clk_put(usb_oh3_clk);
return ret;
}
usbh1_internal_phy_clock_gate(true);
usb_phy_enable(pdev->dev.platform_data);
return 0;
}
int MSCenable(void){
USBD_API_INIT_PARAM_T usb_param;
USB_CORE_DESCS_T desc;
ErrorCode_t ret = LPC_OK;
USB_CORE_CTRL_T *pCtrl;
flashInit();
usb_clock_init();
usb_phy_enable();
/* Init USB API structure */
g_pUsbApi = (const USBD_API_T *) LPC_ROM_API->usbdApiBase;
/* initialize call back structures */
memset((void *) &usb_param, 0, sizeof(USBD_API_INIT_PARAM_T));
usb_param.usb_reg_base = LPC_USB_BASE;
usb_param.mem_base = USB_STACK_MEM_BASE;
usb_param.mem_size = USB_STACK_MEM_SIZE;
usb_param.max_num_ep = 2;
/* Set the USB descriptors */
desc.device_desc = (uint8_t *) USB_msc_DeviceDescriptor;
desc.string_desc = (uint8_t *) USB_msc_StringDescriptor;
desc.high_speed_desc = USB_msc_HsConfigDescriptor;
desc.full_speed_desc = USB_msc_FsConfigDescriptor;
desc.device_qualifier = (uint8_t *) USB_msc_DeviceQualifier;
/* USB Initialization */
ret = USBD_API->hw->Init(&g_hUsb, &desc, &usb_param);
if (ret == LPC_OK) {
/* WORKAROUND for artf45032 ROM driver BUG:
Due to a race condition there is the chance that a second NAK event will
occur before the default endpoint0 handler has completed its preparation
of the DMA engine for the first NAK event. This can cause certain fields
in the DMA descriptors to be in an invalid state when the USB controller
reads them, thereby causing a hang.
*/
pCtrl = (USB_CORE_CTRL_T *) g_hUsb; /* convert the handle to control structure */
g_Ep0BaseHdlr = pCtrl->ep_event_hdlr[0];/* retrieve the default EP0_OUT handler */
pCtrl->ep_event_hdlr[0] = EP0_patch;/* set our patch routine as EP0_OUT handler */
ret = mscDisk_init(g_hUsb, &desc, &usb_param);
if (ret == LPC_OK) {
/* enable USB interrrupts */
nvic_enable_irq(NVIC_USB0_IRQ);
/* now connect */
USBD_API->hw->Connect(g_hUsb, 1);
return 0;
}
}
return 1;
}
void usb_device_init(
usb_device_t* const device
) {
if( device->controller == 0 ) {
usb_devices[0] = device;
usb_phy_enable();
usb_controller_reset(device);
usb_controller_set_device_mode(device);
// Set interrupt threshold interval to 0
USB0_USBCMD_D &= ~USB0_USBCMD_D_ITC_MASK;
// Configure endpoint list address
USB0_ENDPOINTLISTADDR = (uint32_t)usb_qh[0];
// Enable interrupts
USB0_USBINTR_D =
USB0_USBINTR_D_UE
| USB0_USBINTR_D_UEE
| USB0_USBINTR_D_PCE
| USB0_USBINTR_D_URE
//| USB0_USBINTR_D_SRE
| USB0_USBINTR_D_SLE
//| USB0_USBINTR_D_NAKE
;
}
if( device->controller == 1 ) {
usb_devices[1] = device;
//usb_phy_enable();
usb_controller_reset(device);
usb_controller_set_device_mode(device);
// Set interrupt threshold interval to 0
USB1_USBCMD_D &= ~USB0_USBCMD_D_ITC_MASK;
// Configure endpoint list address
USB1_ENDPOINTLISTADDR = (uint32_t)usb_qh[1];
// Enable interrupts
USB1_USBINTR_D =
USB1_USBINTR_D_UE
| USB1_USBINTR_D_UEE
| USB1_USBINTR_D_PCE
| USB1_USBINTR_D_URE
//| USB1_USBINTR_D_SRE
| USB1_USBINTR_D_SLE
//| USB1_USBINTR_D_NAKE
;
}
}
int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
enum usb_init_type type;
#if defined(CONFIG_MX6)
u32 controller_spacing = 0x200;
#elif defined(CONFIG_MX7)
u32 controller_spacing = 0x10000;
#endif
struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
(controller_spacing * index));
int ret;
if (index > 3)
return -EINVAL;
enable_usboh3_clk(1);
mdelay(1);
/* Do board specific initialization */
ret = board_ehci_hcd_init(index);
if (ret)
return ret;
usb_power_config(index);
usb_oc_config(index);
#if defined(CONFIG_MX6)
usb_internal_phy_clock_gate(index, 1);
usb_phy_enable(index, ehci);
#endif
type = board_usb_phy_mode(index);
*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
if ((type == init) || (type == USB_INIT_DEVICE))
board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
if (type != init)
return -ENODEV;
if (type == USB_INIT_DEVICE)
return 0;
setbits_le32(&ehci->usbmode, CM_HOST);
writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
setbits_le32(&ehci->portsc, USB_EN);
mdelay(10);
return 0;
}
int ehci_vf_common_init(struct usb_ehci *ehci, int index)
{
int ret;
/* Do board specific initialisation */
ret = board_ehci_hcd_init(index);
if (ret)
return ret;
usb_power_config(index);
usb_oc_config(index);
usb_internal_phy_clock_gate(index);
usb_phy_enable(index, ehci);
return 0;
}
static int fsl_usb_host_init_ext(struct platform_device *pdev)
{
int ret;
struct clk *usb_clk;
usb_clk = clk_get(NULL, "usboh3_clk");
clk_enable(usb_clk);
usb_oh3_clk = usb_clk;
ret = fsl_usb_host_init(pdev);
if (ret) {
printk(KERN_ERR "host1 init fails......\n");
clk_disable(usb_oh3_clk);
clk_put(usb_oh3_clk);
return ret;
}
usbh1_internal_phy_clock_gate(true);
usb_phy_enable(pdev->dev.platform_data);
return 0;
}
static int fsl_usb_host_init_ext(struct platform_device *pdev)
{
int ret;
struct clk *usb_clk;
void __iomem *anatop_base_addr = MX6_IO_ADDRESS(ANATOP_BASE_ADDR);
usb_clk = clk_get(NULL, "usboh3_clk");
clk_enable(usb_clk);
usb_oh3_clk = usb_clk;
ret = fsl_usb_host_init(pdev);
if (ret) {
printk(KERN_ERR "host1 init fails......\n");
return ret;
}
usbh1_internal_phy_clock_gate(true);
usb_phy_enable(pdev->dev.platform_data);
usb_stop_mode_lock();
if (usb_stop_mode_refcount(true) == 1)
__raw_writel(BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG, anatop_base_addr + HW_ANADIG_ANA_MISC0_SET);
usb_stop_mode_unlock();
return 0;
}
int ehci_mx6_common_init(struct usb_ehci *ehci, int index)
{
int ret;
enable_usboh3_clk(1);
mdelay(1);
/* Do board specific initialization */
ret = board_ehci_hcd_init(index);
if (ret)
return ret;
usb_power_config(index);
usb_oc_config(index);
#if defined(CONFIG_MX6)
usb_internal_phy_clock_gate(index, 1);
usb_phy_enable(index, ehci);
#endif
return 0;
}
int usbotg_init(struct platform_device *pdev)
{
struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
struct fsl_xcvr_ops *xops;
u32 tmp;
pr_debug("%s: pdev=0x%p pdata=0x%p\n", __func__, pdev, pdata);
xops = fsl_usb_get_xcvr(pdata->transceiver);
if (!xops) {
printk(KERN_ERR "DR transceiver ops missing\n");
return -EINVAL;
}
pdata->xcvr_ops = xops;
pdata->xcvr_type = xops->xcvr_type;
pdata->pdev = pdev;
otg_used = 0;
if (!otg_used) {
pr_debug("%s: grab pins\n", __func__);
if (xops->init)
xops->init(xops);
usb_phy_enable(pdata);
}
if (pdata->operating_mode == FSL_USB2_DR_HOST) {
/* enable FS/LS device */
tmp = __raw_readl(IO_ADDRESS(pdata->phy_regs) + HW_USBPHY_CTRL);
tmp |= (BM_USBPHY_CTRL_ENUTMILEVEL2 |
BM_USBPHY_CTRL_ENUTMILEVEL3);
__raw_writel(tmp, IO_ADDRESS(pdata->phy_regs) + HW_USBPHY_CTRL);
}
otg_used++;
pr_debug("%s: success\n", __func__);
return 0;
}
