/**
* dwc3_core_soft_reset_after_phy_init - Issues core soft reset
* and PHY reset for HW versions which require core reset after
* PHY initialization and reset
* @dwc: pointer to our context structure
*/
static void dwc3_core_soft_reset_after_phy_init(struct dwc3 *dwc)
{
u32 reg;
/* Reset PHYs */
usb_phy_reset(dwc->usb3_phy);
usb_phy_reset(dwc->usb2_phy);
msleep(100);
/* Bring up PHYs */
usb_phy_init(dwc->usb2_phy);
usb_phy_init(dwc->usb3_phy);
msleep(100);
/* Put Core in Reset */
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
reg |= DWC3_GCTL_CORESOFTRESET;
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
dwc3_notify_event(dwc, DWC3_CONTROLLER_RESET_EVENT);
msleep(100);
/* Take Core out of reset state */
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
reg &= ~DWC3_GCTL_CORESOFTRESET;
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
dwc3_notify_event(dwc, DWC3_CONTROLLER_POST_RESET_EVENT);
}
static int dwc3_resume(struct device *dev)
{
struct dwc3 *dwc = dev_get_drvdata(dev);
unsigned long flags;
usb_phy_init(dwc->usb3_phy);
usb_phy_init(dwc->usb2_phy);
msleep(100);
spin_lock_irqsave(&dwc->lock, flags);
dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
switch (dwc->mode) {
case DWC3_MODE_DEVICE:
case DWC3_MODE_DRD:
dwc3_gadget_resume(dwc);
/* FALLTHROUGH */
case DWC3_MODE_HOST:
default:
/* do nothing */
break;
}
spin_unlock_irqrestore(&dwc->lock, flags);
pm_runtime_disable(dev);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
return 0;
}
/**
* dwc3_core_soft_reset - Issues core soft reset and PHY reset
* @dwc: pointer to our context structure
*/
static int dwc3_core_soft_reset(struct dwc3 *dwc)
{
u32 reg;
int retries = 1000;
int ret;
usb_phy_init(dwc->usb2_phy);
usb_phy_init(dwc->usb3_phy);
ret = phy_init(dwc->usb2_generic_phy);
if (ret < 0)
return ret;
ret = phy_init(dwc->usb3_generic_phy);
if (ret < 0) {
phy_exit(dwc->usb2_generic_phy);
return ret;
}
/*
* We're resetting only the device side because, if we're in host mode,
* XHCI driver will reset the host block. If dwc3 was configured for
* host-only mode, then we can return early.
*/
if (dwc->dr_mode == USB_DR_MODE_HOST || dwc->is_hibernated == true)
return 0;
if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
return 0;
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
reg |= DWC3_DCTL_CSFTRST;
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
do {
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
if (!(reg & DWC3_DCTL_CSFTRST))
goto done;
udelay(1);
} while (--retries);
phy_exit(dwc->usb3_generic_phy);
phy_exit(dwc->usb2_generic_phy);
return -ETIMEDOUT;
done:
/*
* For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared,
* we must wait at least 50ms before accessing the PHY domain
* (synchronization delay). DWC_usb31 programming guide section 1.3.2.
*/
if (dwc3_is_usb31(dwc))
msleep(50);
return 0;
}
/**
* dwc3_core_soft_reset - Issues core soft reset and PHY reset
* @dwc: pointer to our context structure
*/
static int dwc3_core_soft_reset(struct dwc3 *dwc)
{
u32 reg;
int ret;
/* Before Resetting PHY, put Core in Reset */
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
reg |= DWC3_GCTL_CORESOFTRESET;
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
/* Assert USB3 PHY reset */
reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
/* Assert USB2 PHY reset */
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
usb_phy_init(dwc->usb2_phy);
usb_phy_init(dwc->usb3_phy);
ret = phy_init(dwc->usb2_generic_phy);
if (ret < 0)
return ret;
ret = phy_init(dwc->usb3_generic_phy);
if (ret < 0) {
phy_exit(dwc->usb2_generic_phy);
return ret;
}
mdelay(100);
/* Clear USB3 PHY reset */
reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
/* Clear USB2 PHY reset */
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
mdelay(100);
/* After PHYs are stable we can take Core out of reset state */
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
reg &= ~DWC3_GCTL_CORESOFTRESET;
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
return 0;
}
/**
* dwc3_core_soft_reset - Issues core soft reset and PHY reset
* @dwc: pointer to our context structure
*/
static void dwc3_core_soft_reset(struct dwc3 *dwc)
{
u32 reg;
if (dwc->core_reset_after_phy_init)
return dwc3_core_soft_reset_after_phy_init(dwc);
/* Before Resetting PHY, put Core in Reset */
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
reg |= DWC3_GCTL_CORESOFTRESET;
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
/* Bring up PHYs */
usb_phy_init(dwc->usb2_phy);
usb_phy_init(dwc->usb3_phy);
dwc3_notify_event(dwc, DWC3_CONTROLLER_RESET_EVENT);
/* Assert USB3 PHY reset */
reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
/* Assert USB2 PHY reset */
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
mdelay(100);
/* Clear USB3 PHY reset */
reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
/* Clear USB2 PHY reset */
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
mdelay(100);
/* After PHYs are stable we can take Core out of reset state */
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
reg &= ~DWC3_GCTL_CORESOFTRESET;
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
dwc3_notify_event(dwc, DWC3_CONTROLLER_POST_RESET_EVENT);
}
static void ci_hdrc_msm_notify_event(struct ci_hdrc *ci, unsigned event)
{
struct device *dev = ci->gadget.dev.parent;
switch (event) {
case CI_HDRC_CONTROLLER_RESET_EVENT:
dev_dbg(dev, "CI_HDRC_CONTROLLER_RESET_EVENT received\n");
writel(0, USB_AHBBURST);
/* use AHB transactor, allow posted data writes */
writel(0x8, USB_AHBMODE);
usb_phy_init(ci->usb_phy);
break;
case CI_HDRC_CONTROLLER_STOPPED_EVENT:
dev_dbg(dev, "CI_HDRC_CONTROLLER_STOPPED_EVENT received\n");
/*
* Put the phy in non-driving mode. Otherwise host
* may not detect soft-disconnection.
*/
usb_phy_notify_disconnect(ci->usb_phy, USB_SPEED_UNKNOWN);
break;
default:
dev_dbg(dev, "unknown ci_hdrc event\n");
break;
}
}
static int exynos_ohci_runtime_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct exynos4_ohci_platdata *pdata = pdev->dev.platform_data;
struct exynos_ohci_hcd *exynos_ohci = platform_get_drvdata(pdev);
struct usb_hcd *hcd = exynos_ohci->hcd;
if (dev->power.is_suspended)
return 0;
dev_dbg(dev, "%s\n", __func__);
if (exynos_ohci->phy) {
struct usb_phy *phy = exynos_ohci->phy;
if (exynos_ohci->post_lpa_resume) {
usb_phy_init(phy);
exynos_ohci->post_lpa_resume = 0;
}
pm_runtime_get_sync(phy->dev);
} else if (pdata->phy_resume) {
pdata->phy_resume(pdev, USB_PHY_TYPE_HOST);
}
ohci_resume(hcd, false);
return 0;
}
static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
{
struct platform_device *pdev = to_platform_device(hsotg->dev);
int ret;
ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
hsotg->supplies);
if (ret)
return ret;
if (hsotg->clk) {
ret = clk_prepare_enable(hsotg->clk);
if (ret)
return ret;
}
if (hsotg->uphy) {
ret = usb_phy_init(hsotg->uphy);
} else if (hsotg->plat && hsotg->plat->phy_init) {
ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
} else {
ret = phy_power_on(hsotg->phy);
if (ret == 0)
ret = phy_init(hsotg->phy);
}
return ret;
}
static int dsps_musb_reset(struct musb *musb)
{
struct device *dev = musb->controller;
struct dsps_glue *glue = dev_get_drvdata(dev->parent);
const struct dsps_musb_wrapper *wrp = glue->wrp;
int session_restart = 0;
if (glue->sw_babble_enabled)
session_restart = sw_babble_control(musb);
/*
* In case of new silicon version babble condition can be recovered
* without resetting the MUSB. But for older silicon versions, MUSB
* reset is needed
*/
if (session_restart || !glue->sw_babble_enabled) {
dev_info(musb->controller, "Restarting MUSB to recover from Babble\n");
dsps_writel(musb->ctrl_base, wrp->control, (1 << wrp->reset));
usleep_range(100, 200);
usb_phy_shutdown(musb->xceiv);
usleep_range(100, 200);
usb_phy_init(musb->xceiv);
session_restart = 1;
}
return !session_restart;
}
static int dwc3_resume(struct device *dev)
{
struct dwc3 *dwc = dev_get_drvdata(dev);
unsigned long flags;
int ret;
pinctrl_pm_select_default_state(dev);
usb_phy_init(dwc->usb3_phy);
usb_phy_init(dwc->usb2_phy);
ret = phy_init(dwc->usb2_generic_phy);
if (ret < 0)
return ret;
ret = phy_init(dwc->usb3_generic_phy);
if (ret < 0)
goto err_usb2phy_init;
spin_lock_irqsave(&dwc->lock, flags);
dwc3_event_buffers_setup(dwc);
dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
switch (dwc->dr_mode) {
case USB_DR_MODE_PERIPHERAL:
case USB_DR_MODE_OTG:
dwc3_gadget_resume(dwc);
/* FALLTHROUGH */
case USB_DR_MODE_HOST:
default:
/* do nothing */
break;
}
spin_unlock_irqrestore(&dwc->lock, flags);
pm_runtime_disable(dev);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
return 0;
err_usb2phy_init:
phy_exit(dwc->usb2_generic_phy);
return ret;
}
static int dwc3_resume(struct device *dev)
{
struct dwc3 *dwc = dev_get_drvdata(dev);
unsigned long flags;
int ret;
/* Check if platform glue driver handling PM, if not then handle here */
if(!dwc3_notify_event(dwc, DWC3_CORE_PM_RESUME_EVENT))
return 0;
ret = usb_phy_init(dwc->usb3_phy);
if (ret) {
pr_err("%s: usb_phy_init(dwc->usb3_phy) returned %d\n",
__func__, ret);
return ret;
}
ret = usb_phy_init(dwc->usb2_phy);
if (ret) {
pr_err("%s: usb_phy_init(dwc->usb2_phy) returned %d\n",
__func__, ret);
return ret;
}
msleep(100);
spin_lock_irqsave(&dwc->lock, flags);
dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
switch (dwc->mode) {
case DWC3_MODE_DEVICE:
case DWC3_MODE_DRD:
dwc3_gadget_resume(dwc);
/* FALLTHROUGH */
case DWC3_MODE_HOST:
default:
/* do nothing */
break;
}
spin_unlock_irqrestore(&dwc->lock, flags);
pm_runtime_disable(dev);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
return 0;
}
static int dsps_musb_init(struct musb *musb)
{
struct device *dev = musb->controller;
struct dsps_glue *glue = dev_get_drvdata(dev->parent);
struct platform_device *parent = to_platform_device(dev->parent);
const struct dsps_musb_wrapper *wrp = glue->wrp;
void __iomem *reg_base;
struct resource *r;
u32 rev, val;
int ret;
r = platform_get_resource_byname(parent, IORESOURCE_MEM, "control");
reg_base = devm_ioremap_resource(dev, r);
if (IS_ERR(reg_base))
return PTR_ERR(reg_base);
musb->ctrl_base = reg_base;
/* NOP driver needs change if supporting dual instance */
musb->xceiv = devm_usb_get_phy_by_phandle(dev, "phys", 0);
if (IS_ERR(musb->xceiv))
return PTR_ERR(musb->xceiv);
/* Returns zero if e.g. not clocked */
rev = dsps_readl(reg_base, wrp->revision);
if (!rev)
return -ENODEV;
usb_phy_init(musb->xceiv);
setup_timer(&glue->timer, otg_timer, (unsigned long) musb);
/* Reset the musb */
dsps_writel(reg_base, wrp->control, (1 << wrp->reset));
musb->isr = dsps_interrupt;
/* reset the otgdisable bit, needed for host mode to work */
val = dsps_readl(reg_base, wrp->phy_utmi);
val &= ~(1 << wrp->otg_disable);
dsps_writel(musb->ctrl_base, wrp->phy_utmi, val);
/*
* Check whether the dsps version has babble control enabled.
* In latest silicon revision the babble control logic is enabled.
* If MUSB_BABBLE_CTL returns 0x4 then we have the babble control
* logic enabled.
*/
val = dsps_readb(musb->mregs, MUSB_BABBLE_CTL);
if (val == MUSB_BABBLE_RCV_DISABLE) {
glue->sw_babble_enabled = true;
val |= MUSB_BABBLE_SW_SESSION_CTRL;
dsps_writeb(musb->mregs, MUSB_BABBLE_CTL, val);
}
ret = dsps_musb_dbg_init(musb, glue);
if (ret)
return ret;
return 0;
}
static void exynos_ohci_phy_enable(struct platform_device *pdev)
{
struct usb_hcd *hcd = platform_get_drvdata(pdev);
struct exynos_ohci_hcd *exynos_ohci = to_exynos_ohci(hcd);
if (exynos_ohci->phy)
usb_phy_init(exynos_ohci->phy);
}
static void musb_otg_notifier_work(struct work_struct *data_notifier_work)
{
struct musb *musb = container_of(data_notifier_work, struct musb, otg_notifier_work);
struct device *dev = musb->controller;
struct musb_hdrc_platform_data *pdata = dev->platform_data;
struct omap_musb_board_data *data = pdata->board_data;
switch (musb->xceiv_event) {
case USB_EVENT_ID:
dev_dbg(musb->controller, "ID GND\n");
if (!is_otg_enabled(musb) || musb->gadget_driver) {
pm_runtime_get_sync(musb->controller);
usb_phy_init(musb->xceiv);
omap2430_musb_set_vbus(musb, 1);
}
break;
case USB_EVENT_VBUS:
dev_dbg(musb->controller, "VBUS Connect\n");
if (musb->gadget_driver)
pm_runtime_get_sync(musb->controller);
usb_phy_init(musb->xceiv);
break;
case USB_EVENT_NONE:
dev_dbg(musb->controller, "VBUS Disconnect\n");
if (is_otg_enabled(musb) || is_peripheral_enabled(musb))
if (musb->gadget_driver) {
pm_runtime_mark_last_busy(musb->controller);
pm_runtime_put_autosuspend(musb->controller);
}
if (data->interface_type == MUSB_INTERFACE_UTMI) {
if (musb->xceiv->otg->set_vbus)
otg_set_vbus(musb->xceiv->otg, 0);
}
usb_phy_shutdown(musb->xceiv);
break;
default:
dev_dbg(musb->controller, "ID float\n");
}
}
static void exynos_ohci_phy_enable(struct exynos_ohci_hcd *exynos_ohci)
{
struct platform_device *pdev = to_platform_device(exynos_ohci->dev);
if (exynos_ohci->phy)
usb_phy_init(exynos_ohci->phy);
else if (exynos_ohci->pdata && exynos_ohci->pdata->phy_init)
exynos_ohci->pdata->phy_init(pdev, USB_PHY_TYPE_HOST);
}
/**
* Peforms initialization of HS and SS PHYs.
* If used as a part of POR or init sequence it is recommended
* that we should perform hard reset of the PHYs prior to invoking
* this function.
* @dwc: pointer to our context structure
*/
static int dwc3_init_usb_phys(struct dwc3 *dwc)
{
int ret;
/* Bring up PHYs */
ret = usb_phy_init(dwc->usb2_phy);
if (ret) {
pr_err("%s: usb_phy_init(dwc->usb2_phy) returned %d\n",
__func__, ret);
return ret;
}
ret = usb_phy_init(dwc->usb3_phy);
if (ret) {
pr_err("%s: usb_phy_init(dwc->usb3_phy) returned %d\n",
__func__, ret);
return ret;
}
return 0;
}
static int usb_power_on(struct platform_device *pdev)
{
if (IS_ERR(phy))
return PTR_ERR(phy);
pm_runtime_enable(&pdev->dev);
pm_runtime_get_sync(&pdev->dev);
usb_phy_init(phy);
return 0;
}
/**
* dwc3_core_soft_reset - Issues core soft reset and PHY reset
* @dwc: pointer to our context structure
*/
static int dwc3_core_soft_reset(struct dwc3 *dwc)
{
u32 reg;
int retries = 1000;
int ret;
usb_phy_init(dwc->usb2_phy);
usb_phy_init(dwc->usb3_phy);
ret = phy_init(dwc->usb2_generic_phy);
if (ret < 0)
return ret;
ret = phy_init(dwc->usb3_generic_phy);
if (ret < 0) {
phy_exit(dwc->usb2_generic_phy);
return ret;
}
/*
* We're resetting only the device side because, if we're in host mode,
* XHCI driver will reset the host block. If dwc3 was configured for
* host-only mode, then we can return early.
*/
if (dwc->dr_mode == USB_DR_MODE_HOST)
return 0;
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
reg |= DWC3_DCTL_CSFTRST;
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
do {
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
if (!(reg & DWC3_DCTL_CSFTRST))
return 0;
udelay(1);
} while (--retries);
return -ETIMEDOUT;
}
static void usb_udc_init(void)
{
DBG("\n************************\n");
DBG(" usb init start\n");
DBG("\n************************\n");
usb_phy_init();
usb_set_mode_device();
mxc_init_usb_qh();
usb_init_eps();
mxc_init_ep_struct();
ep0_setup();
}
static void omap2430_musb_enable(struct musb *musb)
{
u8 devctl;
unsigned long timeout = jiffies + msecs_to_jiffies(1000);
struct device *dev = musb->controller;
struct musb_hdrc_platform_data *pdata = dev->platform_data;
struct omap_musb_board_data *data = pdata->board_data;
switch (musb->xceiv->last_event) {
case USB_EVENT_ID:
usb_phy_init(musb->xceiv);
if (data->interface_type != MUSB_INTERFACE_UTMI)
break;
devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
devctl |= MUSB_DEVCTL_SESSION;
musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
while (musb_readb(musb->mregs, MUSB_DEVCTL) &
MUSB_DEVCTL_BDEVICE) {
cpu_relax();
if (time_after(jiffies, timeout)) {
dev_err(dev, "configured as A device timeout");
break;
}
}
break;
case USB_EVENT_VBUS:
usb_phy_init(musb->xceiv);
break;
default:
break;
}
}
static void usb_udc_init(void)
{
DBG("usb init start\n");
usbotg_init_ext();
usbotg_clock_gate(1);
usb_phy_init();
usb_set_mode_device();
//mxc_init_usb_qh();
//usb_init_eps();
//mxc_init_ep_struct();
//ep0_setup();
//mxc_ep_qh_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
// USB_MAX_CTRL_PAYLOAD, 0, 0);
udc_connect();
}
static void s5p_ehci_phy_init(struct platform_device *pdev)
{
struct usb_hcd *hcd = platform_get_drvdata(pdev);
struct s5p_ehci_hcd *s5p_ehci = to_s5p_ehci(hcd);
if (s5p_ehci->phy) {
usb_phy_init(s5p_ehci->phy);
s5p_ehci->post_lpa_resume = 0;
} else if (s5p_ehci->pdata->phy_init) {
s5p_ehci->pdata->phy_init(pdev, USB_PHY_TYPE_HOST);
} else {
dev_err(&pdev->dev, "Failed to init ehci phy\n");
return;
}
s5p_ehci_configurate(hcd);
}
static int dsps_musb_init(struct musb *musb)
{
struct device *dev = musb->controller;
struct dsps_glue *glue = dev_get_drvdata(dev->parent);
struct platform_device *parent = to_platform_device(dev->parent);
const struct dsps_musb_wrapper *wrp = glue->wrp;
void __iomem *reg_base;
struct resource *r;
u32 rev, val;
r = platform_get_resource_byname(parent, IORESOURCE_MEM, "control");
if (!r)
return -EINVAL;
reg_base = devm_ioremap_resource(dev, r);
if (IS_ERR(reg_base))
return PTR_ERR(reg_base);
musb->ctrl_base = reg_base;
/* NOP driver needs change if supporting dual instance */
musb->xceiv = devm_usb_get_phy_by_phandle(dev, "phys", 0);
if (IS_ERR(musb->xceiv))
return PTR_ERR(musb->xceiv);
/* Returns zero if e.g. not clocked */
rev = dsps_readl(reg_base, wrp->revision);
if (!rev)
return -ENODEV;
usb_phy_init(musb->xceiv);
setup_timer(&glue->timer, otg_timer, (unsigned long) musb);
/* Reset the musb */
dsps_writel(reg_base, wrp->control, (1 << wrp->reset));
musb->isr = dsps_interrupt;
/* reset the otgdisable bit, needed for host mode to work */
val = dsps_readl(reg_base, wrp->phy_utmi);
val &= ~(1 << wrp->otg_disable);
dsps_writel(musb->ctrl_base, wrp->phy_utmi, val);
return 0;
}
static int dsps_musb_init(struct musb *musb)
{
struct device_d *dev = musb->controller;
struct dsps_glue *glue = dev->priv;
const struct dsps_musb_wrapper *wrp = glue->wrp;
u32 rev, val, mode;
musb->xceiv = am335x_get_usb_phy();
if (IS_ERR(musb->xceiv))
return PTR_ERR(musb->xceiv);
/* Returns zero if e.g. not clocked */
rev = dsps_readl(musb->ctrl_base, wrp->revision);
if (!rev)
return -ENODEV;
usb_phy_init(musb->xceiv);
/* Reset the musb */
dsps_writel(musb->ctrl_base, wrp->control, (1 << wrp->reset));
musb->isr = dsps_interrupt;
/* reset the otgdisable bit, needed for host mode to work */
val = dsps_readl(musb->ctrl_base, wrp->phy_utmi);
val &= ~(1 << wrp->otg_disable);
dsps_writel(musb->ctrl_base, wrp->phy_utmi, val);
mode = dsps_readl(musb->ctrl_base, wrp->mode);
switch (musb->port_mode) {
case MUSB_PORT_MODE_HOST:
mode &= ~0x100;
break;
case MUSB_PORT_MODE_GADGET:
mode |= 0x100;
break;
}
mode |= 0x80;
dsps_writel(musb->ctrl_base, wrp->mode, mode); /* IDDIG=0, IDDIG_MUX=1 */
return 0;
}
static int exynos_ehci_resume(struct device *dev)
{
struct usb_hcd *hcd = dev_get_drvdata(dev);
struct exynos_ehci_hcd *exynos_ehci = to_exynos_ehci(hcd);
clk_prepare_enable(exynos_ehci->clk);
if (exynos_ehci->otg)
exynos_ehci->otg->set_host(exynos_ehci->otg, &hcd->self);
if (exynos_ehci->phy)
usb_phy_init(exynos_ehci->phy);
/* DMA burst Enable */
writel(EHCI_INSNREG00_ENABLE_DMA_BURST, EHCI_INSNREG00(hcd->regs));
ehci_resume(hcd, false);
return 0;
}
static int s5p_ehci_runtime_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct s5p_ehci_platdata *pdata = pdev->dev.platform_data;
struct usb_hcd *hcd = platform_get_drvdata(pdev);
struct s5p_ehci_hcd *s5p_ehci = to_s5p_ehci(hcd);
int rc = 0;
if (dev->power.is_suspended)
return 0;
dev_dbg(dev, "%s\n", __func__);
if (s5p_ehci->phy) {
struct usb_phy *phy = s5p_ehci->phy;
if (s5p_ehci->post_lpa_resume)
usb_phy_init(phy);
pm_runtime_get_sync(phy->dev);
} else if (pdata && pdata->phy_resume) {
rc = pdata->phy_resume(pdev, USB_PHY_TYPE_HOST);
s5p_ehci->post_lpa_resume = !!rc;
}
if (s5p_ehci->post_lpa_resume)
s5p_ehci_configurate(hcd);
ehci_resume(hcd, false);
/*
* REVISIT: in case of LPA bus won't be resumed, so we do it here.
* Alternatively, we can try to setup HC in such a way that it starts
* to sense connections. In this case, root hub will be resumed from
* interrupt (ehci_irq()).
*/
if (s5p_ehci->post_lpa_resume)
usb_hcd_resume_root_hub(hcd);
s5p_ehci->post_lpa_resume = 0;
return 0;
}
int r8a7778_usb_phy_power(bool enable)
{
static struct usb_phy *phy = NULL;
int ret = 0;
if (!phy)
phy = usb_get_phy(USB_PHY_TYPE_USB2);
if (IS_ERR(phy)) {
pr_err("kernel doesn't have usb phy driver\n");
return PTR_ERR(phy);
}
if (enable)
ret = usb_phy_init(phy);
else
usb_phy_shutdown(phy);
return ret;
}
static int usbhs_power_ctrl(struct platform_device *pdev,
void __iomem *base, int enable)
{
struct usbhs_private *priv = usbhs_get_priv(pdev);
if (!priv->phy)
return -ENODEV;
if (enable) {
int retval = usb_phy_init(priv->phy);
if (!retval)
retval = usb_phy_set_suspend(priv->phy, 0);
return retval;
}
usb_phy_set_suspend(priv->phy, 1);
usb_phy_shutdown(priv->phy);
return 0;
}
static int mv_otg_enable_internal(struct mv_otg *mvotg)
{
int retval = 0;
if (mvotg->active)
return 0;
dev_dbg(&mvotg->pdev->dev, "otg enabled\n");
otg_clock_enable(mvotg);
retval = usb_phy_init(mvotg->outer_phy);
if (retval) {
dev_err(&mvotg->pdev->dev,
"failed to initialize phy %d\n", retval);
otg_clock_disable(mvotg);
return retval;
}
mvotg->active = 1;
return 0;
}
static int s5p_ehci_resume(struct device *dev)
{
struct usb_hcd *hcd = dev_get_drvdata(dev);
struct s5p_ehci_hcd *s5p_ehci = to_s5p_ehci(hcd);
struct platform_device *pdev = to_platform_device(dev);
s5p_ehci_clk_prepare_enable(s5p_ehci);
if (s5p_ehci->otg)
s5p_ehci->otg->set_host(s5p_ehci->otg, &hcd->self);
if (s5p_ehci->phy) {
usb_phy_init(s5p_ehci->phy);
s5p_ehci->post_lpa_resume = 0;
/*
* We are going to change runtime status to active.
* Make sure we get the phy only if we didn't get it before.
*/
if (pm_runtime_suspended(dev))
pm_runtime_get_sync(s5p_ehci->phy->dev);
} else if (s5p_ehci->pdata->phy_init) {
s5p_ehci->pdata->phy_init(pdev, USB_PHY_TYPE_HOST);
}
/* DMA burst Enable */
writel(EHCI_INSNREG00_ENABLE_DMA_BURST, EHCI_INSNREG00(hcd->regs));
ehci_resume(hcd, false);
/* Update runtime PM status and clear runtime_error */
pm_runtime_disable(dev);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
return 0;
}