Exemple #1
0
static void __init rk3288_dt_map_io(void)
{
	iotable_init(rk3288_io_desc, ARRAY_SIZE(rk3288_io_desc));
	debug_ll_io_init();
	usb_uart_init();

	rockchip_soc_id = ROCKCHIP_SOC_RK3288;

	/* rkpwm is used instead of old pwm */
	writel_relaxed(0x00010001, RK_GRF_VIRT + RK3288_GRF_SOC_CON2);

	/* disable address remap */
	writel_relaxed(0x08000000, RK_SGRF_VIRT + RK3288_SGRF_SOC_CON0);

	/* enable timer7 for core */
	writel_relaxed(0, RK3288_TIMER7_VIRT + 0x10);
	dsb();
	writel_relaxed(0xFFFFFFFF, RK3288_TIMER7_VIRT + 0x00);
	writel_relaxed(0xFFFFFFFF, RK3288_TIMER7_VIRT + 0x04);
	dsb();
	writel_relaxed(1, RK3288_TIMER7_VIRT + 0x10);
	dsb();

	rk3288_boot_mode_init();
}
Exemple #2
0
void system_init(void)
{
    hal_sys_init();
    hal_i2c_init();
    usb_uart_init();
    tmp245_init();
    /* initialize system lock */
    syslock = xSemaphoreCreateMutex();
    set_configuration(ADC_INPUT_VOLTAGE_DC, ADC_RANGE_300, 
        ADC_INTEGRATION_50HZ, ADC_CHANNEL_0, 1, 0, ADC_RESOLUTION_5_5);
}
static void __init rk3188_dt_map_io(void)
{
	iotable_init(rk3188_io_desc, ARRAY_SIZE(rk3188_io_desc));
	debug_ll_io_init();
	usb_uart_init();

	rockchip_soc_id = ROCKCHIP_SOC_RK3188;
	if (readl_relaxed(RK_ROM_VIRT + 0x27f0) == 0x33313042
	 && readl_relaxed(RK_ROM_VIRT + 0x27f4) == 0x32303133
	 && readl_relaxed(RK_ROM_VIRT + 0x27f8) == 0x30313331
	 && readl_relaxed(RK_ROM_VIRT + 0x27fc) == 0x56313031)
		rockchip_soc_id = ROCKCHIP_SOC_RK3188PLUS;

	/* rki2c is used instead of old i2c */
	writel_relaxed(0xF800F800, RK_GRF_VIRT + RK3188_GRF_SOC_CON1);

	rk3188_boot_mode_init();
}
static void __init rk3036_dt_map_io(void)
{
	rockchip_soc_id = ROCKCHIP_SOC_RK3036;

	iotable_init(rk3036_io_desc, ARRAY_SIZE(rk3036_io_desc));
	debug_ll_io_init();
	usb_uart_init();

	/* enable timer5 for core */
	writel_relaxed(0, RK3036_TIMER5_VIRT + 0x10);
	dsb();
	writel_relaxed(0xFFFFFFFF, RK3036_TIMER5_VIRT + 0x00);
	writel_relaxed(0xFFFFFFFF, RK3036_TIMER5_VIRT + 0x04);
	dsb();
	writel_relaxed(1, RK3036_TIMER5_VIRT + 0x10);
	dsb();

	rk3036_boot_mode_init();
}
static void __init rk3288_dt_map_io(void)
{
	u32 v;

	rockchip_soc_id = ROCKCHIP_SOC_RK3288;

	iotable_init(rk3288_io_desc, ARRAY_SIZE(rk3288_io_desc));
	debug_ll_io_init();
	usb_uart_init();

	/* pmu reset by second global soft reset */
	v = readl_relaxed(RK_CRU_VIRT + RK3288_CRU_GLB_RST_CON);
	v &= ~(3 << 2);
	v |= 1 << 2;
	writel_relaxed(v, RK_CRU_VIRT + RK3288_CRU_GLB_RST_CON);

	/* rkpwm is used instead of old pwm */
	writel_relaxed(0x00010001, RK_GRF_VIRT + RK3288_GRF_SOC_CON2);

	/* disable address remap */
#ifndef CONFIG_ARM_TRUSTZONE
	writel_relaxed(0x08000000, RK_SGRF_VIRT + RK3288_SGRF_SOC_CON0);
#endif

	/* enable timer7 for core */
	writel_relaxed(0, RK3288_TIMER7_VIRT + 0x10);
	dsb();
	writel_relaxed(0xFFFFFFFF, RK3288_TIMER7_VIRT + 0x00);
	writel_relaxed(0xFFFFFFFF, RK3288_TIMER7_VIRT + 0x04);
	dsb();
	writel_relaxed(1, RK3288_TIMER7_VIRT + 0x10);
	dsb();

	/* power up/down GPU domain wait 1us */
	writel_relaxed(24, RK_PMU_VIRT + RK3288_PMU_GPU_PWRDWN_CNT);
	writel_relaxed(24, RK_PMU_VIRT + RK3288_PMU_GPU_PWRUP_CNT);

	rk3288_boot_mode_init();
#ifndef CONFIG_ARM_TRUSTZONE
	rockchip_efuse_init();
#endif
}