void usrInit (int startType)
{
sysStart (startType); /* clear BSS and set up the vector table base address. */
cacheLibInit (USER_I_CACHE_MODE, USER_D_CACHE_MODE); /* include cache support */
excVecInit (); /* exception handling */
sysHwInit (); /* call the BSPs sysHwInit routine during system startup */
usrCacheEnable (); /* optionally enable caches */
objOwnershipInit (); /* object management ownership */
objInfoInit (); /* object management routines that requires lookup in a list of objects, such as the objNameToId() routine. */
objLibInit ((FUNCPTR)FUNCPTR_OBJ_MEMALLOC_RTN, FUNCPTR_OBJ_MEMFREE_RTN, OBJ_MEM_POOL_ID, OBJ_LIBRARY_OPTIONS); /* object management */
vxMemProbeInit (); /* Initialize vxMemProbe exception handler support */
wvLibInit (); /* low-level kernel instrumentation needed by System Viewer */
classListLibInit (); /* object class list management */
semLibInit (); /* semaphore support infrastructure */
/* mutex semaphores */
/* mutex semaphore creation routine */
classLibInit (); /* object class management */
kernelBaseInit (); /* required component DO NOT REMOVE. */
/* __thread variables support */
usrKernelInit (VX_GLOBAL_NO_STACK_FILL); /* context switch and interrupt handling (DO NOT REMOVE). */
}
void usrInit
(
int startType
)
{
/*
* This trap will catch improper loading of the data section.
* We check the magic cookie values to make sure the data section is
* in the expected memory location. We do not want
* to proceed further if the data segment is not correct.
*
* It should be easy to detect entry into the trap using an ICE, JTAG,
* or logic analyzer. Without the trap, the processor is likely to run
* away out of control.
*
* Data section misalignment can occur when there is a change in tool
* chain, build rules, compiler, host utilites, etc.
*/
while (trapValue1 != TRAP_VALUE_1 || trapValue2 != TRAP_VALUE_2)
{
/* infinite loop */;
}
#if (CPU_FAMILY == SPARC)
excWindowInit (); /* SPARC window management */
#endif
#ifdef INCLUDE_SYS_HW_INIT_0
/*
* Perform any BSP-specific initialisation that must be done before
* cacheLibInit() is called and/or BSS is cleared.
*/
SYS_HW_INIT_0 ();
#endif /* INCLUDE_SYS_HW_INIT_0 */
/* configure data and instruction cache if available and leave disabled */
#ifdef INCLUDE_CACHE_SUPPORT
/*
* SPR 73609: If a cache is not to be enabled, don't require
* its mode to be defined. Instead, default it to disabled.
*/
# if (!defined(USER_D_CACHE_ENABLE) && !defined(USER_D_CACHE_MODE))
# define USER_D_CACHE_MODE CACHE_DISABLED
# endif /* !USER_D_CACHE_ENABLE && !USER_D_CACHE_MODE */
# if (!defined(USER_I_CACHE_ENABLE) && !defined(USER_I_CACHE_MODE))
# define USER_I_CACHE_MODE CACHE_DISABLED
# endif /* !USER_I_CACHE_ENABLE && !USER_I_CACHE_MODE */
cacheLibInit (USER_I_CACHE_MODE, USER_D_CACHE_MODE);
#endif /* INCLUDE_CACHE_SUPPORT */
#if CPU_FAMILY!=SIMNT && CPU_FAMILY!=SIMSPARCSUNOS && CPU_FAMILY!=SIMHPPA && CPU_FAMILY!=SIMSPARCSOLARIS
/* don't assume bss variables are zero before this call */
bzero (edata, end - edata); /* zero out bss variables */
#endif /* CPU_FAMILY!=SIMNT && CPU_FAMILY!=SIMSPARCSUNOS && CPU_FAMILY!=SIMHPPA && CPU_FAMILY!=SIMSPARCSOLARIS */
#if (CPU_FAMILY == PPC)
/*
* Immediately after clearing the bss, ensure global stdin
* etc. are ERROR until set to real values. This is used in
* target/src/arch/ppc/excArchLib.c to improve diagnosis of
* exceptions which occur before I/O is set up.
*/
ioGlobalStdSet (STD_IN, ERROR);
ioGlobalStdSet (STD_OUT, ERROR);
ioGlobalStdSet (STD_ERR, ERROR);
#endif /* CPU_FAMILY == PPC */
sysStartType = startType; /* save type of system start */
intVecBaseSet ((FUNCPTR *) VEC_BASE_ADRS); /* set vector base table */
#if (CPU_FAMILY == AM29XXX)
excSpillFillInit (); /* am29k stack cache managemt */
#endif
#ifdef INCLUDE_EXC_HANDLING
# if (CPU_FAMILY == PPC) && defined(INCLUDE_EXC_SHOW)
/*
* Do this ahead of excVecInit() to set up _func_excPanicHook, in case
* the enabling of Machine Check there allows a pending one to occur.
* excShowInit() will be called again later, harmlessly.
*/
excShowInit ();
# endif /* CPU_FAMILY == PPC && defined(INCLUDE_EXC_SHOW) */
excVecInit (); /* install exception vectors */
#endif /* INCLUDE_EXC_HANDLING */
sysHwInit (); /* initialize system hardware */
usrKernelInit (); /* configure the Wind kernel */
#ifdef INCLUDE_USB
# ifdef INCLUDE_OHCI_PCI_INIT
sysUsbPciOhciInit ();
# endif
#endif
#ifdef INCLUDE_CACHE_SUPPORT
#ifdef USER_I_CACHE_ENABLE
cacheEnable (INSTRUCTION_CACHE); /* enable instruction cache */
#endif /* USER_I_CACHE_ENABLE */
#ifdef USER_D_CACHE_ENABLE
cacheEnable (DATA_CACHE); /* enable data cache */
#endif /* USER_D_CACHE_ENABLE */
#if (CPU == MC68060)
#ifdef USER_B_CACHE_ENABLE
cacheEnable (BRANCH_CACHE); /* enable branch cache */
#endif /* USER_B_CACHE_ENABLE */
#endif /* (CPU == MC68060) */
#endif /* INCLUDE_CACHE_SUPPORT */
/* start the kernel specifying usrRoot as the root task */
kernelInit ((FUNCPTR) usrRoot, ROOT_STACK_SIZE,
(char *) MEM_POOL_START_ADRS,
sysMemTop (), ISR_STACK_SIZE, INT_LOCK_LEVEL);
}