static int rk3288_hdmi_video_frameComposer(struct hdmi *hdmi_drv, struct hdmi_video_para *vpara) //TODO Daisen wait to add support 3D
{
int h_act = 0, v_act = 0;
int h_syncdelay = 0, v_syncdelay = 0;
int h_sync = 0, v_sync = 0;
int h_blank = 0, v_blank = 0;
int vsync_pol = hdmi_drv->lcdc->cur_screen->pin_vsync;
int hsync_pol = hdmi_drv->lcdc->cur_screen->pin_hsync;
int de_pol = (hdmi_drv->lcdc->cur_screen->pin_den == 0) ? 1 : 0;
struct fb_videomode *mode = NULL;
struct rk3288_hdmi_device *hdmi_dev = container_of(hdmi_drv, struct rk3288_hdmi_device, driver);
mode = (struct fb_videomode *)hdmi_vic_to_videomode(vpara->vic);
if(mode == NULL) {
hdmi_err(hdmi_drv->dev, "[%s] not found vic %d\n", __FUNCTION__, vpara->vic);
return -ENOENT;
}
hdmi_drv->pixclock = mode->pixclock;
switch(vpara->color_depth) {
case HDMI_COLOR_DEPTH_8BIT:
hdmi_drv->tmdsclk = mode->pixclock;
break;
case HDMI_COLOR_DEPTH_10BIT:
hdmi_drv->tmdsclk = mode->pixclock * 10 / 8;
break;
case HDMI_COLOR_DEPTH_12BIT:
hdmi_drv->tmdsclk = mode->pixclock * 12 / 8;
break;
case HDMI_COLOR_DEPTH_16BIT:
hdmi_drv->tmdsclk = mode->pixclock * 2;
break;
default:
hdmi_drv->tmdsclk = mode->pixclock;
break;
}
rk3288_hdmi_config_phy(hdmi_drv, vpara->pixel_repet, vpara->color_depth);
hdmi_msk_reg(hdmi_dev, A_HDCPCFG0, m_ENCRYPT_BYPASS | m_HDMI_DVI,
v_ENCRYPT_BYPASS(1) | v_HDMI_DVI(vpara->output_mode)); //cfg to bypass hdcp data encrypt
hdmi_msk_reg(hdmi_dev, FC_INVIDCONF, m_FC_VSYNC_POL | m_FC_HSYNC_POL | m_FC_DE_POL | m_FC_HDMI_DVI | m_FC_INTERLACE_MODE,
v_FC_VSYNC_POL(vsync_pol) | v_FC_HSYNC_POL(hsync_pol) | v_FC_DE_POL(de_pol) | v_FC_HDMI_DVI(vpara->output_mode) | v_FC_INTERLACE_MODE(mode->vmode));
hdmi_msk_reg(hdmi_dev, FC_INVIDCONF, m_FC_VBLANK, v_FC_VBLANK(mode->vmode));
h_act = mode->xres;
hdmi_writel(hdmi_dev, FC_INHACTIV1, v_FC_HACTIVE1(h_act >> 8));
hdmi_writel(hdmi_dev, FC_INHACTIV0, (h_act & 0xff));
v_act = mode->yres;
hdmi_writel(hdmi_dev, FC_INVACTIV1, v_FC_VACTIVE1(v_act >> 8));
hdmi_writel(hdmi_dev, FC_INVACTIV0, (v_act & 0xff));
h_blank = mode->hsync_len + mode->left_margin + mode->right_margin;
hdmi_writel(hdmi_dev, FC_INHBLANK1, v_FC_HBLANK1(h_blank >> 8));
hdmi_writel(hdmi_dev, FC_INHBLANK0, (h_blank & 0xff));
v_blank = mode->vsync_len + mode->upper_margin + mode->lower_margin;
hdmi_writel(hdmi_dev, FC_INVBLANK, (v_blank & 0xff));
h_syncdelay = mode->right_margin;
hdmi_writel(hdmi_dev, FC_HSYNCINDELAY1, v_FC_HSYNCINDEAY1(h_syncdelay >> 8));
hdmi_writel(hdmi_dev, FC_HSYNCINDELAY0, (h_syncdelay & 0xff));
v_syncdelay = mode->lower_margin;
hdmi_writel(hdmi_dev, FC_VSYNCINDELAY, (v_syncdelay & 0xff));
h_sync = mode->hsync_len;
hdmi_writel(hdmi_dev, FC_HSYNCINWIDTH1, v_FC_HSYNCWIDTH1(h_sync >> 8));
hdmi_writel(hdmi_dev, FC_HSYNCINWIDTH0, (h_sync & 0xff));
v_sync = mode->vsync_len;
hdmi_writel(hdmi_dev, FC_VSYNCINWIDTH, (v_sync & 0xff));
/*Set the control period minimum duration(min. of 12 pixel clock cycles, refer to HDMI 1.4b specification)*/
hdmi_writel(hdmi_dev, FC_CTRLDUR, 12);
hdmi_writel(hdmi_dev, FC_EXCTRLDUR, 32);
#if 0
if(hdmi_drv->tmdsclk > 340000000) { //used for HDMI 2.0 TX //TODO Daisen wait to modify HDCP KEEPOUT
hdmi_msk_reg(hdmi_dev, FC_INVIDCONF, m_FC_HDCP_KEEPOUT, v_FC_HDCP_KEEPOUT(1));
hdmi_msk_reg(hdmi_dev, FC_SCRAMBLER_CTRL, m_FC_SCRAMBLE_EN, v_FC_SCRAMBLE_EN(1));
}
/* spacing < 256^2 * config / tmdsClock, spacing <= 50ms
* worst case: tmdsClock == 25MHz => config <= 19
*/
hdmi_writel(hdmi_dev, FC_EXCTRLSPAC, 1);
/*Set PreambleFilter*/
for (i = 0; i < 3; i++) {
value = (i + 1) * 11;
if (i == 0) /*channel 0*/
hdmi_writel(hdmi_dev, FC_CH0PREAM, value);
else if (i == 1) /*channel 1*/
hdmi_writel(hdmi_dev, FC_CH1PREAM, value & 0x3f);
else if (i == 2) /*channel 2*/
hdmi_writel(hdmi_dev, FC_CH2PREAM, value & 0x3f);
}
#endif
/*Set PixelRepetition:No pixel repetition*/
hdmi_writel(hdmi_dev, FC_PRCONF, v_FC_PR_FACTOR(vpara->pixel_repet + 1));
return 0;
}
static int rk2928_hdmi_config_video(struct hdmi_video_para *vpara)
{
int value;
struct fb_videomode *mode;
hdmi_dbg(hdmi->dev, "[%s]\n", __FUNCTION__);
if(vpara == NULL) {
hdmi_err(hdmi->dev, "[%s] input parameter error\n", __FUNCTION__);
return -1;
}
if(hdmi->hdcp_power_off_cb)
hdmi->hdcp_power_off_cb();
// Diable video and audio output
HDMIWrReg(AV_MUTE, v_AUDIO_MUTE(1) | v_VIDEO_MUTE(1));
// Input video mode is SDR RGB24bit, Data enable signal from external
HDMIWrReg(VIDEO_CONTRL1, v_VIDEO_INPUT_FORMAT(VIDEO_INPUT_SDR_RGB444) | v_DE_EXTERNAL);
HDMIWrReg(VIDEO_CONTRL2, v_VIDEO_INPUT_BITS(VIDEO_INPUT_8BITS) | (vpara->output_color & 0xFF));
// Set HDMI Mode
HDMIWrReg(HDCP_CTRL, v_HDMI_DVI(vpara->output_mode));
// Enable or disalbe color space convert
if(vpara->input_color != vpara->output_color) {
value = v_SOF_DISABLE | v_CSC_ENABLE;
}
else
value = v_SOF_DISABLE;
HDMIWrReg(VIDEO_CONTRL3, value);
// Set ext video
#if 1
HDMIWrReg(VIDEO_TIMING_CTL, 0);
mode = (struct fb_videomode *)hdmi_vic_to_videomode(vpara->vic);
if(mode == NULL)
{
hdmi_err(hdmi->dev, "[%s] not found vic %d\n", __FUNCTION__, vpara->vic);
return -ENOENT;
}
hdmi->tmdsclk = mode->pixclock;
#else
value = v_EXTERANL_VIDEO(1) | v_INETLACE(mode->vmode);
if(mode->sync & FB_SYNC_HOR_HIGH_ACT)
value |= v_HSYNC_POLARITY(1);
if(mode->sync & FB_SYNC_VERT_HIGH_ACT)
value |= v_VSYNC_POLARITY(1);
HDMIWrReg(VIDEO_TIMING_CTL, value);
value = mode->left_margin + mode->xres + mode->right_margin + mode->hsync_len;
HDMIWrReg(VIDEO_EXT_HTOTAL_L, value & 0xFF);
HDMIWrReg(VIDEO_EXT_HTOTAL_H, (value >> 8) & 0xFF);
value = mode->left_margin + mode->right_margin + mode->hsync_len;
HDMIWrReg(VIDEO_EXT_HBLANK_L, value & 0xFF);
HDMIWrReg(VIDEO_EXT_HBLANK_H, (value >> 8) & 0xFF);
value = mode->left_margin + mode->hsync_len;
HDMIWrReg(VIDEO_EXT_HDELAY_L, value & 0xFF);
HDMIWrReg(VIDEO_EXT_HDELAY_H, (value >> 8) & 0xFF);
value = mode->hsync_len;
HDMIWrReg(VIDEO_EXT_HDURATION_L, value & 0xFF);
HDMIWrReg(VIDEO_EXT_HDURATION_H, (value >> 8) & 0xFF);
value = mode->upper_margin + mode->yres + mode->lower_margin + mode->vsync_len;
HDMIWrReg(VIDEO_EXT_VTOTAL_L, value & 0xFF);
HDMIWrReg(VIDEO_EXT_VTOTAL_H, (value >> 8) & 0xFF);
value = mode->upper_margin + mode->vsync_len + mode->lower_margin;
HDMIWrReg(VIDEO_EXT_VBLANK, value & 0xFF);
if(vpara->vic == HDMI_720x480p_60Hz_4_3 || vpara->vic == HDMI_720x480p_60Hz_16_9)
value = 42;
else
value = mode->upper_margin + mode->vsync_len;
HDMIWrReg(VIDEO_EXT_VDELAY, value & 0xFF);
value = mode->vsync_len;
HDMIWrReg(VIDEO_EXT_VDURATION, value & 0xFF);
#endif
if(vpara->output_mode == OUTPUT_HDMI) {
rk2928_hdmi_config_avi(vpara->vic, vpara->output_color);
hdmi_dbg(hdmi->dev, "[%s] sucess output HDMI.\n", __FUNCTION__);
}
else {
hdmi_dbg(hdmi->dev, "[%s] sucess output DVI.\n", __FUNCTION__);
}
return 0;
}
int rk30_hdmi_config_video(struct hdmi_video_para *vpara)
{
int value;
struct fb_videomode *mode;
hdmi_dbg(hdmi->dev, "[%s]\n", __FUNCTION__);
if(vpara == NULL) {
hdmi_err(hdmi->dev, "[%s] input parameter error\n", __FUNCTION__);
return -1;
}
if(hdmi->pwr_mode == PWR_SAVE_MODE_E)
rk30_hdmi_set_pwr_mode(PWR_SAVE_MODE_D);
if(hdmi->pwr_mode == PWR_SAVE_MODE_D || hdmi->pwr_mode == PWR_SAVE_MODE_A)
rk30_hdmi_set_pwr_mode(PWR_SAVE_MODE_B);
if(hdmi->hdcp_power_off_cb)
hdmi->hdcp_power_off_cb();
// Input video mode is RGB24bit, Data enable signal from external
HDMIMskReg(value, AV_CTRL1, m_INPUT_VIDEO_MODE | m_DE_SIGNAL_SELECT, \
v_INPUT_VIDEO_MODE(vpara->input_mode) | EXTERNAL_DE)
HDMIMskReg(value, VIDEO_CTRL1, m_VIDEO_OUTPUT_MODE | m_VIDEO_INPUT_DEPTH | m_VIDEO_INPUT_COLOR_MODE, \
v_VIDEO_OUTPUT_MODE(vpara->output_color) | v_VIDEO_INPUT_DEPTH(VIDEO_INPUT_DEPTH_8BIT) | vpara->input_color)
HDMIWrReg(DEEP_COLOR_MODE, 0x20);
// color space convert
rk30_hdmi_config_csc(vpara);
// Set HDMI Mode
HDMIWrReg(HDCP_CTRL, v_HDMI_DVI(vpara->output_mode));
// Set ext video
mode = (struct fb_videomode *)hdmi_vic_to_videomode(vpara->vic);
if(mode == NULL)
{
hdmi_err(hdmi->dev, "[%s] not found vic %d\n", __FUNCTION__, vpara->vic);
return -ENOENT;
}
hdmi->tmdsclk = mode->pixclock;
if( (vpara->vic == HDMI_720x480p_60Hz_4_3) || (vpara->vic == HDMI_720x480p_60Hz_16_9) )
value = v_VSYNC_OFFSET(6);
else
value = v_VSYNC_OFFSET(0);
value |= v_EXT_VIDEO_ENABLE(1) | v_INTERLACE(mode->vmode);
if(mode->sync & FB_SYNC_HOR_HIGH_ACT)
value |= v_HSYNC_POLARITY(1);
if(mode->sync & FB_SYNC_VERT_HIGH_ACT)
value |= v_VSYNC_POLARITY(1);
HDMIWrReg(EXT_VIDEO_PARA, value);
value = mode->left_margin + mode->xres + mode->right_margin + mode->hsync_len;
HDMIWrReg(EXT_VIDEO_PARA_HTOTAL_L, value & 0xFF);
HDMIWrReg(EXT_VIDEO_PARA_HTOTAL_H, (value >> 8) & 0xFF);
value = mode->left_margin + mode->right_margin + mode->hsync_len;
HDMIWrReg(EXT_VIDEO_PARA_HBLANK_L, value & 0xFF);
HDMIWrReg(EXT_VIDEO_PARA_HBLANK_H, (value >> 8) & 0xFF);
value = mode->left_margin + mode->hsync_len;
HDMIWrReg(EXT_VIDEO_PARA_HDELAY_L, value & 0xFF);
HDMIWrReg(EXT_VIDEO_PARA_HDELAY_H, (value >> 8) & 0xFF);
value = mode->hsync_len;
HDMIWrReg(EXT_VIDEO_PARA_HSYNCWIDTH_L, value & 0xFF);
HDMIWrReg(EXT_VIDEO_PARA_HSYNCWIDTH_H, (value >> 8) & 0xFF);
value = mode->upper_margin + mode->yres + mode->lower_margin + mode->vsync_len;
HDMIWrReg(EXT_VIDEO_PARA_VTOTAL_L, value & 0xFF);
HDMIWrReg(EXT_VIDEO_PARA_VTOTAL_H, (value >> 8) & 0xFF);
value = mode->upper_margin + mode->vsync_len + mode->lower_margin;
HDMIWrReg(EXT_VIDEO_PARA_VBLANK_L, value & 0xFF);
if(vpara->vic == HDMI_720x480p_60Hz_4_3 || vpara->vic == HDMI_720x480p_60Hz_16_9)
value = 42;
else
value = mode->upper_margin + mode->vsync_len;
HDMIWrReg(EXT_VIDEO_PARA_VDELAY, value & 0xFF);
value = mode->vsync_len;
HDMIWrReg(EXT_VIDEO_PARA_VSYNCWIDTH, value & 0xFF);
if(vpara->output_mode == OUTPUT_HDMI) {
rk30_hdmi_config_avi(vpara->vic, vpara->output_color);
hdmi_dbg(hdmi->dev, "[%s] sucess output HDMI.\n", __FUNCTION__);
}
else {
hdmi_dbg(hdmi->dev, "[%s] sucess output DVI.\n", __FUNCTION__);
}
rk30_hdmi_config_phy(vpara->vic);
rk30_hdmi_control_output(0);
return 0;
}
int rk610_hdmi_sys_config_video(struct hdmi *hdmi, int vic, int input_color, int output_color)
{
char value;
struct fb_videomode *mode;
// Diable HDCP
if(rk610_hdmi->hdcp_power_off_cb)
rk610_hdmi->hdcp_power_off_cb();
// Diable video and audio output
HDMIWrReg(AV_MUTE, v_AUDIO_MUTE(1) | v_VIDEO_MUTE(1));
// Input video mode is SDR RGB24bit, Data enable signal from external
HDMIWrReg(VIDEO_CONTRL1, v_VIDEO_INPUT_FORMAT(VIDEO_INPUT_SDR_RGB444) | v_DE_EXTERNAL);
HDMIWrReg(VIDEO_CONTRL2, v_VIDEO_INPUT_BITS(VIDEO_INPUT_8BITS) | (output_color & 0xFF));
// Set HDMI Mode
HDMIWrReg(HDCP_CTRL, v_HDMI_DVI(hdmi->edid.is_hdmi));
// Enable or disalbe color space convert
if(input_color != output_color) {
value = v_SOF_DISABLE | v_CSC_ENABLE;
}
else
value = v_SOF_DISABLE;
HDMIWrReg(VIDEO_CONTRL3, value);
#if 1
HDMIWrReg(VIDEO_TIMING_CTL, 0);
mode = (struct fb_videomode *)ext_hdmi_vic_to_videomode(vic);
if(mode == NULL)
{
hdmi_dbg(hdmi->dev, "[%s] not found vic %d\n", __FUNCTION__, vic);
return -ENOENT;
}
rk610_hdmi->frequency = mode->pixclock;
#else
// Set ext video
value = v_EXTERANL_VIDEO(1) | v_INETLACE(mode->vmode);
if(mode->sync & FB_SYNC_HOR_HIGH_ACT)
value |= v_HSYNC_POLARITY(1);
if(mode->sync & FB_SYNC_VERT_HIGH_ACT)
value |= v_VSYNC_POLARITY(1);
HDMIWrReg(VIDEO_TIMING_CTL, value);
value = mode->left_margin + mode->xres + mode->right_margin + mode->hsync_len;
HDMIWrReg(VIDEO_EXT_HTOTAL_L, value & 0xFF);
HDMIWrReg(VIDEO_EXT_HTOTAL_H, (value >> 8) & 0xFF);
value = mode->left_margin + mode->right_margin + mode->hsync_len;
HDMIWrReg(VIDEO_EXT_HBLANK_L, value & 0xFF);
HDMIWrReg(VIDEO_EXT_HBLANK_H, (value >> 8) & 0xFF);
value = mode->left_margin + mode->hsync_len;
HDMIWrReg(VIDEO_EXT_HDELAY_L, value & 0xFF);
HDMIWrReg(VIDEO_EXT_HDELAY_H, (value >> 8) & 0xFF);
value = mode->hsync_len;
HDMIWrReg(VIDEO_EXT_HDURATION_L, value & 0xFF);
HDMIWrReg(VIDEO_EXT_HDURATION_H, (value >> 8) & 0xFF);
value = mode->upper_margin + mode->yres + mode->lower_margin + mode->vsync_len;
HDMIWrReg(VIDEO_EXT_VTOTAL_L, value & 0xFF);
HDMIWrReg(VIDEO_EXT_VTOTAL_H, (value >> 8) & 0xFF);
value = mode->upper_margin + mode->vsync_len + mode->lower_margin;
HDMIWrReg(VIDEO_EXT_VBLANK, value & 0xFF);
value = mode->upper_margin + mode->vsync_len;
HDMIWrReg(VIDEO_EXT_VDELAY, value & 0xFF);
value = mode->vsync_len;
HDMIWrReg(VIDEO_EXT_VDURATION, value & 0xFF);
#endif
if(hdmi->edid.is_hdmi) {
rk610_hdmi_config_avi(vic, output_color);
hdmi_dbg(hdmi->dev, "[%s] sucess output HDMI.\n", __FUNCTION__);
}
else {
hdmi_dbg(hdmi->dev, "[%s] sucess output DVI.\n", __FUNCTION__);
}
// Power on TMDS
HDMIWrReg(PHY_PRE_EMPHASIS, v_PRE_EMPHASIS(0) | v_TMDS_PWRDOWN(0)); // TMDS power on
// Enable TMDS
value = 0;
rk610_hdmi_i2c_read_reg(PHY_DRIVER, &value);
value |= v_TX_ENABLE(1);
HDMIWrReg(PHY_DRIVER, value);
return 0;
}
