/**
* intel_dpio_reg_write:
* @reg: register offset
* @val: value to write
* @phy: dpio PHY to use
*
* 32-bit write of the register at @offset through the DPIO sideband port.
*/
void intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy)
{
if (phy == 0)
vlv_sideband_rw(IOSF_PORT_DPIO, SB_MWR_NP, reg, &val);
else
vlv_sideband_rw(IOSF_PORT_DPIO_2, SB_MWR_NP, reg, &val);
}
/**
* intel_dpio_reg_read:
* @reg: register offset
* @phy: DPIO PHY to use
*
* 32-bit read of the register at @offset through the DPIO sideband port.
*
* Returns:
* The value read from the register.
*/
uint32_t intel_dpio_reg_read(uint32_t reg, int phy)
{
uint32_t val;
if (phy == 0)
vlv_sideband_rw(IOSF_PORT_DPIO, SB_MRD_NP, reg, &val);
else
vlv_sideband_rw(IOSF_PORT_DPIO_2, SB_MRD_NP, reg, &val);
return val;
}
u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg)
{
u32 val = 0;
vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPS_CORE,
PUNIT_OPCODE_REG_READ, reg, &val);
return val;
}
u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg)
{
u32 val = 0;
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE,
SB_CRRDDA_NP, reg, &val);
return val;
}
u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)
{
u32 val = 0;
vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
reg, &val);
return val;
}
u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg)
{
u32 val = 0;
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU,
PUNIT_OPCODE_REG_READ, reg, &val);
return val;
}
u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg)
{
u32 val = 0;
vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
SB_CRRDDA_NP, reg, &val);
return val;
}
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
{
u32 val = 0;
vlv_sideband_rw(dev_priv, DPIO_DEVFN, vlv_get_phy_port(pipe),
DPIO_OPCODE_REG_READ, reg, &val);
return val;
}
uint32_t intel_flisdsi_reg_read(uint32_t reg)
{
uint32_t val = 0;
vlv_sideband_rw(IOSF_PORT_FLISDSI, SB_CRRDDA_NP, reg, &val);
return val;
}
void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
{
// mutex_lock(&dev_priv->dpio_lock);
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT,
PUNIT_OPCODE_REG_WRITE, addr, &val);
// mutex_unlock(&dev_priv->dpio_lock);
}
uint32_t intel_iosf_sb_read(uint32_t port, uint32_t reg)
{
uint32_t val;
vlv_sideband_rw(port, SB_CRRDDA_NP, reg, &val);
return val;
}
static int vlv_sideband_rw32_bits(struct drm_i915_private *dev_priv, u32 devfn,
u32 port, u32 opcode, u32 addr, u32 *val, u32 mask)
{
u32 tmp;
int status;
status = vlv_sideband_rw(dev_priv, DPIO_DEVFN, port,
DPIO_OPCODE_REG_READ, addr, &tmp);
if (status != 0)
return status;
tmp = tmp & ~mask;
*val = *val & mask;
tmp = *val | tmp;
return vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_PMC,
DPIO_OPCODE_REG_WRITE, addr, &tmp);
}
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg)
{
u32 val = 0;
vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_DPIO,
DPIO_OPCODE_REG_READ, reg, &val);
return val;
}
void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
{
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
mutex_lock(&dev_priv->dpio_lock);
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT,
SB_CRWRDA_NP, addr, &val);
mutex_unlock(&dev_priv->dpio_lock);
}
/*Changed type of parameter addr from u8 to u16. Can be made to u32 too*/
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u16 addr)
{
u32 val = 0;
// mutex_lock(&dev_priv->dpio_lock);
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_NC,
PUNIT_OPCODE_REG_READ, addr, &val);
// mutex_unlock(&dev_priv->dpio_lock);
return val;
}
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr)
{
u32 val = 0;
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
mutex_lock(&dev_priv->dpio_lock);
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT,
SB_CRRDDA_NP, addr, &val);
mutex_unlock(&dev_priv->dpio_lock);
return val;
}
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
{
u32 val = 0;
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
mutex_lock(&dev_priv->dpio_lock);
vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_NC,
PUNIT_OPCODE_REG_READ, addr, &val);
mutex_unlock(&dev_priv->dpio_lock);
return val;
}
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
{
u32 val = 0;
vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
SB_MRD_NP, reg, &val);
/*
* FIXME: There might be some registers where all 1's is a valid value,
* so ideally we should check the register offset instead...
*/
WARN(val == 0xffffffff, "DPIO read pipe %c reg 0x%x == 0x%x\n",
pipe_name(pipe), reg, val);
return val;
}
void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val)
{
vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
SB_MWR_NP, reg, &val);
}
void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
{
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE,
SB_CRWRDA_NP, reg, &val);
}
void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
{
vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU,
SB_CRWRDA_NP, reg, &val);
}
/**
* intel_nc_read:
* @addr: register offset
* @val: pointer to starge for the read result
*
* 32-bit read of the register at @offset through the NC sideband port.
*
* Returns:
* 0 when the register access succeeded, negative errno code on failure.
*/
int intel_nc_read(uint32_t addr, uint32_t *val)
{
return vlv_sideband_rw(IOSF_PORT_NC, SB_CRRDDA_NP, addr, val);
}
void intel_iosf_sb_write(uint32_t port, uint32_t reg, uint32_t val)
{
vlv_sideband_rw(port, SB_CRWRDA_NP, reg, &val);
}
void intel_flisdsi_reg_write(uint32_t reg, uint32_t val)
{
vlv_sideband_rw(IOSF_PORT_FLISDSI, SB_CRWRDA_NP, reg, &val);
}
void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
{
vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
SB_CRWRDA_NP, reg, &val);
}
/**
* intel_nc_write:
* @addr: register offset
* @val: value to write
*
* 32-bit write of the register at @offset through the NC sideband port.
*
* Returns:
* 0 when the register access succeeded, negative errno code on failure.
*/
int intel_nc_write(uint32_t addr, uint32_t val)
{
return vlv_sideband_rw(IOSF_PORT_NC, SB_CRWRDA_NP, addr, &val);
}
void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
{
vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,
reg, &val);
}
/**
* intel_punit_read:
* @addr: register offset
* @val: pointer to store the read result
*
* 32-bit read of the register at @offset through the P-Unit sideband port.
*
* Returns:
* 0 when the register access succeeded, negative errno code on failure.
*/
int intel_punit_read(uint32_t addr, uint32_t *val)
{
return vlv_sideband_rw(IOSF_PORT_PUNIT, SB_CRRDDA_NP, addr, val);
}
/**
* intel_punit_write:
* @addr: register offset
* @val: value to write
*
* 32-bit write of the register at @offset through the P-Unit sideband port.
*
* Returns:
* 0 when the register access succeeded, negative errno code on failure.
*/
int intel_punit_write(uint32_t addr, uint32_t val)
{
return vlv_sideband_rw(IOSF_PORT_PUNIT, SB_CRWRDA_NP, addr, &val);
}
void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
{
vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC,
SB_CRWRDA_NP, reg, &val);
}
