void mxr_reg_set_mbus_fmt(struct mxr_device *mdev,
struct v4l2_mbus_framefmt *fmt, u32 dvi_mode)
{
u32 val = 0;
unsigned long flags;
spin_lock_irqsave(&mdev->reg_slock, flags);
mxr_vsync_set_update(mdev, MXR_DISABLE);
/* choosing between YUV444 and RGB888 as mixer output type */
if (mdev->sub_mxr[MXR_SUB_MIXER0].mbus_fmt[MXR_PAD_SOURCE_GRP0].code ==
V4L2_MBUS_FMT_YUV8_1X24) {
if (dvi_mode) {
val = MXR_CFG_OUT_RGB888;
fmt->code = V4L2_MBUS_FMT_XRGB8888_4X8_LE;
} else {
val = MXR_CFG_OUT_YUV444;
fmt->code = V4L2_MBUS_FMT_YUV8_1X24;
}
} else {
val = MXR_CFG_OUT_RGB888;
fmt->code = V4L2_MBUS_FMT_XRGB8888_4X8_LE;
}
/* choosing between interlace and progressive mode */
if (fmt->field == V4L2_FIELD_INTERLACED)
val |= MXR_CFG_SCAN_INTERLACE;
else
val |= MXR_CFG_SCAN_PROGRASSIVE;
/* choosing between porper HD and SD mode */
if (fmt->height <= 480)
val |= MXR_CFG_SCAN_NTSC | MXR_CFG_SCAN_SD;
else if (fmt->height <= 576)
val |= MXR_CFG_SCAN_PAL | MXR_CFG_SCAN_SD;
else if (fmt->height <= 720)
val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;
else if (fmt->height <= 1080)
val |= MXR_CFG_SCAN_HD_1080 | MXR_CFG_SCAN_HD;
else {
WARN(1, "unrecognized mbus height %u!\n", fmt->height);
val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;
}
mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_SCAN_MASK |
MXR_CFG_OUT_MASK);
val = (fmt->field == V4L2_FIELD_INTERLACED) ? ~0 : 0;
vp_write_mask(mdev, VP_MODE, val,
VP_MODE_LINE_SKIP | VP_MODE_FIELD_ID_AUTO_TOGGLING);
mxr_vsync_set_update(mdev, MXR_ENABLE);
spin_unlock_irqrestore(&mdev->reg_slock, flags);
}
void mxr_reg_vp_format(struct mxr_device *mdev,
const struct mxr_format *fmt, const struct mxr_geometry *geo)
{
#if defined(CONFIG_ARCH_EXYNOS4)
unsigned long flags;
spin_lock_irqsave(&mdev->reg_slock, flags);
mxr_vsync_set_update(mdev, MXR_DISABLE);
vp_write_mask(mdev, VP_MODE, fmt->cookie, VP_MODE_FMT_MASK);
/* setting size of input image */
vp_write(mdev, VP_IMG_SIZE_Y, VP_IMG_HSIZE(geo->src.full_width) |
VP_IMG_VSIZE(geo->src.full_height));
/* chroma height has to reduced by 2 to avoid chroma distorions */
vp_write(mdev, VP_IMG_SIZE_C, VP_IMG_HSIZE(geo->src.full_width) |
VP_IMG_VSIZE(geo->src.full_height / 2));
vp_write(mdev, VP_SRC_WIDTH, geo->src.width);
vp_write(mdev, VP_SRC_HEIGHT, geo->src.height);
vp_write(mdev, VP_SRC_H_POSITION,
VP_SRC_H_POSITION_VAL(geo->src.x_offset));
vp_write(mdev, VP_SRC_V_POSITION, geo->src.y_offset);
vp_write(mdev, VP_DST_WIDTH, geo->dst.width);
vp_write(mdev, VP_DST_H_POSITION, geo->dst.x_offset);
if (geo->dst.field == V4L2_FIELD_INTERLACED) {
vp_write(mdev, VP_DST_HEIGHT, geo->dst.height / 2);
vp_write(mdev, VP_DST_V_POSITION, geo->dst.y_offset / 2);
} else {
vp_write(mdev, VP_DST_HEIGHT, geo->dst.height);
vp_write(mdev, VP_DST_V_POSITION, geo->dst.y_offset);
}
vp_write(mdev, VP_H_RATIO, geo->x_ratio);
vp_write(mdev, VP_V_RATIO, geo->y_ratio);
vp_write(mdev, VP_ENDIAN_MODE, VP_ENDIAN_MODE_LITTLE);
mxr_vsync_set_update(mdev, MXR_ENABLE);
spin_unlock_irqrestore(&mdev->reg_slock, flags);
#endif
}
void mxr_reg_set_mbus_fmt(struct mxr_device *mdev,
struct v4l2_mbus_framefmt *fmt)
{
u32 val = 0;
unsigned long flags;
spin_lock_irqsave(&mdev->reg_slock, flags);
mxr_vsync_set_update(mdev, MXR_DISABLE);
if (fmt->colorspace == V4L2_COLORSPACE_JPEG)
val |= MXR_CFG_OUT_YUV444;
else
val |= MXR_CFG_OUT_RGB888;
if (fmt->field == V4L2_FIELD_INTERLACED)
val |= MXR_CFG_SCAN_INTERLACE;
else
val |= MXR_CFG_SCAN_PROGRASSIVE;
if (fmt->height == 480)
val |= MXR_CFG_SCAN_NTSC | MXR_CFG_SCAN_SD;
else if (fmt->height == 576)
val |= MXR_CFG_SCAN_PAL | MXR_CFG_SCAN_SD;
else if (fmt->height == 720)
val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;
else if (fmt->height == 1080)
val |= MXR_CFG_SCAN_HD_1080 | MXR_CFG_SCAN_HD;
else
WARN(1, "unrecognized mbus height %u!\n", fmt->height);
mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_SCAN_MASK |
MXR_CFG_OUT_MASK);
val = (fmt->field == V4L2_FIELD_INTERLACED) ? ~0 : 0;
vp_write_mask(mdev, VP_MODE, val,
VP_MODE_LINE_SKIP | VP_MODE_FIELD_ID_AUTO_TOGGLING);
mxr_vsync_set_update(mdev, MXR_ENABLE);
spin_unlock_irqrestore(&mdev->reg_slock, flags);
}
void mxr_reg_vp_buffer(struct mxr_device *mdev,
dma_addr_t luma_addr[2], dma_addr_t chroma_addr[2])
{
u32 val = luma_addr[0] ? ~0 : 0;
unsigned long flags;
spin_lock_irqsave(&mdev->reg_slock, flags);
mxr_vsync_set_update(mdev, MXR_DISABLE);
mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_VP_ENABLE);
vp_write_mask(mdev, VP_ENABLE, val, VP_ENABLE_ON);
/* TODO: fix tiled mode */
vp_write(mdev, VP_TOP_Y_PTR, luma_addr[0]);
vp_write(mdev, VP_TOP_C_PTR, chroma_addr[0]);
vp_write(mdev, VP_BOT_Y_PTR, luma_addr[1]);
vp_write(mdev, VP_BOT_C_PTR, chroma_addr[1]);
mxr_vsync_set_update(mdev, MXR_ENABLE);
spin_unlock_irqrestore(&mdev->reg_slock, flags);
}
void mxr_reg_set_mbus_fmt(struct mxr_device *mdev,
struct v4l2_mbus_framefmt *fmt)
{
u32 val = 0;
unsigned long flags;
spin_lock_irqsave(&mdev->reg_slock, flags);
mxr_vsync_set_update(mdev, MXR_DISABLE);
/* choosing between interlace and progressive mode */
if (fmt->field == V4L2_FIELD_INTERLACED)
val |= MXR_CFG_SCAN_INTERLACE;
else
val |= MXR_CFG_SCAN_PROGRASSIVE;
/* choosing between porper HD and SD mode */
if (fmt->height == 480)
val |= MXR_CFG_SCAN_NTSC | MXR_CFG_SCAN_SD;
else if (fmt->height == 576)
val |= MXR_CFG_SCAN_PAL | MXR_CFG_SCAN_SD;
else if (fmt->height == 720)
val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;
else if (fmt->height == 1080)
val |= MXR_CFG_SCAN_HD_1080 | MXR_CFG_SCAN_HD;
else
WARN(1, "unrecognized mbus height %u!\n", fmt->height);
mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_SCAN_MASK);
val = (fmt->field == V4L2_FIELD_INTERLACED) ? ~0 : 0;
vp_write_mask(mdev, VP_MODE, val,
VP_MODE_LINE_SKIP | VP_MODE_FIELD_ID_AUTO_TOGGLING);
mxr_vsync_set_update(mdev, MXR_ENABLE);
spin_unlock_irqrestore(&mdev->reg_slock, flags);
}
