/*----------------------- GOVW CSC --------------------------------------*/
void govw_set_csc_mode(vpp_csc_t mode)
{
vdo_color_fmt src_fmt,dst_fmt;
#ifdef WMT_FTBLK_PIP
src_fmt = govm_get_pip_color_format();
// src_fmt = vpu_r_get_color_format();
dst_fmt = govw_get_hd_color_format();
#else
src_fmt = VDO_COL_FMT_YUV444;
dst_fmt = govw_get_hd_color_format();
// mode = VPP_CSC_MAX;
#endif
mode = vpp_check_csc_mode(mode,src_fmt,dst_fmt,0);
if (mode >= VPP_CSC_MAX) {
vppif_reg32_out(REG_GOVW_CSC_COEF1, 0x400); //CSC1
vppif_reg32_out(REG_GOVW_CSC_COEF2, 0x0); //CSC2
vppif_reg32_out(REG_GOVW_CSC_COEF3, 0x400); //CSC3
vppif_reg32_out(REG_GOVW_CSC_COEF4, 0x0); //CSC4
vppif_reg32_out(REG_GOVW_CSC_COEF5, 0x400); //CSC5
vppif_reg32_out(REG_GOVW_CSC_COEF6, 0x0); //CSC6
vppif_reg32_out(REG_GOVW_CSC_MODE, 0x0); //CSC_CTL
vppif_reg32_write(GOVW_CSC_ENABLE,0);
} else {
vppif_reg32_out(REG_GOVW_CSC_COEF1, vpp_csc_parm[mode][0]); //CSC1
vppif_reg32_out(REG_GOVW_CSC_COEF2, vpp_csc_parm[mode][1]); //CSC2
vppif_reg32_out(REG_GOVW_CSC_COEF3, vpp_csc_parm[mode][2]); //CSC3
vppif_reg32_out(REG_GOVW_CSC_COEF4, vpp_csc_parm[mode][3]); //CSC4
vppif_reg32_out(REG_GOVW_CSC_COEF5, vpp_csc_parm[mode][4]); //CSC5
vppif_reg32_out(REG_GOVW_CSC_COEF6, vpp_csc_parm[mode][5]); //CSC6
vppif_reg32_out(REG_GOVW_CSC_MODE, vpp_csc_parm[mode][6]); //CSC_CTL
vppif_reg32_write(GOVW_CSC_ENABLE,1);
}
}
void scl_set_csc_mode(vpp_csc_t mode)
{
vdo_color_fmt src_fmt,dst_fmt;
src_fmt = sclr_get_color_format();
dst_fmt = ( scl_get_timing_master() == VPP_MOD_SCL )? sclw_get_color_format():govw_get_color_format();
mode = vpp_check_csc_mode(mode,src_fmt,dst_fmt,0);
if (mode >= VPP_CSC_MAX) {
vppif_reg32_write(SCL_CSC_ENABLE, VPP_FLAG_DISABLE);
} else {
vppif_reg32_out(REG_SCL_CSC1, vpp_csc_parm[mode][0]); //CSC1
vppif_reg32_out(REG_SCL_CSC2, vpp_csc_parm[mode][1]); //CSC2
vppif_reg32_out(REG_SCL_CSC3, vpp_csc_parm[mode][2]); //CSC3
vppif_reg32_out(REG_SCL_CSC4, vpp_csc_parm[mode][3]); //CSC4
vppif_reg32_out(REG_SCL_CSC5, vpp_csc_parm[mode][4]); //CSC5
vppif_reg32_out(REG_SCL_CSC6, vpp_csc_parm[mode][5]); //CSC6
vppif_reg32_out(REG_SCL_CSC_CTL, vpp_csc_parm[mode][6]); //CSC_CTL
vppif_reg32_write(SCL_CSC_ENABLE, VPP_FLAG_ENABLE);
}
}
