void sclw_set_fb_addr(U32 y_addr,U32 c_addr)
{
DBGMSG("y_addr:0x%08x, c_addr:0x%08x\n",y_addr,c_addr);
// if( (y_addr & 0x3f) || (c_addr & 0x3f) ){
// DPRINT("[SCL] *E* addr should align 64\n");
// }
vppif_reg32_out(REG_SCLW_YSA,y_addr);
vppif_reg32_out(REG_SCLW_CSA,c_addr);
}
void scl_set_scale(unsigned int SRC_W,unsigned int SRC_H,unsigned int DST_W,unsigned int DST_H)
{
int h_scale_up;
int v_scale_up;
DBGMSG("[SCL] src(%dx%d),dst(%dx%d)\n",SRC_W,SRC_H,DST_W,DST_H);
h_scale_up = ( DST_W > SRC_W )? 1:0;
v_scale_up = ( DST_H > SRC_H )? 1:0;
if( ((DST_W / SRC_W) >= 32) || ((DST_W / SRC_W) < 1/32) ){
DBGMSG("*W* SCL H scale rate invalid\n");
}
if( ((DST_H / SRC_H) >= 32) || ((DST_H / SRC_H) < 1/32) ){
DBGMSG("*W* SCL V scale rate invalid\n");
}
// DBGMSG("scale H %d,V %d\n",h_scale_up,v_scale_up);
sclr_set_mif2_enable(VPP_FLAG_DISABLE);
scl_set_scale_PP(SRC_W,DST_W,1);
if( h_scale_up ){ // max 32
vppif_reg32_out(REG_SCL_HSCL_TB0,3);
vppif_reg32_out(REG_SCL_HPTR,0);
vppif_reg32_write(SCL_BILINEAR_H,0);
}
else { // min 1/32
vppif_reg32_out(REG_SCL_HSCL_TB0,1);
scl_set_scale_RT(SRC_W,DST_W,1);
}
scl_set_scale_PP(SRC_H,DST_H,0);
if( v_scale_up ){ // max 32
vppif_reg32_out(REG_SCL_VSCL_TB0,3);
vppif_reg32_out(REG_SCL_VPTR,0);
}
else { // min 1/16
scl_set_scale_RT(SRC_H,DST_H,0);
// mif2 enable in real quality mode,only mif1 in SCL recursive mode
if( vppif_reg32_read(SCL_TG_GOVWTG_ENABLE) && (vppif_reg32_read(SCL_SCLDW_METHOD)==0)){
sclr_set_mif2_enable(VPP_FLAG_ENABLE);
}
}
scl_set_scale_enable(v_scale_up, h_scale_up);
}
void vppm_set_module_reset(vpp_mod_t mod)
{
unsigned int value1 = 0x00, value2 = 0x00;
#if 0
#ifdef WMT_FTBLK_GE
if(mod == VPP_MOD_GE)
value1 |= BIT16;
#endif
#ifdef WMT_FTBLK_VID
if(mod == VPP_MOD_VID)
value1 |= BIT8;
#endif
#endif
#ifdef WMT_FTBLK_SCL
if(mod == VPP_MOD_SCL)
value1 |= BIT0;
#endif
#ifdef WMT_FTBLK_GOVW
if(mod == VPP_MOD_GOVW)
value2 |= BIT16;
#endif
#ifdef WMT_FTBLK_GOVRH
if(mod & VPP_MOD_GOVRH) {
value2 |= (BIT0 | BIT8);
g_vpp.govrh_field = VPP_FIELD_BOTTOM;
}
#endif
#ifdef WMT_FTBLK_VPU
if(mod == VPP_MOD_VPU)
value1 |= BIT24;
#endif
#ifdef WMT_FTBLK_DISP
if(mod == VPP_MOD_DISP)
value2 |= BIT24;
#endif
#ifdef WMT_FTBLK_LVDS
// if(mod == VPP_MOD_LVDS)
value2 |= BIT4;
#endif
vppif_reg32_out(REG_VPP_SWRST1_SEL, ~value1);
vppif_reg32_out(REG_VPP_SWRST1_SEL, 0x1010101);
vppif_reg32_out(REG_VPP_SWRST2_SEL, ~value2);
vppif_reg32_out(REG_VPP_SWRST2_SEL, 0x1010111);
}
void sclr_set_fb_addr(U32 y_addr, U32 c_addr)
{
unsigned int line_y,line_c;
unsigned int offset_y,offset_c;
unsigned int pre_y,pre_c;
DBGMSG("y_addr:0x%08x, c_addr:0x%08x\n",y_addr,c_addr);
offset_y = offset_c = 0;
line_y = line_c = vppif_reg32_read(SCLR_YBUFWID);
switch(sclr_get_color_format()){
case VDO_COL_FMT_YUV420:
offset_c /= 2;
line_c = 0;
break;
case VDO_COL_FMT_YUV422H:
break;
case VDO_COL_FMT_ARGB:
offset_y *= 4;
line_y *= 4;
break;
case VDO_COL_FMT_RGB_565:
offset_y *= 2;
line_y *= 2;
break;
default:
offset_c *= 2;
line_c *= 2;
break;
}
pre_y = vppif_reg32_in(REG_SCLR_YSA);
pre_c = vppif_reg32_in(REG_SCLR_CSA);
vppif_reg32_out(REG_SCLR_YSA,y_addr+offset_y);
vppif_reg32_out(REG_SCLR_CSA,c_addr+offset_c);
switch(scl_get_filter_mode()){
default:
case VPP_FILTER_SCALE:
case VPP_FILTER_FIELD_DEFLICKER:
vppif_reg32_out(REG_SCLR_YSA2,y_addr+offset_y+line_y);
vppif_reg32_out(REG_SCLR_CSA2,c_addr+offset_c+line_c);
break;
case VPP_FILTER_DEBLOCK:
vppif_reg32_out(REG_SCLR_YSA2,y_addr+offset_y);
vppif_reg32_out(REG_SCLR_CSA2,c_addr+offset_c);
break;
case VPP_FILTER_FRAME_DEFLICKER:
// next frame buffer address
vppif_reg32_out(REG_SCLR_YSA2,pre_y);
vppif_reg32_out(REG_SCLR_CSA2,pre_c);
break;
}
}
void scl_clean_int_status(vpp_int_err_t int_sts)
{
if (int_sts & VPP_INT_ERR_SCL_TG) {
vppif_reg32_out(REG_SCL_TG_STS+0x0,BIT0);
}
if (int_sts & VPP_INT_ERR_SCLR1_MIF) {
vppif_reg8_out(REG_SCLR_FIFO_CTL+0x1,BIT0);
}
if (int_sts & VPP_INT_ERR_SCLR2_MIF) {
vppif_reg8_out(REG_SCLR_FIFO_CTL+0x1,BIT1);
}
if (int_sts & VPP_INT_ERR_SCLW_MIFRGB) {
vppif_reg32_out(REG_SCLW_FF_CTL,BIT16);
}
if (int_sts & VPP_INT_ERR_SCLW_MIFY) {
vppif_reg32_out(REG_SCLW_FF_CTL,BIT8);
}
if (int_sts & VPP_INT_ERR_SCLW_MIFC) {
vppif_reg32_out(REG_SCLW_FF_CTL,BIT0);
}
}
int scl_proc_scale_complete(void *arg)
{
// DPRINT("[SCL] scl_proc_scale_complete\n");
if( vppif_reg32_read(SCL_INTSTS_TGERR) ){
DPRINT("[SCL] scale TG err 0x%x,0x%x\n",vppif_reg32_in(REG_SCL_TG_STS),vppif_reg32_in(REG_SCLW_FF_CTL));
vppif_reg32_out(REG_SCL_TG_STS+0x0,BIT0);
vppif_reg32_out(REG_SCLW_FF_CTL,0x10101);
}
scl_set_tg_enable(VPP_FLAG_DISABLE);
vppm_set_int_enable(VPP_FLAG_DISABLE,SCL_COMPLETE_INT);
sclw_set_mif_enable(VPP_FLAG_DISABLE);
sclr_set_mif_enable(VPP_FLAG_DISABLE);
sclr_set_mif2_enable(VPP_FLAG_DISABLE);
scl_set_enable(VPP_FLAG_DISABLE);
//#ifdef __KERNEL__
#if 0
INIT_WORK(&scl_proc_scale_wq, scl_proc_scale_complete_work);
schedule_work(&scl_proc_scale_wq);
#else
scl_proc_scale_complete_work(0);
#endif
return 0;
}
void govw_clean_int_status(vpp_int_err_t int_sts)
{
unsigned int reg;
reg = vppif_reg32_in(REG_GOVW_INT) & 0xFF;
if (int_sts & VPP_INT_ERR_GOVW_TG) {
reg |= BIT20;
}
if (int_sts & VPP_INT_ERR_GOVW_MIFY) {
reg |= BIT19;
}
if (int_sts & VPP_INT_ERR_GOVW_MIFC) {
reg |= BIT18;
}
vppif_reg32_out(REG_GOVW_INT,reg);
}
/*!
* \brief
*
* \retval 0 if success
*/
static int __init wmt_cec_probe
(
struct platform_device *dev /*!<; // a pointer point to struct device */
)
{
dev_t dev_no;
int ret;
DBGMSG("[CEC] Enter wmt_cec_probe\n");
wmt_cec_init_hw();
// wmt_cec_set_logical_addr(0,0x4,1);
wmt_cec_set_logical_addr(4,0xf,1); // default set boardcast address
wmt_cec_rx_enable(0);
// wmt_cec_enable_loopback(1);
dev_no = MKDEV(CEC_MAJOR, 0);
ret = register_chrdev_region(dev_no,1,"wmtcec");
if( ret < 0 ){
printk("can't get %s device major %d\n",DRIVER_NAME, CEC_MAJOR);
return ret;
}
/* register char device */
wmt_cec_cdev = cdev_alloc();
if(!wmt_cec_cdev){
DPRINT("alloc dev error.\n");
return -ENOMEM;
}
cdev_init(wmt_cec_cdev,&wmt_cec_fops);
ret = cdev_add(wmt_cec_cdev,dev_no,1);
if(ret){
DPRINT("reg char dev error(%d).\n",ret);
cdev_del(wmt_cec_cdev);
return ret;
}
if ( vpp_request_irq(IRQ_VPP_IRQ20, wmt_cec_do_irq, SA_INTERRUPT, "cec", (void *) 0) ) {
DPRINT("*E* request CEC ISR fail\n");
}
vppif_reg32_out(REG_CEC_INT_ENABLE,0x1f);
DBGMSG("[CEC] Exit wmt_cec_probe(0x%x)\n",dev_no);
return 0;
} /* End of wmt_cec_probe */
void wmt_cec_do_resume(void)
{
vppif_reg32_out(REG_VPP_SWRST2_SEL, 0x1011111);
/* disable GPIO function */
vppif_reg32_write(GPIO_BASE_ADDR + 0x40, BIT4, 4, 0);
/* GPIO4 disable GPIO out */
vppif_reg32_write(GPIO_BASE_ADDR + 0x80, BIT4, 4, 0);
/* GPIO4 disable pull ctrl */
vppif_reg32_write(GPIO_BASE_ADDR + 0x480, BIT4, 4, 0);
/* Suspend GPIO output enable */
vppif_reg32_write(GPIO_BASE_ADDR + 0x80, BIT23, 23, 1);
/* Suspend GPIO output high */
vppif_reg32_write(GPIO_BASE_ADDR + 0xC0, BIT23, 23, 1);
/* Wake3 disable pull ctrl */
vppif_reg32_write(GPIO_BASE_ADDR + 0x480, BIT19, 19, 0);
vpp_restore_reg(REG_CEC_BEGIN,
(REG_CEC_END - REG_CEC_BEGIN), wmt_cec_pm_bk);
wmt_cec_pm_bk = 0;
}
/*---------------------------- CEC HAL --------------------------------------*/
void wmt_cec_tx_data(char *buf, int size)
{
int i;
unsigned int addr, reg;
int wait_idle;
#ifdef DEBUG
DPRINT("[CEC] tx data(%d):", size);
for (i = 0; i < size; i++)
DPRINT(" 0x%x", buf[i]);
DPRINT("\n");
#endif
if (size > 16) {
DPRINT("[CEC] *W* size max 16\n");
return;
}
wait_idle = 0;
while (vppif_reg32_read(CEC_WR_START)) { /* wait idle */
if (wait_idle >= 10) {
DPRINT("[CEC] wait idle timeout\n");
return;
}
wait_idle++;
mdelay(10);
return;
}
addr = REG_CEC_ENCODE_HEADER;
for (i = 0; i < size; i++) {
reg = (buf[i] << 4) + 0x1;
if (i == (size - 1))
reg |= BIT1;
vppif_reg32_out(addr, reg);
#ifdef DEBUG
DPRINT("[CEC] wr 0x%x = 0x%x\n", addr, reg);
#endif
addr += 4;
}
vppif_reg32_write(CEC_WR_NUM, (size * 10) + 0x1);
vppif_reg32_write(CEC_WR_START, 1);
}
static void scl_scale_bilinear(int src,int dst,int h)
{
unsigned int tb0,tb1;
unsigned int pos,index;
int i;
index = 1;
tb0 = 0xc;
tb1 = 0x0;
for(i=2;i<src;i++){
pos = src * index;
pos = (pos / dst) + ((pos % dst)? 1:0);
if( pos == i ){
if(i<16)
tb0 = tb0 + (0x3 << (i*2));
else
tb1 = tb1 + (0x3 << ((i-16)*2));
index++;
}
}
index = 0;
while( index == 0 ){
if( src <= 16 )
index = tb0 & (0x3 << ((src-1)*2));
else
index = tb1 & (0x3 << ((src-17)*2));
if( index == 0 ){
if( (tb0 & 0xc0000000) == 0 )
tb1 = tb1 << 2;
else
tb1 = (tb1 << 2) + 0x3;
tb0 = tb0 << 2;
}
}
if( h ){
vppif_reg32_write(SCL_BILINEAR_H,1);
vppif_reg32_out(REG_SCL_HSCL_TB0,tb0);
vppif_reg32_out(REG_SCL_HSCL_TB1,tb1);
vppif_reg32_out(REG_SCL_HPTR,src-1);
}
else {
vppif_reg32_write(SCL_BILINEAR_V,1);
vppif_reg32_out(REG_SCL_VSCL_TB0,tb0);
vppif_reg32_out(REG_SCL_VSCL_TB1,tb1);
vppif_reg32_out(REG_SCL_VPTR,src-1);
}
}
void wmt_cec_init_hw(void)
{
wmt_cec_set_clock();
vppif_reg32_write(CEC_WR_RETRY, 3);
vppif_reg32_out(REG_CEC_RX_TRIG_RANGE, 2);
vppif_reg32_write(CEC_FREE_3X, 3);
vppif_reg32_write(CEC_FREE_5X, 5);
vppif_reg32_write(CEC_FREE_7X, 7);
vppif_reg32_write(CEC_COMP_DISABLE, 1);
vppif_reg32_write(CEC_ERR_HANDLE_DISABLE, 0);
vppif_reg32_write(CEC_NO_ACK_DISABLE, 0);
vppif_reg32_write(CEC_DECODE_FULL_DISABLE, 0);
vppif_reg32_write(CEC_STATUS4_START_DISABLE, 1);
vppif_reg32_write(CEC_STATUS4_LOGIC0_DISABLE, 1);
vppif_reg32_write(CEC_STATUS4_LOGIC1_DISABLE, 1);
/* 1 : read self write and all dest data */
vppif_reg32_write(CEC_RD_ENCODE_ENABLE, 0);
}
void scl_set_csc_mode(vpp_csc_t mode)
{
vdo_color_fmt src_fmt,dst_fmt;
src_fmt = sclr_get_color_format();
dst_fmt = ( scl_get_timing_master() == VPP_MOD_SCL )? sclw_get_color_format():govw_get_color_format();
mode = vpp_check_csc_mode(mode,src_fmt,dst_fmt,0);
if (mode >= VPP_CSC_MAX) {
vppif_reg32_write(SCL_CSC_ENABLE, VPP_FLAG_DISABLE);
} else {
vppif_reg32_out(REG_SCL_CSC1, vpp_csc_parm[mode][0]); //CSC1
vppif_reg32_out(REG_SCL_CSC2, vpp_csc_parm[mode][1]); //CSC2
vppif_reg32_out(REG_SCL_CSC3, vpp_csc_parm[mode][2]); //CSC3
vppif_reg32_out(REG_SCL_CSC4, vpp_csc_parm[mode][3]); //CSC4
vppif_reg32_out(REG_SCL_CSC5, vpp_csc_parm[mode][4]); //CSC5
vppif_reg32_out(REG_SCL_CSC6, vpp_csc_parm[mode][5]); //CSC6
vppif_reg32_out(REG_SCL_CSC_CTL, vpp_csc_parm[mode][6]); //CSC_CTL
vppif_reg32_write(SCL_CSC_ENABLE, VPP_FLAG_ENABLE);
}
}
/*----------------------- GOVW CSC --------------------------------------*/
void govw_set_csc_mode(vpp_csc_t mode)
{
vdo_color_fmt src_fmt,dst_fmt;
#ifdef WMT_FTBLK_PIP
src_fmt = govm_get_pip_color_format();
// src_fmt = vpu_r_get_color_format();
dst_fmt = govw_get_hd_color_format();
#else
src_fmt = VDO_COL_FMT_YUV444;
dst_fmt = govw_get_hd_color_format();
// mode = VPP_CSC_MAX;
#endif
mode = vpp_check_csc_mode(mode,src_fmt,dst_fmt,0);
if (mode >= VPP_CSC_MAX) {
vppif_reg32_out(REG_GOVW_CSC_COEF1, 0x400); //CSC1
vppif_reg32_out(REG_GOVW_CSC_COEF2, 0x0); //CSC2
vppif_reg32_out(REG_GOVW_CSC_COEF3, 0x400); //CSC3
vppif_reg32_out(REG_GOVW_CSC_COEF4, 0x0); //CSC4
vppif_reg32_out(REG_GOVW_CSC_COEF5, 0x400); //CSC5
vppif_reg32_out(REG_GOVW_CSC_COEF6, 0x0); //CSC6
vppif_reg32_out(REG_GOVW_CSC_MODE, 0x0); //CSC_CTL
vppif_reg32_write(GOVW_CSC_ENABLE,0);
} else {
vppif_reg32_out(REG_GOVW_CSC_COEF1, vpp_csc_parm[mode][0]); //CSC1
vppif_reg32_out(REG_GOVW_CSC_COEF2, vpp_csc_parm[mode][1]); //CSC2
vppif_reg32_out(REG_GOVW_CSC_COEF3, vpp_csc_parm[mode][2]); //CSC3
vppif_reg32_out(REG_GOVW_CSC_COEF4, vpp_csc_parm[mode][3]); //CSC4
vppif_reg32_out(REG_GOVW_CSC_COEF5, vpp_csc_parm[mode][4]); //CSC5
vppif_reg32_out(REG_GOVW_CSC_COEF6, vpp_csc_parm[mode][5]); //CSC6
vppif_reg32_out(REG_GOVW_CSC_MODE, vpp_csc_parm[mode][6]); //CSC_CTL
vppif_reg32_write(GOVW_CSC_ENABLE,1);
}
}
void sclw_set_framebuffer(vdo_framebuf_t *fb)
{
vdo_framebuf_t *scl_fb; // source
vpp_clock_t timing;
unsigned int pixel_clock;
int h,v;
sclw_set_fb_addr(fb->y_addr, fb->c_addr);
sclw_set_color_format(fb->col_fmt);
sclw_set_fb_width(fb->img_w, fb->fb_w);
sclw_set_field_mode(vpp_get_fb_field(fb));
scl_fb = &p_scl->fb_p->fb;
scl_set_scale(scl_fb->img_w, scl_fb->img_h, fb->img_w, fb->img_h);
{
int rec_h,rec_v;
h = rec_h = 0;
if( scl_fb->img_w > fb->img_w ){ // scale down
switch(p_scl->scale_mode){
case VPP_SCALE_MODE_ADAPTIVE:
if( (fb->img_w * 2) > scl_fb->img_w ){ // 1 > mode(3) > 1/2
h = 1; // bilinear mode
}
else {
rec_h = 1; // recursive mode
}
break;
case VPP_SCALE_MODE_BILINEAR:
h = 1; // bilinear mode
break;
case VPP_SCALE_MODE_RECURSIVE:
rec_h = 1; // recursive mode
break;
default:
break;
}
}
v = rec_v = 0;
if( scl_fb->img_h > fb->img_h ){ // scale down
switch(p_scl->scale_mode){
case VPP_SCALE_MODE_ADAPTIVE:
if( ((fb->img_h * 2) > scl_fb->img_h) && ((scl_fb->fb_w % 64) == 0) ){ // 1 > mode(3) > 1/2
v = 1; // bilinear mode
}
else {
rec_v = 1; // recursive mode
}
break;
case VPP_SCALE_MODE_BILINEAR:
v = 1; // bilinear mode
break;
case VPP_SCALE_MODE_RECURSIVE:
rec_v = 1; // recursive mode
break;
default:
break;
}
}
if( p_scl->scale_mode != VPP_SCALE_MODE_REC_TABLE ){
vppif_reg32_out(REG_SCL_HRES_TB,0);
vppif_reg32_out(REG_SCL_VRES_TB,0);
}
vppif_reg32_write(SCL_BILINEAR_H,h);
vppif_reg32_write(SCL_BILINEAR_V,v);
vppif_reg32_write(SCL_RECURSIVE_H,rec_h);
vppif_reg32_write(SCL_RECURSIVE_V,rec_v);
// vertical bilinear mode
if( v ){
vppif_reg32_write(SCL_VXWIDTH,vppif_reg32_read(SCL_VXWIDTH)-1);
vppif_reg32_write(SCL_DST_VXWIDTH,vppif_reg32_read(SCL_VXWIDTH));
}
sclr_set_mif2_enable((v)? VPP_FLAG_ENABLE:VPP_FLAG_DISABLE);
// DPRINT("[SCL] bil h %d,v %d, rec h %d,v %d\n",h,v,rec_h,rec_v);
}
p_scl->fb_p->set_csc(p_scl->fb_p->csc_mode);
// scl TG
timing.total_pixel_of_line = (fb->img_w > scl_fb->img_w)?fb->img_w:scl_fb->img_w;
if( v ){
timing.total_line_of_frame = fb->img_h;
}
else {
timing.total_line_of_frame = (fb->img_h> scl_fb->img_h)?fb->img_h:scl_fb->img_h;
}
timing.begin_pixel_of_active = 60;
timing.end_pixel_of_active = timing.total_pixel_of_line + 60;
timing.total_pixel_of_line = timing.total_pixel_of_line + 120;
timing.begin_line_of_active = 8;
timing.end_line_of_active = timing.total_line_of_frame + 8;
timing.total_line_of_frame = timing.total_line_of_frame + 16;
timing.line_number_between_VBIS_VBIE = 4;
timing.line_number_between_PVBI_VBIS = 1;
pixel_clock = timing.total_pixel_of_line * timing.total_line_of_frame * p_scl->fb_p->framerate;
scl_set_timing(&timing,pixel_clock);
}
void govw_set_hd_fb_addr(U32 y_addr,U32 c_addr)
{
// DBGMSG("y_addr:0x%08x, c_addr:0x%08x\n",y_addr,c_addr);
vppif_reg32_out(REG_GOVW_HD_YSA,y_addr);
vppif_reg32_out(REG_GOVW_HD_CSA,c_addr);
}
int scl_do_recursive_scale(vdo_framebuf_t *src_fb,vdo_framebuf_t *dst_fb)
{
int ret = 0;
vpp_filter_mode_t filter;
vpp_mod_set_clock(VPP_MOD_SCL,VPP_FLAG_ENABLE,0);
scl_set_timing_master(VPP_MOD_SCL);
filter = ( (src_fb->img_w == dst_fb->img_w) && (src_fb->img_h == dst_fb->img_h) )? p_scl->filter_mode:VPP_FILTER_SCALE;
scl_set_filter_mode(filter,1);
p_scl->fb_p->fb = *src_fb;
p_scl->fb_p->set_framebuf(src_fb);
#ifdef CONFIG_HW_SCL_SCALEDN_GARBAGE_EDGE
// The ¡§start address¡¨ and ¡§start address + Horizontal active size¡¨ have to be
// avoiding the following offset failed address offset : ( 34 , 36 , 38 ) + n*64
{
unsigned int beg,end;
unsigned int temp;
beg = dst_fb->y_addr;
end = dst_fb->y_addr + dst_fb->img_w - 1;
temp = beg % 64;
if( (temp >=34) && (temp <=38) ){
temp = 40 - temp;
dst_fb->y_addr += temp;
dst_fb->c_addr += temp * ((dst_fb->col_fmt==VDO_COL_FMT_YUV444)?2:1);
beg += temp;
}
temp = end % 64;
if( (temp >=34) && (temp <=38) ){
end -= (temp - 32);
dst_fb->img_w = end - beg;
}
}
#endif
p_sclw->fb_p->fb = *dst_fb;
p_sclw->fb_p->set_framebuf(dst_fb);
// scale process
scl_set_enable(VPP_FLAG_ENABLE);
sclr_set_mif_enable(VPP_FLAG_ENABLE);
if( filter != VPP_FILTER_SCALE )
sclr_set_mif2_enable(VPP_FLAG_ENABLE);
#if 1
// #ifdef SCL_ONESHOT_ENABLE
vppif_reg32_write(SCL_ONESHOT_ENABLE,1);
#endif
sclw_set_mif_enable(VPP_FLAG_ENABLE);
scl_set_tg_enable(VPP_FLAG_ENABLE);
#ifdef CONFIG_VPP_CHECK_SCL_STATUS
vppif_reg32_out(REG_SCL_TG_STS+0x0,BIT0);
vppif_reg32_out(REG_SCLW_FF_CTL,0x10101);
#endif
scl_scale_complete = 0;
vppm_set_int_enable(VPP_FLAG_ENABLE,SCL_COMPLETE_INT);
if( p_scl->scale_sync ){
vpp_irqproc_work(SCL_COMPLETE_INT,scl_proc_scale_complete,0,1);
scl_proc_scale_finish();
}
else {
vpp_irqproc_work(SCL_COMPLETE_INT,scl_proc_scale_complete,0,0);
}
return ret;
}
void wmt_cec_clr_int(int sts)
{
vppif_reg32_out(REG_CEC_STATUS, sts);
}
void wmt_cec_set_clock(void)
{
#define CEC_CLOCK (1000000 / 7984)
vppif_reg32_out(REG_CEC_WR_START_SET0, 370 * CEC_CLOCK); /* 3.7 ms */
vppif_reg32_out(REG_CEC_WR_START_SET1, 450 * CEC_CLOCK); /* 4.5 ms */
vppif_reg32_out(REG_CEC_WR_LOGIC0_SET0, 150 * CEC_CLOCK); /* 1.5 ms */
vppif_reg32_out(REG_CEC_WR_LOGIC0_SET1, 240 * CEC_CLOCK); /* 2.4 ms */
vppif_reg32_out(REG_CEC_WR_LOGIC1_SET0, 60 * CEC_CLOCK); /* 0.6 ms */
vppif_reg32_out(REG_CEC_WR_LOGIC1_SET1, 240 * CEC_CLOCK); /* 2.4 ms */
vppif_reg32_out(REG_CEC_RD_START_L_SET0, 350 * CEC_CLOCK); /* 3.5 ms */
vppif_reg32_out(REG_CEC_RD_START_R_SET0, 390 * CEC_CLOCK); /* 3.9 ms */
vppif_reg32_out(REG_CEC_RD_START_L_SET1, 430 * CEC_CLOCK); /* 4.3 ms */
vppif_reg32_out(REG_CEC_RD_START_R_SET1, 470 * CEC_CLOCK); /* 4.7 ms */
vppif_reg32_out(REG_CEC_RD_LOGIC0_L_SET0, 130 * CEC_CLOCK); /* 1.3 ms */
vppif_reg32_out(REG_CEC_RD_LOGIC0_R_SET0, 170 * CEC_CLOCK); /* 1.7 ms */
vppif_reg32_out(REG_CEC_RD_LOGIC0_L_SET1, 205 * CEC_CLOCK); /* 2.05 ms*/
vppif_reg32_out(REG_CEC_RD_LOGIC0_R_SET1, 275 * CEC_CLOCK); /* 2.75 ms*/
vppif_reg32_out(REG_CEC_RD_LOGIC1_L_SET0, 40 * CEC_CLOCK); /* 0.4 ms */
vppif_reg32_out(REG_CEC_RD_LOGIC1_R_SET0, 80 * CEC_CLOCK); /* 0.8 ms */
vppif_reg32_out(REG_CEC_RD_LOGIC1_L_SET1, 205 * CEC_CLOCK); /* 2.05 ms*/
vppif_reg32_out(REG_CEC_RD_LOGIC1_R_SET1, 275 * CEC_CLOCK); /* 2.75 ms*/
vppif_reg32_out(REG_CEC_RD_L_SET0_ERROR, 182 * CEC_CLOCK); /* 1.82 ms */
vppif_reg32_out(REG_CEC_RD_R_SET1_ERROR, 238 * CEC_CLOCK); /* 2.38 ms */
vppif_reg32_out(REG_CEC_RD_L_ERROR, 287 * CEC_CLOCK); /* 2.87 ms */
vppif_reg32_out(REG_CEC_RX_SAMPLE_L_RANGE, 85 * CEC_CLOCK); /* 0.85 ms*/
vppif_reg32_out(REG_CEC_RX_SAMPLE_R_RANGE, 125 * CEC_CLOCK); /*1.25 ms*/
vppif_reg32_out(REG_CEC_WR_SET0_ERROR, 225 * CEC_CLOCK); /* 2.25 ms */
vppif_reg32_out(REG_CEC_WR_SET1_ERROR, 225 * CEC_CLOCK); /* 2.25 ms ?*/
}
void govm_set_pip_fb_addr(unsigned int y_addr,unsigned int c_addr)
{
DBGMSG("y_addr:0x%08x, c_addr:0x%08x\n",y_addr,c_addr);
vppif_reg32_out(REG_GOVM_PIP_Y_ADDR,y_addr);
vppif_reg32_out(REG_GOVM_PIP_C_ADDR,c_addr);
}
void govm_set_blanking(U32 color)
{
vppif_reg32_out(REG_GOVM_BNK,color);
}
void scl_set_V_scale_ptr(unsigned int init_val,unsigned int ret_val)
{
unsigned int reg;
reg = ((init_val) << 16) + (ret_val);
vppif_reg32_out(REG_SCL_VPTR,reg);
/* init V scale registers */
vppif_reg32_out(REG_SCL_VSCL_TB0,0x1);
vppif_reg32_out(REG_SCL_VSCL_TB1,0x0);
vppif_reg32_out(REG_SCL_VRES_TB,0x0);
vppif_reg32_out(REG_SCL_VDIV_TB0,0x0);
vppif_reg32_out(REG_SCL_VDIV_TB1,0x0);
vppif_reg32_out(REG_SCL_VDIV_TB2,0x0);
vppif_reg32_out(REG_SCL_VDIV_TB3,0x0);
vppif_reg32_out(REG_SCL_VDIV_TB4,0x0);
vppif_reg32_out(REG_SCL_VDIV_TB5,0x0);
vppif_reg32_out(REG_SCL_VDIV_TB6,0x0);
vppif_reg32_out(REG_SCL_VDIV_TB7,0x0);
vppif_reg32_out(REG_SCL_VDIV_TB8,0x0);
vppif_reg32_out(REG_SCL_VDIV_TB9,0x0);
vppif_reg32_out(REG_SCL_VDIV_TB10,0x0);
vppif_reg32_out(REG_SCL_VDIV_TB11,0x0);
vppif_reg32_out(REG_SCL_VDIV_TB12,0x0);
vppif_reg32_out(REG_SCL_VDIV_TB13,0x0);
vppif_reg32_out(REG_SCL_VDIV_TB14,0x0);
vppif_reg32_out(REG_SCL_VDIV_TB15,0x0);
}
void scl_set_H_scale_ptr(unsigned int init_val,unsigned int ret_val)
{
unsigned int reg;
reg = ((init_val) << 16) + (ret_val);
vppif_reg32_out(REG_SCL_HPTR,reg);
/* init V scale registers */
vppif_reg32_out(REG_SCL_HSCL_TB0,0x1);
vppif_reg32_out(REG_SCL_HSCL_TB1,0x0);
vppif_reg32_out(REG_SCL_HRES_TB,0x0);
vppif_reg32_out(REG_SCL_HDIV_TB0,0x0);
vppif_reg32_out(REG_SCL_HDIV_TB1,0x0);
vppif_reg32_out(REG_SCL_HDIV_TB2,0x0);
vppif_reg32_out(REG_SCL_HDIV_TB3,0x0);
vppif_reg32_out(REG_SCL_HDIV_TB4,0x0);
vppif_reg32_out(REG_SCL_HDIV_TB5,0x0);
vppif_reg32_out(REG_SCL_HDIV_TB6,0x0);
vppif_reg32_out(REG_SCL_HDIV_TB7,0x0);
vppif_reg32_out(REG_SCL_HDIV_TB8,0x0);
vppif_reg32_out(REG_SCL_HDIV_TB9,0x0);
vppif_reg32_out(REG_SCL_HDIV_TB10,0x0);
vppif_reg32_out(REG_SCL_HDIV_TB11,0x0);
vppif_reg32_out(REG_SCL_HDIV_TB12,0x0);
vppif_reg32_out(REG_SCL_HDIV_TB13,0x0);
vppif_reg32_out(REG_SCL_HDIV_TB14,0x0);
vppif_reg32_out(REG_SCL_HDIV_TB15,0x0);
vppif_reg32_write(SCL_BILINEAR_H,0);
}
