void vrc4173_select_function(int func)
{
u16 val;
if (vrc4173_initialized) {
val = vrc4173_inw(VRC4173_SELECTREG);
switch(func) {
case PS2CH1_SELECT:
val |= 0x0004;
break;
case PS2CH2_SELECT:
val |= 0x0002;
break;
case TOUCHPANEL_SELECT:
val &= 0x0007;
break;
case KIU8_SELECT:
val &= 0x000e;
break;
case KIU10_SELECT:
val &= 0x000c;
break;
case KIU12_SELECT:
val &= 0x0008;
break;
case GPIO_SELECT:
val |= 0x0008;
break;
}
vrc4173_outw(val, VRC4173_SELECTREG);
}
}
void vrc4173_select_function(int func)
{
if (vrc4173_initialized) {
spin_lock_irq(&vrc4173_giu_lock);
switch(func) {
case PS2CH1_SELECT:
vrc4173_selectreg |= 0x0004;
break;
case PS2CH2_SELECT:
vrc4173_selectreg |= 0x0002;
break;
case TOUCHPANEL_SELECT:
vrc4173_selectreg &= 0x0007;
break;
case KIU8_SELECT:
vrc4173_selectreg &= 0x000e;
break;
case KIU10_SELECT:
vrc4173_selectreg &= 0x000c;
break;
case KIU12_SELECT:
vrc4173_selectreg &= 0x0008;
break;
case GPIO_SELECT:
vrc4173_selectreg |= 0x0008;
break;
}
vrc4173_outw(vrc4173_selectreg, VRC4173_SELECTREG);
spin_unlock_irq(&vrc4173_giu_lock);
}
}
void vrc4173_clock_supply(u16 mask)
{
if (vrc4173_initialized) {
vrc4173_cmuclkmsk |= mask;
vrc4173_outw(vrc4173_cmuclkmsk, VRC4173_CMUCLKMSK);
}
}
void vrc4173_clock_mask(u16 mask)
{
if (vrc4173_initialized) {
vrc4173_cmuclkmsk &= ~mask;
vrc4173_outw(vrc4173_cmuclkmsk, VRC4173_CMUCLKMSK);
}
}
static inline void clear_cmusrst(uint16_t val)
{
uint16_t cmusrst;
cmusrst = vrc4173_inw(VRC4173_CMUSRST);
cmusrst &= ~val;
vrc4173_outw(cmusrst, VRC4173_CMUSRST);
}
static inline void set_cmusrst(uint16_t val)
{
uint16_t cmusrst;
cmusrst = vrc4173_inw(VRC4173_CMUSRST);
cmusrst |= val;
vrc4173_outw(cmusrst, VRC4173_CMUSRST);
}
static void disable_vrc4173_irq(unsigned int irq)
{
uint16_t val;
val = vrc4173_inw(VRC4173_MSYSINT1REG);
val &= ~((uint16_t)1 << (irq - VRC4173_IRQ_BASE));
vrc4173_outw(val, VRC4173_MSYSINT1REG);
}
static void enable_vrc4173_irq(unsigned int irq)
{
u16 val;
val = vrc4173_inw(VRC4173_MSYSINT1REG);
val |= (u16)1 << (irq - VRC4173_IRQ_BASE);
vrc4173_outw(val, VRC4173_MSYSINT1REG);
}
void vrc4173_disable_kiuint(uint16_t mask)
{
irq_desc_t *desc = irq_desc + VRC4173_KIU_IRQ;
unsigned long flags;
uint16_t val;
spin_lock_irqsave(&desc->lock, flags);
val = vrc4173_inw(VRC4173_MKIUINTREG);
val &= ~mask;
vrc4173_outw(val, VRC4173_MKIUINTREG);
spin_unlock_irqrestore(&desc->lock, flags);
}
static inline void vrc4173_icu_init(int cascade_irq)
{
int i;
if (cascade_irq < GIU_IRQ(0) || cascade_irq > GIU_IRQ(15))
return;
vrc4173_outw(0, VRC4173_MSYSINT1REG);
vr41xx_set_irq_trigger(GIU_IRQ_TO_PIN(cascade_irq), TRIGGER_LEVEL, SIGNAL_THROUGH);
vr41xx_set_irq_level(GIU_IRQ_TO_PIN(cascade_irq), LEVEL_LOW);
for (i = VRC4173_IRQ_BASE; i <= VRC4173_IRQ_LAST; i++)
irq_desc[i].handler = &vrc4173_irq_type;
}
void vrc4173_select_function(vrc4173_function_t function)
{
if (vrc4173_initialized) {
spin_lock_irq(&vrc4173_giu_lock);
switch(function) {
case PS2_CHANNEL1:
vrc4173_selectreg |= SEL2;
break;
case PS2_CHANNEL2:
vrc4173_selectreg |= SEL1;
break;
case TOUCHPANEL:
vrc4173_selectreg &= SEL2 | SEL1 | SEL0;
break;
case KEYBOARD_8SCANLINES:
vrc4173_selectreg &= SEL3 | SEL2 | SEL1;
break;
case KEYBOARD_10SCANLINES:
vrc4173_selectreg &= SEL3 | SEL2;
break;
case KEYBOARD_12SCANLINES:
vrc4173_selectreg &= SEL3;
break;
case GPIO_0_15PINS:
vrc4173_selectreg |= SEL0;
break;
case GPIO_16_20PINS:
vrc4173_selectreg |= SEL3;
break;
}
vrc4173_outw(vrc4173_selectreg, VRC4173_SELECTREG);
spin_unlock_irq(&vrc4173_giu_lock);
}
}
void vrc4173_supply_clock(unsigned int clock)
{
if (vrc4173_initialized) {
spin_lock_irq(&vrc4173_cmu_lock);
switch (clock) {
case VRC4173_PIU_CLOCK:
vrc4173_cmuclkmsk |= MSKPIU;
break;
case VRC4173_KIU_CLOCK:
vrc4173_cmuclkmsk |= MSKKIU;
break;
case VRC4173_AIU_CLOCK:
vrc4173_cmuclkmsk |= MSKAIU;
break;
case VRC4173_PS2_CH1_CLOCK:
vrc4173_cmuclkmsk |= MSKPS2CH1;
break;
case VRC4173_PS2_CH2_CLOCK:
vrc4173_cmuclkmsk |= MSKPS2CH2;
break;
case VRC4173_USBU_PCI_CLOCK:
set_cmusrst(USBRST);
vrc4173_cmuclkmsk |= MSKUSB;
break;
case VRC4173_CARDU1_PCI_CLOCK:
set_cmusrst(CARD1RST);
vrc4173_cmuclkmsk |= MSKCARD1;
break;
case VRC4173_CARDU2_PCI_CLOCK:
set_cmusrst(CARD2RST);
vrc4173_cmuclkmsk |= MSKCARD2;
break;
case VRC4173_AC97U_PCI_CLOCK:
set_cmusrst(AC97RST);
vrc4173_cmuclkmsk |= MSKAC97;
break;
case VRC4173_USBU_48MHz_CLOCK:
set_cmusrst(USBRST);
vrc4173_cmuclkmsk |= MSK48MUSB;
break;
case VRC4173_EXT_48MHz_CLOCK:
if (vrc4173_cmuclkmsk & MSK48MOSC)
vrc4173_cmuclkmsk |= MSK48MPIN;
else
printk(KERN_WARNING
"vrc4173_supply_clock: "
"Please supply VRC4173_48MHz_CLOCK first "
"rather than VRC4173_EXT_48MHz_CLOCK.\n");
break;
case VRC4173_48MHz_CLOCK:
vrc4173_cmuclkmsk |= MSK48MOSC;
break;
default:
printk(KERN_WARNING
"vrc4173_supply_clock: Invalid CLOCK value %u\n", clock);
break;
}
vrc4173_outw(vrc4173_cmuclkmsk, VRC4173_CMUCLKMSK);
switch (clock) {
case VRC4173_USBU_PCI_CLOCK:
case VRC4173_USBU_48MHz_CLOCK:
clear_cmusrst(USBRST);
break;
case VRC4173_CARDU1_PCI_CLOCK:
clear_cmusrst(CARD1RST);
break;
case VRC4173_CARDU2_PCI_CLOCK:
clear_cmusrst(CARD2RST);
break;
case VRC4173_AC97U_PCI_CLOCK:
clear_cmusrst(AC97RST);
break;
default:
break;
}
spin_unlock_irq(&vrc4173_cmu_lock);
}
}
void vrc4173_mask_clock(vrc4173_clock_t clock)
{
if (vrc4173_initialized) {
spin_lock_irq(&vrc4173_cmu_lock);
switch (clock) {
case VRC4173_PIU_CLOCK:
vrc4173_cmuclkmsk &= ~MSKPIU;
break;
case VRC4173_KIU_CLOCK:
vrc4173_cmuclkmsk &= ~MSKKIU;
break;
case VRC4173_AIU_CLOCK:
vrc4173_cmuclkmsk &= ~MSKAIU;
break;
case VRC4173_PS2_CH1_CLOCK:
vrc4173_cmuclkmsk &= ~MSKPS2CH1;
break;
case VRC4173_PS2_CH2_CLOCK:
vrc4173_cmuclkmsk &= ~MSKPS2CH2;
break;
case VRC4173_USBU_PCI_CLOCK:
set_cmusrst(USBRST);
vrc4173_cmuclkmsk &= ~MSKUSB;
break;
case VRC4173_CARDU1_PCI_CLOCK:
set_cmusrst(CARD1RST);
vrc4173_cmuclkmsk &= ~MSKCARD1;
break;
case VRC4173_CARDU2_PCI_CLOCK:
set_cmusrst(CARD2RST);
vrc4173_cmuclkmsk &= ~MSKCARD2;
break;
case VRC4173_AC97U_PCI_CLOCK:
set_cmusrst(AC97RST);
vrc4173_cmuclkmsk &= ~MSKAC97;
break;
case VRC4173_USBU_48MHz_CLOCK:
set_cmusrst(USBRST);
vrc4173_cmuclkmsk &= ~MSK48MUSB;
break;
case VRC4173_EXT_48MHz_CLOCK:
vrc4173_cmuclkmsk &= ~MSK48MPIN;
break;
case VRC4173_48MHz_CLOCK:
vrc4173_cmuclkmsk &= ~MSK48MOSC;
break;
default:
printk(KERN_WARNING "vrc4173_mask_clock: Invalid CLOCK value %u\n", clock);
break;
}
vrc4173_outw(vrc4173_cmuclkmsk, VRC4173_CMUCLKMSK);
switch (clock) {
case VRC4173_USBU_PCI_CLOCK:
case VRC4173_USBU_48MHz_CLOCK:
clear_cmusrst(USBRST);
break;
case VRC4173_CARDU1_PCI_CLOCK:
clear_cmusrst(CARD1RST);
break;
case VRC4173_CARDU2_PCI_CLOCK:
clear_cmusrst(CARD2RST);
break;
case VRC4173_AC97U_PCI_CLOCK:
clear_cmusrst(AC97RST);
break;
default:
break;
}
spin_unlock_irq(&vrc4173_cmu_lock);
}
}
