static void rpf_vdev_queue(struct vsp1_video *video, struct vsp1_video_buffer *buf) { struct vsp1_rwpf *rpf = container_of(video, struct vsp1_rwpf, video); vsp1_rpf_write(rpf, VI6_RPF_SRCM_ADDR_Y, buf->addr[0] + rpf->offsets[0]); if (buf->buf.num_planes > 1) vsp1_rpf_write(rpf, VI6_RPF_SRCM_ADDR_C0, buf->addr[1] + rpf->offsets[1]); if (buf->buf.num_planes > 2) vsp1_rpf_write(rpf, VI6_RPF_SRCM_ADDR_C1, buf->addr[2] + rpf->offsets[1]); }
static void rpf_configure_frame(struct vsp1_entity *entity, struct vsp1_pipeline *pipe, struct vsp1_dl_list *dl, struct vsp1_dl_body *dlb) { struct vsp1_rwpf *rpf = to_rwpf(&entity->subdev); vsp1_rpf_write(rpf, dlb, VI6_RPF_VRTCOL_SET, rpf->alpha << VI6_RPF_VRTCOL_SET_LAYA_SHIFT); vsp1_rpf_write(rpf, dlb, VI6_RPF_MULT_ALPHA, rpf->mult_alpha | (rpf->alpha << VI6_RPF_MULT_ALPHA_RATIO_SHIFT)); vsp1_pipeline_propagate_alpha(pipe, dlb, rpf->alpha); }
static void rpf_set_memory(struct vsp1_rwpf *rpf, struct vsp1_rwpf_memory *mem) { unsigned int i; for (i = 0; i < 3; ++i) rpf->buf_addr[i] = mem->addr[i]; if (!vsp1_entity_is_streaming(&rpf->entity)) return; vsp1_rpf_write(rpf, VI6_RPF_SRCM_ADDR_Y, mem->addr[0] + rpf->offsets[0]); if (mem->num_planes > 1) vsp1_rpf_write(rpf, VI6_RPF_SRCM_ADDR_C0, mem->addr[1] + rpf->offsets[1]); if (mem->num_planes > 2) vsp1_rpf_write(rpf, VI6_RPF_SRCM_ADDR_C1, mem->addr[2] + rpf->offsets[1]); }
static int rpf_s_ctrl(struct v4l2_ctrl *ctrl) { struct vsp1_rwpf *rpf = container_of(ctrl->handler, struct vsp1_rwpf, ctrls); struct vsp1_pipeline *pipe; if (!vsp1_entity_is_streaming(&rpf->entity)) return 0; switch (ctrl->id) { case V4L2_CID_ALPHA_COMPONENT: vsp1_rpf_write(rpf, VI6_RPF_VRTCOL_SET, ctrl->val << VI6_RPF_VRTCOL_SET_LAYA_SHIFT); pipe = to_vsp1_pipeline(&rpf->entity.subdev.entity); vsp1_pipeline_propagate_alpha(pipe, &rpf->entity, ctrl->val); break; } return 0; }
static int rpf_s_stream(struct v4l2_subdev *subdev, int enable) { struct vsp1_pipeline *pipe = to_vsp1_pipeline(&subdev->entity); struct vsp1_rwpf *rpf = to_rwpf(subdev); struct vsp1_device *vsp1 = rpf->entity.vsp1; const struct vsp1_format_info *fmtinfo = rpf->fmtinfo; const struct v4l2_pix_format_mplane *format = &rpf->format; const struct v4l2_rect *crop = &rpf->crop; u32 pstride; u32 infmt; int ret; ret = vsp1_entity_set_streaming(&rpf->entity, enable); if (ret < 0) return ret; if (!enable) return 0; /* Source size, stride and crop offsets. * * The crop offsets correspond to the location of the crop rectangle top * left corner in the plane buffer. Only two offsets are needed, as * planes 2 and 3 always have identical strides. */ vsp1_rpf_write(rpf, VI6_RPF_SRC_BSIZE, (crop->width << VI6_RPF_SRC_BSIZE_BHSIZE_SHIFT) | (crop->height << VI6_RPF_SRC_BSIZE_BVSIZE_SHIFT)); vsp1_rpf_write(rpf, VI6_RPF_SRC_ESIZE, (crop->width << VI6_RPF_SRC_ESIZE_EHSIZE_SHIFT) | (crop->height << VI6_RPF_SRC_ESIZE_EVSIZE_SHIFT)); rpf->offsets[0] = crop->top * format->plane_fmt[0].bytesperline + crop->left * fmtinfo->bpp[0] / 8; pstride = format->plane_fmt[0].bytesperline << VI6_RPF_SRCM_PSTRIDE_Y_SHIFT; vsp1_rpf_write(rpf, VI6_RPF_SRCM_ADDR_Y, rpf->buf_addr[0] + rpf->offsets[0]); if (format->num_planes > 1) { rpf->offsets[1] = crop->top * format->plane_fmt[1].bytesperline + crop->left * fmtinfo->bpp[1] / 8; pstride |= format->plane_fmt[1].bytesperline << VI6_RPF_SRCM_PSTRIDE_C_SHIFT; vsp1_rpf_write(rpf, VI6_RPF_SRCM_ADDR_C0, rpf->buf_addr[1] + rpf->offsets[1]); if (format->num_planes > 2) vsp1_rpf_write(rpf, VI6_RPF_SRCM_ADDR_C1, rpf->buf_addr[2] + rpf->offsets[1]); } vsp1_rpf_write(rpf, VI6_RPF_SRCM_PSTRIDE, pstride); /* Format */ infmt = VI6_RPF_INFMT_CIPM | (fmtinfo->hwfmt << VI6_RPF_INFMT_RDFMT_SHIFT); if (fmtinfo->swap_yc) infmt |= VI6_RPF_INFMT_SPYCS; if (fmtinfo->swap_uv) infmt |= VI6_RPF_INFMT_SPUVS; if (rpf->entity.formats[RWPF_PAD_SINK].code != rpf->entity.formats[RWPF_PAD_SOURCE].code) infmt |= VI6_RPF_INFMT_CSC; vsp1_rpf_write(rpf, VI6_RPF_INFMT, infmt); vsp1_rpf_write(rpf, VI6_RPF_DSWAP, fmtinfo->swap); /* Output location */ vsp1_rpf_write(rpf, VI6_RPF_LOC, (rpf->location.left << VI6_RPF_LOC_HCOORD_SHIFT) | (rpf->location.top << VI6_RPF_LOC_VCOORD_SHIFT)); /* Use the alpha channel (extended to 8 bits) when available or an * alpha value set through the V4L2_CID_ALPHA_COMPONENT control * otherwise. Disable color keying. */ vsp1_rpf_write(rpf, VI6_RPF_ALPH_SEL, VI6_RPF_ALPH_SEL_AEXT_EXT | (fmtinfo->alpha ? VI6_RPF_ALPH_SEL_ASEL_PACKED : VI6_RPF_ALPH_SEL_ASEL_FIXED)); if (vsp1->info->uapi) mutex_lock(rpf->ctrls.lock); vsp1_rpf_write(rpf, VI6_RPF_VRTCOL_SET, rpf->alpha->cur.val << VI6_RPF_VRTCOL_SET_LAYA_SHIFT); vsp1_pipeline_propagate_alpha(pipe, &rpf->entity, rpf->alpha->cur.val); if (vsp1->info->uapi) mutex_unlock(rpf->ctrls.lock); vsp1_rpf_write(rpf, VI6_RPF_MSK_CTRL, 0); vsp1_rpf_write(rpf, VI6_RPF_CKEY_CTRL, 0); return 0; }
static int rpf_s_stream(struct v4l2_subdev *subdev, int enable) { struct vsp1_rwpf *rpf = to_rwpf(subdev); const struct vsp1_format_info *fmtinfo = rpf->video.fmtinfo; const struct v4l2_pix_format_mplane *format = &rpf->video.format; const struct v4l2_rect *crop = &rpf->crop; u32 pstride; u32 infmt; if (!enable) return 0; /* Source size, stride and crop offsets. * * The crop offsets correspond to the location of the crop rectangle top * left corner in the plane buffer. Only two offsets are needed, as * planes 2 and 3 always have identical strides. */ vsp1_rpf_write(rpf, VI6_RPF_SRC_BSIZE, (crop->width << VI6_RPF_SRC_BSIZE_BHSIZE_SHIFT) | (crop->height << VI6_RPF_SRC_BSIZE_BVSIZE_SHIFT)); vsp1_rpf_write(rpf, VI6_RPF_SRC_ESIZE, (crop->width << VI6_RPF_SRC_ESIZE_EHSIZE_SHIFT) | (crop->height << VI6_RPF_SRC_ESIZE_EVSIZE_SHIFT)); rpf->offsets[0] = crop->top * format->plane_fmt[0].bytesperline + crop->left * fmtinfo->bpp[0] / 8; pstride = format->plane_fmt[0].bytesperline << VI6_RPF_SRCM_PSTRIDE_Y_SHIFT; if (format->num_planes > 1) { rpf->offsets[1] = crop->top * format->plane_fmt[1].bytesperline + crop->left * fmtinfo->bpp[1] / 8; pstride |= format->plane_fmt[1].bytesperline << VI6_RPF_SRCM_PSTRIDE_C_SHIFT; } vsp1_rpf_write(rpf, VI6_RPF_SRCM_PSTRIDE, pstride); /* Format */ infmt = VI6_RPF_INFMT_CIPM | (fmtinfo->hwfmt << VI6_RPF_INFMT_RDFMT_SHIFT); if (fmtinfo->swap_yc) infmt |= VI6_RPF_INFMT_SPYCS; if (fmtinfo->swap_uv) infmt |= VI6_RPF_INFMT_SPUVS; if (rpf->entity.formats[RWPF_PAD_SINK].code != rpf->entity.formats[RWPF_PAD_SOURCE].code) infmt |= VI6_RPF_INFMT_CSC; vsp1_rpf_write(rpf, VI6_RPF_INFMT, infmt); vsp1_rpf_write(rpf, VI6_RPF_DSWAP, fmtinfo->swap); /* Output location */ vsp1_rpf_write(rpf, VI6_RPF_LOC, (rpf->location.left << VI6_RPF_LOC_HCOORD_SHIFT) | (rpf->location.top << VI6_RPF_LOC_VCOORD_SHIFT)); /* Disable alpha, mask and color key. Set the alpha channel to a fixed * value of 255. */ vsp1_rpf_write(rpf, VI6_RPF_ALPH_SEL, VI6_RPF_ALPH_SEL_ASEL_FIXED); vsp1_rpf_write(rpf, VI6_RPF_VRTCOL_SET, 255 << VI6_RPF_VRTCOL_SET_LAYA_SHIFT); vsp1_rpf_write(rpf, VI6_RPF_MSK_CTRL, 0); vsp1_rpf_write(rpf, VI6_RPF_CKEY_CTRL, 0); return 0; }
static void rpf_configure_stream(struct vsp1_entity *entity, struct vsp1_pipeline *pipe, struct vsp1_dl_body *dlb) { struct vsp1_rwpf *rpf = to_rwpf(&entity->subdev); const struct vsp1_format_info *fmtinfo = rpf->fmtinfo; const struct v4l2_pix_format_mplane *format = &rpf->format; const struct v4l2_mbus_framefmt *source_format; const struct v4l2_mbus_framefmt *sink_format; unsigned int left = 0; unsigned int top = 0; u32 pstride; u32 infmt; /* Stride */ pstride = format->plane_fmt[0].bytesperline << VI6_RPF_SRCM_PSTRIDE_Y_SHIFT; if (format->num_planes > 1) pstride |= format->plane_fmt[1].bytesperline << VI6_RPF_SRCM_PSTRIDE_C_SHIFT; /* * pstride has both STRIDE_Y and STRIDE_C, but multiplying the whole * of pstride by 2 is conveniently OK here as we are multiplying both * values. */ if (pipe->interlaced) pstride *= 2; vsp1_rpf_write(rpf, dlb, VI6_RPF_SRCM_PSTRIDE, pstride); /* Format */ sink_format = vsp1_entity_get_pad_format(&rpf->entity, rpf->entity.config, RWPF_PAD_SINK); source_format = vsp1_entity_get_pad_format(&rpf->entity, rpf->entity.config, RWPF_PAD_SOURCE); infmt = VI6_RPF_INFMT_CIPM | (fmtinfo->hwfmt << VI6_RPF_INFMT_RDFMT_SHIFT); if (fmtinfo->swap_yc) infmt |= VI6_RPF_INFMT_SPYCS; if (fmtinfo->swap_uv) infmt |= VI6_RPF_INFMT_SPUVS; if (sink_format->code != source_format->code) infmt |= VI6_RPF_INFMT_CSC; vsp1_rpf_write(rpf, dlb, VI6_RPF_INFMT, infmt); vsp1_rpf_write(rpf, dlb, VI6_RPF_DSWAP, fmtinfo->swap); /* Output location. */ if (pipe->brx) { const struct v4l2_rect *compose; compose = vsp1_entity_get_pad_selection(pipe->brx, pipe->brx->config, rpf->brx_input, V4L2_SEL_TGT_COMPOSE); left = compose->left; top = compose->top; } if (pipe->interlaced) top /= 2; vsp1_rpf_write(rpf, dlb, VI6_RPF_LOC, (left << VI6_RPF_LOC_HCOORD_SHIFT) | (top << VI6_RPF_LOC_VCOORD_SHIFT)); /* * On Gen2 use the alpha channel (extended to 8 bits) when available or * a fixed alpha value set through the V4L2_CID_ALPHA_COMPONENT control * otherwise. * * The Gen3 RPF has extended alpha capability and can both multiply the * alpha channel by a fixed global alpha value, and multiply the pixel * components to convert the input to premultiplied alpha. * * As alpha premultiplication is available in the BRx for both Gen2 and * Gen3 we handle it there and use the Gen3 alpha multiplier for global * alpha multiplication only. This however prevents conversion to * premultiplied alpha if no BRx is present in the pipeline. If that use * case turns out to be useful we will revisit the implementation (for * Gen3 only). * * We enable alpha multiplication on Gen3 using the fixed alpha value * set through the V4L2_CID_ALPHA_COMPONENT control when the input * contains an alpha channel. On Gen2 the global alpha is ignored in * that case. * * In all cases, disable color keying. */ vsp1_rpf_write(rpf, dlb, VI6_RPF_ALPH_SEL, VI6_RPF_ALPH_SEL_AEXT_EXT | (fmtinfo->alpha ? VI6_RPF_ALPH_SEL_ASEL_PACKED : VI6_RPF_ALPH_SEL_ASEL_FIXED)); if (entity->vsp1->info->gen == 3) { u32 mult; if (fmtinfo->alpha) { /* * When the input contains an alpha channel enable the * alpha multiplier. If the input is premultiplied we * need to multiply both the alpha channel and the pixel * components by the global alpha value to keep them * premultiplied. Otherwise multiply the alpha channel * only. */ bool premultiplied = format->flags & V4L2_PIX_FMT_FLAG_PREMUL_ALPHA; mult = VI6_RPF_MULT_ALPHA_A_MMD_RATIO | (premultiplied ? VI6_RPF_MULT_ALPHA_P_MMD_RATIO : VI6_RPF_MULT_ALPHA_P_MMD_NONE); } else { /* * When the input doesn't contain an alpha channel the * global alpha value is applied in the unpacking unit, * the alpha multiplier isn't needed and must be * disabled. */ mult = VI6_RPF_MULT_ALPHA_A_MMD_NONE | VI6_RPF_MULT_ALPHA_P_MMD_NONE; } rpf->mult_alpha = mult; } vsp1_rpf_write(rpf, dlb, VI6_RPF_MSK_CTRL, 0); vsp1_rpf_write(rpf, dlb, VI6_RPF_CKEY_CTRL, 0); }
static void rpf_configure_partition(struct vsp1_entity *entity, struct vsp1_pipeline *pipe, struct vsp1_dl_list *dl, struct vsp1_dl_body *dlb) { struct vsp1_rwpf *rpf = to_rwpf(&entity->subdev); struct vsp1_rwpf_memory mem = rpf->mem; struct vsp1_device *vsp1 = rpf->entity.vsp1; const struct vsp1_format_info *fmtinfo = rpf->fmtinfo; const struct v4l2_pix_format_mplane *format = &rpf->format; struct v4l2_rect crop; /* * Source size and crop offsets. * * The crop offsets correspond to the location of the crop * rectangle top left corner in the plane buffer. Only two * offsets are needed, as planes 2 and 3 always have identical * strides. */ crop = *vsp1_rwpf_get_crop(rpf, rpf->entity.config); /* * Partition Algorithm Control * * The partition algorithm can split this frame into multiple * slices. We must scale our partition window based on the pipe * configuration to match the destination partition window. * To achieve this, we adjust our crop to provide a 'sub-crop' * matching the expected partition window. Only 'left' and * 'width' need to be adjusted. */ if (pipe->partitions > 1) { crop.width = pipe->partition->rpf.width; crop.left += pipe->partition->rpf.left; } if (pipe->interlaced) { crop.height = round_down(crop.height / 2, fmtinfo->vsub); crop.top = round_down(crop.top / 2, fmtinfo->vsub); } vsp1_rpf_write(rpf, dlb, VI6_RPF_SRC_BSIZE, (crop.width << VI6_RPF_SRC_BSIZE_BHSIZE_SHIFT) | (crop.height << VI6_RPF_SRC_BSIZE_BVSIZE_SHIFT)); vsp1_rpf_write(rpf, dlb, VI6_RPF_SRC_ESIZE, (crop.width << VI6_RPF_SRC_ESIZE_EHSIZE_SHIFT) | (crop.height << VI6_RPF_SRC_ESIZE_EVSIZE_SHIFT)); mem.addr[0] += crop.top * format->plane_fmt[0].bytesperline + crop.left * fmtinfo->bpp[0] / 8; if (format->num_planes > 1) { unsigned int offset; offset = crop.top * format->plane_fmt[1].bytesperline + crop.left / fmtinfo->hsub * fmtinfo->bpp[1] / 8; mem.addr[1] += offset; mem.addr[2] += offset; } /* * On Gen3 hardware the SPUVS bit has no effect on 3-planar * formats. Swap the U and V planes manually in that case. */ if (vsp1->info->gen == 3 && format->num_planes == 3 && fmtinfo->swap_uv) swap(mem.addr[1], mem.addr[2]); /* * Interlaced pipelines will use the extended pre-cmd to process * SRCM_ADDR_{Y,C0,C1}. */ if (pipe->interlaced) { vsp1_rpf_configure_autofld(rpf, dl); } else { vsp1_rpf_write(rpf, dlb, VI6_RPF_SRCM_ADDR_Y, mem.addr[0]); vsp1_rpf_write(rpf, dlb, VI6_RPF_SRCM_ADDR_C0, mem.addr[1]); vsp1_rpf_write(rpf, dlb, VI6_RPF_SRCM_ADDR_C1, mem.addr[2]); } }