void hardWareInterFaceInit (void)
{
hwMemLibInit(); hwMemPoolCreate(&hwMemPool[0], HWMEM_POOL_SIZE); /* Pre-Kernel Memory Allocation */
hardWareInterFaceBusInit(); /* vxBus subsystem */
vxbInit(); /* vxBus Library Activation */
vxbTimerLibInit(); /* vxBus Timer Support */
}
void hardWareInterFaceBusInit (void)
{
/* initialize bus subsystem */
vxbLibInit();
#ifdef INCLUDE_QUICC_ENGINE_UTILS
quiccEngineRegister();
#endif
#ifdef INCLUDE_DMA_SYS
vxbDmaBufInit();
vxbDmaLibInit();
#endif
#ifdef INCLUDE_NON_VOLATILE_RAM
vxbNonVolLibInit();
#endif /* INCLUDE_NON_VOLATILE_RAM */
#ifdef INCLUDE_VXBUS_SM_SUPPORT
smEndRegister();
#endif
/*
* initialize processor local bus
* PLB: always included
*/
plbRegister();
/* bus registration */
#ifdef DRV_PCIBUS_M83XX
m83xxPciRegister (); /* M83xx PCI host controller */
#endif /* DRV_PCIBUS_M83XX */
#ifdef DRV_PCIBUS_M85XX
m85xxPciRegister (); /* M85xx PCI host controller */
#endif /* DRV_PCIBUS_M85XX */
#ifdef INCLUDE_MII_BUS
miiBusRegister();
#endif
#ifdef INCLUDE_PCI_BUS
pciRegister();
#endif /* INCLUDE_PCI_BUS */
#ifdef INCLUDE_PPC440GX_PCI
vxbPpc440gxPciRegister(); /* PowerPC 440GX PCI host controller */
#endif /* INCLUDE_PPC440GX_PCI */
#ifdef INCLUDE_RAPIDIO_BUS
rapidIoRegister();
#endif /* INCLUDE_RAPIDIO_BUS */
#ifdef DRV_PCI_SH77XX
sh77xxPciRegister();
#endif /* DRV_PCI_SH77XX */
/* driver registration */
#ifdef INCLUDE_AM79C97X_VXB_END
lnPciRegister();
#endif
#ifdef INCLUDE_BCM52XXPHY
bmtPhyRegister();
#endif
#ifdef INCLUDE_BCM54XXPHY
brgPhyRegister();
#endif
#ifdef INCLUDE_VXB_CPM
cpmRegister();
#endif
#ifdef INCLUDE_DM9161PHY
dmPhyRegister();
#endif
#ifdef INCLUDE_FCC_VXB_END
fccRegister();
#endif
#ifdef INCLUDE_FEC_VXB_END
fecRegister();
#endif /* INCLUDE_FEC_VXB_END */
#ifdef INCLUDE_FEI8255X_VXB_END
feiRegister();
#endif
#ifdef INCLUDE_GT64120A_PCI
g64120aPciRegister ();
#endif /* INCLUDE_GT64120A_PCI */
#ifdef INCLUDE_GT64120A_MF
g64120aMfRegister ();
#endif /* INCLUDE_GT64120A_MF */
#ifdef INCLUDE_GEI825XX_VXB_END
geiRegister();
#endif
#ifdef INCLUDE_GEI_HEND
geiHEndRegister();
#endif /* INCLUDE_GEI_HEND */
#ifdef INCLUDE_GEITBIPHY
geiTbiPhyRegister();
#endif
#ifdef INCLUDE_GENERICPHY
genPhyRegister();
#endif
#ifdef INCLUDE_GENERICTBIPHY
genTbiRegister();
#endif
#ifdef DRV_PCIBUS_IXP4XX
ixPciRegister (); /* IXP4xx PCI host controller */
#endif /* DRV_PCIBUS_IXP4XX */
#ifdef INCLUDE_LXT972PHY
lxtPhyRegister();
#endif
#ifdef DRV_RESOURCE_M85XXCCSR
m85xxCCSRRegister();
#endif /* DRV_RESOURCE_M85XXCCSR */
#ifdef INCLUDE_M85XX_CPU
m85xxCpuRegister();
#endif /* INCLUDE_M85XX_CPU */
#ifdef INCLUDE_M85XX_RAPIDIO
m85xxRioRegister();
#endif /* INCLUDE_M85XX_RAPIDIO */
#ifdef INCLUDE_MCF5475_PCI
mcf5475PciRegister();
#endif /* INCLUDE_MCF5475_PCI */
#ifdef INCLUDE_MDIO
mdioRegister();
#endif /* mdioRegister */
#ifdef INCLUDE_MOT_ETSEC_HEND
motEtsecHEndRegister();
#endif /* INCLUDE_MOT_ETSEC_HEND */
#ifdef INCLUDE_MOT_FEC_HEND
motFecHEndRegister();
#endif /* INCLUDE_MOT_FEC_HEND */
#ifdef INCLUDE_MOT_TSEC_HEND
motTsecHEndRegister();
#endif /* INCLUDE_MOT_TSEC_HEND */
#ifdef INCLUDE_MV88E1113PHY
mvfPhyRegister();
#endif
#ifdef INCLUDE_MV88E1X11PHY
mvPhyRegister();
#endif
#ifdef INCLUDE_MVYUKONII_VXB_END
ynRegister();
#endif
#ifdef INCLUDE_NE2000_VXB_END
eneRegister();
#endif
#ifdef INCLUDE_NS83902_VXB_END
nicRegister();
#endif /* INCLUDE_NS83902_VXB_END */
#ifdef INCLUDE_PENTIUM_PCI
pentiumPciRegister(); /* pcPentium PCI host controller */
#endif /* INCLUDE_PENTIUM_PCI */
#ifdef INCLUDE_PPC440GP_PCI
ppc440gpPciRegister(); /* PowerPC 440GP PCI host controller */
#endif /* INCLUDE_PPC440GP_PCI */
#ifdef INCLUDE_QE_FCC_HEND
qeFccHEndRegister();
#endif /* INCLUDE_QE_FCC_HEND */
#ifdef INCLUDE_RTL8139_VXB_END
rtlRegister();
#endif
#ifdef INCLUDE_RTL8169PHY
rtgPhyRegister();
#endif
#ifdef INCLUDE_RTL8169_VXB_END
rtgRegister();
#endif
#ifdef INCLUDE_RTL8201PHY
rtlPhyRegister();
#endif
#ifdef INCLUDE_SBE_VXB_END
sbeRegister();
#endif
#ifdef INCLUDE_SCC_VXB_END
sccRegister();
#endif /* INCLUDE_SCC_VXB_END */
#ifdef INCLUDE_TSEC_MDIO
tmRegister();
#endif /* mdioRegister */
#ifdef INCLUDE_TSEC_VXB_END
tsecRegister();
#endif /* INCLUDE_TSEC_VXB_END */
#ifdef INCLUDE_VSC82XXPHY
vigPhyRegister();
#endif
#ifdef DRV_TIMER_CN3XXX
vxbCn3xxxTimerDrvRegister ();
#endif
#ifdef DRV_SIO_COLDFIRE
coldFireSioRegister();
#endif
#ifdef DRV_EB_GIC
vxbEbGenIntrCtlRegister ();
#endif /* DRV_EB_GIC C*/
#ifdef INCLUDE_EMAC_VXB_NET
vxbEmacRegister();
#endif /* INCLUDE_EMAC_VXB_END */
#ifdef DRV_INTCTLR_EPIC
vxbEpicIntCtlrRegister();
#endif /* DRV_INTCTLR_EPIC */
#ifdef INCLUDE_ETSEC_VXB_END
etsecRegister();
#endif /* INCLUDE_ETSEC_VXB_END */
#ifdef DRV_NVRAM_FILE
vxbFileNvRamRegister();
#endif /* DRV_NVRAM_FILE */
#ifdef DRV_KBD_I8042
i8042vxbRegister ();
#endif /* DRV_KBD_I8042 */
#ifdef DRV_TIMER_I8253
vxbI8253TimerDrvRegister ();
#endif
#ifdef DRV_INTCTLR_I8259
vxbI8259IntCtlrRegister ();
#endif /* DRV_INTCTLR_I8259 */
#ifdef INCLUDE_IPIIX4_MF
vxbIPiix4MfRegister ();
#endif /* INCLUDE_PIIX4_MF */
#ifdef INCLUDE_VXB_IBM_MAL
vxbMalRegister();
#endif /* INCLUDE_VXB_IBM_MAL */
#ifdef INCLUDE_DRV_STORAGE_INTEL_ICH
vxbIntelIchStorageRegister ();
#endif
#ifdef INCLUDE_DRV_STORAGE_INTEL_ICH_SHOW
ichAtaShowInit ();
#endif
#ifdef DRV_TIMER_IA_TIMESTAMP
vxbIaTimestampDrvRegister ();
#endif
#ifdef DRV_INTCTLR_IOAPIC
vxbIoApicIntrDrvRegister ();
#endif /* DRV_INTCTLR_IOAPI C*/
#ifdef DRV_SIO_IXP400
ixp400SioRegister();
#endif /* DRV_SIO_IXP400 */
#ifdef DRV_TIMER_IXP400
ixp400TimerDrvRegister ();
#endif
#ifdef DRV_INTCTLR_LOAPIC
vxbLoApicIntrDrvRegister ();
#endif /* DRV_INTCTLR_LOAPIC */
#ifdef DRV_TIMER_LOAPIC
vxbLoApicTimerDrvRegister ();
#endif
#ifdef DRV_DMA_COLDFIRE
m548xDmaDrvRegister ();
#endif /* DRV_DMA_COLDFIRE */
#ifdef DRV_TIMER_COLDFIRE
m54x5TimerDrvRegister ();
#endif
#ifdef DRV_VGA_M6845
m6845vxbRegister ();
#endif /* DRV_VGA_M6845 */
#ifdef DRV_TIMER_M85XX
m85xxTimerDrvRegister ();
#endif /* DRV_TIMER_M85XX */
#ifdef DRV_TIMER_MC146818
vxbMc146818RtcDrvRegister ();
#endif /* DRV_TIMER_MC146818 */
#ifdef DRV_INTCTLR_MIPS_CAV
vxbMipsCavIntCtlrRegister ();
#endif /* DRV_INTCTLR_MIPS_CAV */
#ifdef DRV_INTCTLR_MIPS
vxbMipsIntCtlrRegister ();
#endif /* DRV_INTCTLR_MIPS */
#ifdef DRV_TIMER_MIPSR4K
vxbR4KTimerDrvRegister ();
#endif /* DRV_TIMER_MIPSR4K */
#ifdef DRV_INTCTLR_MIPS_SBE
vxbMipsSbIntCtlrRegister ();
#endif /* DRV_INTCTLR_MIPS_SBE */
#ifdef DRV_INTCTLR_MPAPIC
vxbMpApicDrvRegister ();
#endif /* DRV_INTCTLR_MPAPIC */
#ifdef INCLUDE_MSC01_PCI
vxbMsc01PciRegister ();
#endif
#ifdef DRV_SIO_NS16550
ns16550SioRegister();
#endif /* DRV_SIO_NS16550 */
#ifdef INCLUDE_OCTEON_MDIO
octeonMdioRegister();
#endif
#ifdef INCLUDE_OCTEON_RGMII_VXB_END
octRgmiiRegister();
#endif
#ifdef DRV_SIO_OCTEON
octeonSioRegister();
#endif /* DRV_SIO_OCTEON */
#ifdef DRV_TIMER_OPENPIC
openPicTimerDrvRegister ();
#endif
#ifdef DRV_TIMER_DEC_PPC
ppcDecTimerDrvRegister ();
#endif
#ifdef DRV_INTCTLR_PPC
ppcIntCtlrRegister();
#endif /* DRV_INTCTLR_PPC */
#ifdef DRV_TIMER_QUICC_PPC
quiccTimerDrvRegister ();
#endif
#ifdef DRV_SIO_PRIMECELL
vxbPrimeCellSioRegister();
#endif /* DRV_SIO_PRIMECELL */
#ifdef DRV_INTCTLR_QE
vxbQeIntCtlrRegister();
#endif /* DRV_INTCTLR_QE */
#ifdef DRV_INTCTLR_QUICC
vxbQuiccIntCtlrRegister();
#endif /* DRV_INTCTLR_QUICC */
#ifdef DRV_STORAGE_SI31XX
vxbSI31xxStorageRegister ();
#endif
#ifdef DRV_SIO_SB1
vxbSb1DuartSioRegister();
#endif /* DRV_SIO_SB1 */
#ifdef DRV_TIMER_SB1
vxbSb1TimerDrvRegister ();
#endif
#ifdef DRV_TIMER_SH7700
sh7700TimerDrvRegister ();
#endif
#ifdef DRV_SIO_SHSCIF
shScifSioRegister();
#endif /* DRV_SIO_SHSCIF */
#ifdef DRV_SUPERIO_SMCFDC37X
vxbSmcFdc37xRegister();
#endif /* DRV_SUPERIO_SMCFDC37X */
#ifdef INCLUDE_SMSCLAN9118_VXB_END
smeRegister();
#endif
#ifdef INCLUDE_EHCI
usbEhcdInstantiate();
#endif
#ifdef INCLUDE_EHCI_INIT
/* Register the Ehci with vxBus */
vxbUsbEhciRegister ();
#endif
#ifdef INCLUDE_OHCI
usbOhciInstantiate();
#endif
#ifdef INCLUDE_OHCI_INIT
/* Register the Ohci with vxBus */
vxbUsbOhciRegister ();
#endif
#ifdef INCLUDE_UHCI
usbUhcdInstantiate();
#endif
#ifdef INCLUDE_UHCI_INIT
/* Register the Uhci with vxBus */
vxbUsbUhciRegister ();
#endif
#ifdef DRV_INTCTLR_VXSIM
vxbVxSimIntCtlrRegister();
#endif /* DRV_INTCTLR_VXSIM */
/* probe devices and create instances */
vxbInit();
}
