int mc13783_write_regs(const unsigned char *regs, uint32_t *buffer,
int count)
{
int i;
for (i = 0; i < count; i++)
{
unsigned reg = regs[i];
if (reg >= MC13783_NUM_REGS)
return -1;
buffer[i] = (1 << 31) | (reg << 25) | (buffer[i] & 0xffffff);
}
mutex_lock(&mc13783_spi_mutex);
mc13783_transfer.txbuf = buffer;
mc13783_transfer.rxbuf = NULL;
mc13783_transfer.count = count;
i = -1;
if (spi_transfer(&mc13783_transfer) && wait_for_transfer_complete())
i = count - mc13783_transfer.count;
mutex_unlock(&mc13783_spi_mutex);
return i;
}
int mc13783_write(unsigned address, uint32_t data)
{
uint32_t packet;
int i;
if (address >= MC13783_NUM_REGS)
return -1;
packet = (1 << 31) | (address << 25) | (data & 0xffffff);
mutex_lock(&mc13783_spi_mutex);
mc13783_transfer.txbuf = &packet;
mc13783_transfer.rxbuf = NULL;
mc13783_transfer.count = 1;
i = -1;
if (spi_transfer(&mc13783_transfer) && wait_for_transfer_complete())
i = 1 - mc13783_transfer.count;
mutex_unlock(&mc13783_spi_mutex);
return i;
}
int spi_sendreadcommand(unsigned char command, int len,unsigned char* buf)
{
int i=0;
unsigned char dummy_value = 0xff;
//Set the control register . Clear the fifo bits and set TA =1
start_spi_transfer();
//Clear GPI0 25.Sending a command
set_DC_low_for_command();
//Wait till the TX buffer has space to send a byte
wait_till_tx_fifo_not_full();
//Put the command in the fifo
PUT32(SPI_TX_RX_FIFO,command);
//Wait for transfer to be complete
wait_for_transfer_complete();
//Simply read the FIFO to ermpty
GET32(SPI_TX_RX_FIFO);
//Set GPIO25
set_DC_high_for_data();
for(i =0; i<len; i++)
{
PUT32(SPI_TX_RX_FIFO,dummy_value);
//Wait till there is data
wait_till_rx_fifo_has_data();
//Get the data from the fifo
buf[i] = GET32(SPI_TX_RX_FIFO);
}
//Set TA = 0 and clear the fifo
stop_spi_transfer();
/*spi_sendbytes(1,&dummy_value);
for(i =0; i<len; i++)
{
spi_getbytes(&buf[i],len);
}*/
return 0;
}
uint32_t mc13783_read(unsigned address)
{
uint32_t packet;
if (address >= MC13783_NUM_REGS)
return MC13783_DATA_ERROR;
packet = address << 25;
mutex_lock(&mc13783_spi_mutex);
mc13783_transfer.txbuf = &packet;
mc13783_transfer.rxbuf = &packet;
mc13783_transfer.count = 1;
if (!spi_transfer(&mc13783_transfer) || !wait_for_transfer_complete())
packet = MC13783_DATA_ERROR;
mutex_unlock(&mc13783_spi_mutex);
return packet;
}
static int send_recv_packets(
struct i2c_bus *i2c_bus,
struct i2c_trans_info *trans)
{
struct i2c_control *control = i2c_bus->control;
u32 int_status;
u32 words;
u8 *dptr;
u32 local;
uchar last_bytes;
int error = 0;
int is_write = trans->flags & I2C_IS_WRITE;
/* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */
int_status = readl(&control->int_status);
writel(int_status, &control->int_status);
send_packet_headers(i2c_bus, trans, 1);
words = BYTES_TO_WORDS(trans->num_bytes);
last_bytes = trans->num_bytes & 3;
dptr = trans->buf;
while (words) {
if (is_write) {
/* deal with word alignment */
if ((unsigned)dptr & 3) {
memcpy(&local, dptr, sizeof(u32));
writel(local, &control->tx_fifo);
debug("pkt data sent (0x%x)\n", local);
} else {
writel(*(u32 *)dptr, &control->tx_fifo);
debug("pkt data sent (0x%x)\n", *(u32 *)dptr);
}
if (!wait_for_tx_fifo_empty(control)) {
error = -1;
goto exit;
}
} else {
if (!wait_for_rx_fifo_notempty(control)) {
error = -1;
goto exit;
}
/*
* for the last word, we read into our local buffer,
* in case that caller did not provide enough buffer.
*/
local = readl(&control->rx_fifo);
if ((words == 1) && last_bytes)
memcpy(dptr, (char *)&local, last_bytes);
else if ((unsigned)dptr & 3)
memcpy(dptr, &local, sizeof(u32));
else
*(u32 *)dptr = local;
debug("pkt data received (0x%x)\n", local);
}
words--;
dptr += sizeof(u32);
}
if (wait_for_transfer_complete(control)) {
error = -1;
goto exit;
}
return 0;
exit:
/* error, reset the controller. */
i2c_reset_controller(i2c_bus);
return error;
}
