static int dyna_alpha_pll_dynamic_update(struct alpha_pll_clk *pll)
{
struct alpha_pll_masks *masks = pll->masks;
u32 regval;
int rc;
regval = readl_relaxed(UPDATE_REG(pll));
regval |= masks->update_mask;
writel_relaxed(regval, UPDATE_REG(pll));
rc = wait_for_dynamic_update(pll);
if (rc < 0)
return rc;
/*
* HPG mandates a wait of at least 570ns before polling the LOCK
* detect bit. Have a delay of 1us just to be safe.
*/
mb();
udelay(1);
rc = wait_for_update(pll);
if (rc < 0)
return rc;
return 0;
}
static int __alpha_pll_enable(struct alpha_pll_clk *pll, int enable_output)
{
int rc;
u32 mode;
mode = readl_relaxed(MODE_REG(pll));
mode |= PLL_BYPASSNL;
writel_relaxed(mode, MODE_REG(pll));
/*
* H/W requires a 5us delay between disabling the bypass and
* de-asserting the reset.
*/
mb();
udelay(5);
mode |= PLL_RESET_N;
writel_relaxed(mode, MODE_REG(pll));
rc = wait_for_update(pll);
if (rc < 0)
return rc;
/* Enable PLL output. */
if (enable_output) {
mode |= PLL_OUTCTRL;
writel_relaxed(mode, MODE_REG(pll));
}
/* Ensure that the write above goes through before returning. */
mb();
return 0;
}
static int __alpha_pll_vote_enable(struct alpha_pll_clk *pll)
{
u32 ena;
ena = readl_relaxed(VOTE_REG(pll));
ena |= pll->fsm_en_mask;
writel_relaxed(ena, VOTE_REG(pll));
mb();
return wait_for_update(pll);
}
static inline void auto_cal_disable(void)
{
int err;
emc_writel(0, EMC_AUTO_CAL_INTERVAL);
err = wait_for_update(EMC_AUTO_CAL_STATUS,
EMC_AUTO_CAL_STATUS_ACTIVE, false);
if (err) {
pr_err("%s: disable auto-cal error: %d", __func__, err);
BUG();
}
}
static inline void emc_timing_update(void)
{
int err;
emc_writel(0x1, EMC_TIMING_CONTROL);
err = wait_for_update(EMC_STATUS,
EMC_STATUS_TIMING_UPDATE_STALLED, false);
if (err) {
pr_err("%s: timing update error: %d", __func__, err);
BUG();
}
}
static inline void do_clock_change(u32 clk_setting)
{
int err;
mc_readl(MC_EMEM_ADR_CFG); /* completes prev writes */
writel(clk_setting, clk_base + emc->reg);
readl(clk_base + emc->reg);/* completes prev write */
err = wait_for_update(EMC_INTSTATUS,
EMC_INTSTATUS_CLKCHANGE_COMPLETE, true);
if (err) {
pr_err("%s: clock change completion error: %d", __func__, err);
BUG();
}
}
static int alpha_pll_enable_hwfsm(struct clk *c)
{
u32 mode;
struct alpha_pll_clk *pll = to_alpha_pll_clk(c);
/* Re-enable HW FSM mode, clear OFFLINE request */
mode = readl_relaxed(MODE_REG(pll));
mode |= PLL_FSM_ENA_BIT;
mode &= ~PLL_OFFLINE_REQ_BIT;
writel_relaxed(mode, MODE_REG(pll));
/* Make sure enable request goes through before waiting for update */
mb();
if (wait_for_update(pll) < 0)
panic("PLL %s failed to lock", c->dbg_name);
return 0;
}
static int __fabia_alpha_pll_enable(struct alpha_pll_clk *pll)
{
int rc;
u32 mode;
/* Disable PLL output */
mode = readl_relaxed(MODE_REG(pll));
mode &= ~PLL_OUTCTRL;
writel_relaxed(mode, MODE_REG(pll));
/* Set operation mode to STANDBY */
writel_relaxed(FABIA_PLL_STANDBY, FABIA_PLL_OPMODE(pll));
/* PLL should be in STANDBY mode before continuing */
mb();
/* Bring PLL out of reset */
mode = readl_relaxed(MODE_REG(pll));
mode |= PLL_RESET_N;
writel_relaxed(mode, MODE_REG(pll));
/* Set operation mode to RUN */
writel_relaxed(FABIA_PLL_RUN, FABIA_PLL_OPMODE(pll));
rc = wait_for_update(pll);
if (rc < 0)
return rc;
/* Enable the main PLL output */
mode = readl_relaxed(FABIA_USER_CTL_LO_REG(pll));
mode |= FABIA_PLL_OUT_MAIN;
writel_relaxed(mode, FABIA_USER_CTL_LO_REG(pll));
/* Enable PLL outputs */
mode = readl_relaxed(MODE_REG(pll));
mode |= PLL_OUTCTRL;
writel_relaxed(mode, MODE_REG(pll));
/* Ensure that the write above goes through before returning. */
mb();
return 0;
}
