static void sata_init(struct device *dev) { u8 byte; u16 word; u32 dword; void *sata_bar5; u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4; int i, j; struct southbridge_ati_sb600_config *conf; conf = dev->chip_info; device_t sm_dev; /* SATA SMBus Disable */ /* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); /* Disable SATA SMBUS */ byte = pci_read_config8(sm_dev, 0xad); byte |= (1 << 1); /* Enable SATA and power saving */ byte = pci_read_config8(sm_dev, 0xad); byte |= (1 << 0); byte |= (1 << 5); pci_write_config8(sm_dev, 0xad, byte); /* Set the interrupt Mapping to INTG# */ byte = pci_read_config8(sm_dev, 0xaf); byte = 0x6 << 2; pci_write_config8(sm_dev, 0xaf, byte); /* get base address */ sata_bar5 = (void *)(pci_read_config32(dev, 0x24) & ~0x3FF); sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7; sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3; sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7; sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x3; sata_bar4 = pci_read_config16(dev, 0x20) & ~0xf; printk(BIOS_SPEW, "sata_bar0=%x\n", sata_bar0); /* 3030 */ printk(BIOS_SPEW, "sata_bar1=%x\n", sata_bar1); /* 3070 */ printk(BIOS_SPEW, "sata_bar2=%x\n", sata_bar2); /* 3040 */ printk(BIOS_SPEW, "sata_bar3=%x\n", sata_bar3); /* 3080 */ printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4); /* 3000 */ printk(BIOS_SPEW, "sata_bar5=%p\n", sata_bar5); /* e0309000 */ /* SERR-Enable */ word = pci_read_config16(dev, 0x04); word |= (1 << 8); pci_write_config16(dev, 0x04, word); /* Dynamic power saving */ byte = pci_read_config8(dev, 0x40); byte |= (1 << 2); pci_write_config8(dev, 0x40, byte); /* Set SATA Operation Mode */ byte = pci_read_config8(dev, 0x40); byte |= (1 << 0); byte |= (1 << 4); pci_write_config8(dev, 0x40, byte); // 1 means IDE, 0 means AHCI i = CONFIG_SATA_MODE; get_option(&i, "sata_mode"); printk(BIOS_INFO, "%s: setting sata mode = %s\n", __func__, (i == SATA_MODE_IDE)?"ide":"ahci" ); dword = pci_read_config32(dev, 0x8); dword &= 0xff0000ff; if (i == SATA_MODE_IDE) dword |= 0x00018f00; // IDE mode else dword |= 0x00060100; // AHCI mode pci_write_config32(dev, 0x8, dword); byte = pci_read_config8(dev, 0x40); byte &= ~(1 << 0); pci_write_config8(dev, 0x40, byte); /* Enable the SATA watchdog counter */ byte = pci_read_config8(dev, 0x44); byte |= (1 << 0); pci_write_config8(dev, 0x44, byte); /* Program the watchdog counter to 0x10 */ byte = 0x10; pci_write_config8(dev, 0x46, byte); /* RPR6.5 Program the PHY Global Control to 0x2C00 for A13 */ word = 0x2c00; pci_write_config16(dev, 0x86, word); /* RPR6.5 Program the Phy Tuning4Ports */ dword = 0x00B401D6; pci_write_config32(dev, 0x88, dword); pci_write_config32(dev, 0x8c, dword); pci_write_config32(dev, 0x90, dword); pci_write_config32(dev, 0x94, dword); byte = 0xB8; pci_write_config8(dev, 0xA5, byte); pci_write_config8(dev, 0xAD, byte); pci_write_config8(dev, 0xB5, byte); pci_write_config8(dev, 0xBD, byte); /* RPR 6.8 */ word = pci_read_config16(dev, 0x42); word |= 1 << 7; pci_write_config16(dev, 0x42, word); /* RPR 6.9 */ dword = pci_read_config32(dev, 0x40); dword |= 1 << 25; pci_write_config32(dev, 0x40, dword); /* Enable the I/O, MM, BusMaster access for SATA */ byte = pci_read_config8(dev, 0x4); byte |= 7 << 0; pci_write_config8(dev, 0x4, byte); /* RPR6.6 SATA drive detection. */ /* Use BAR5+0x128,BAR0 for Primary Slave */ /* Use BAR5+0x1A8,BAR0 for Primary Slave */ /* Use BAR5+0x228,BAR2 for Secondary Master */ /* Use BAR5+0x2A8,BAR2 for Secondary Slave */ for (i = 0; i < 4; i++) { byte = read8(sata_bar5 + 0x128 + 0x80 * i); printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte); byte &= 0xF; if ( byte == 0x1 ) { /* If the drive status is 0x1 then we see it but we aren't talking to it. */ /* Try to do something about it. */ printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n"); /* Read in Port-N Serial ATA Control Register */ byte = read8(sata_bar5 + 0x12C + 0x80 * i); /* Set Reset Bit and 1.5g bit */ byte |= 0x11; write8((sata_bar5 + 0x12C + 0x80 * i), byte); /* Wait 1ms */ mdelay(1); /* Clear Reset Bit */ byte &= ~0x01; write8((sata_bar5 + 0x12C + 0x80 * i), byte); /* Wait 1ms */ mdelay(1); /* Reread status */ byte = read8(sata_bar5 + 0x128 + 0x80 * i); printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte); byte &= 0xF; } if (byte == 0x3) { for (j = 0; j < 10; j++) { if (!sata_drive_detect(i, ((i / 2) == 0) ? sata_bar0 : sata_bar2)) break; } printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n", (i / 2) ? "Secondary" : "Primary", (i % 2 ) ? "Slave" : "Master", (j == 10) ? "not " : "", (j == 10) ? j : j + 1); } else { printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n", (i / 2) ? "Secondary" : "Primary", (i % 2 ) ? "Slave" : "Master", i); } } /* Below is CIM InitSataLateFar */ /* Enable interrupts from the HBA */ byte = read8(sata_bar5 + 0x4); byte |= 1 << 1; write8((sata_bar5 + 0x4), byte); /* Clear error status */ write32((sata_bar5 + 0x130), 0xFFFFFFFF); write32((sata_bar5 + 0x1b0), 0xFFFFFFFF); write32((sata_bar5 + 0x230), 0xFFFFFFFF); write32((sata_bar5 + 0x2b0), 0xFFFFFFFF); /* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */ /* ????? why CIM does not set the AcpiGpe0BlkAddr , but use it??? */ /* word = 0x0000; */ /* word = pm_ioread(0x28); */ /* byte = pm_ioread(0x29); */ /* word |= byte<<8; */ /* printk(BIOS_DEBUG, "AcpiGpe0Blk addr = %x\n", word); */ /* write32(word, 0x80000000); */ }
bool write_keys (int fd, struct key_container *keys, struct octet_buffer *data_zone) { assert (NULL != data_zone); assert (STATE_INITIALIZED == get_device_state (fd)); bool free_keys = false; #define KEY_LEN 32 const unsigned int TEST_KEY_1 = 14; const unsigned int TEST_KEY_2 = 15; struct octet_buffer test_key_14 = make_buffer (KEY_LEN); memset(test_key_14.ptr, 0xAA, KEY_LEN); struct octet_buffer test_key_15 = make_buffer (KEY_LEN); memset(test_key_15.ptr, 0xBB, KEY_LEN); int x = 0; /* If there are no keys, which is the case when we are personalizing a device from scratch, create some new keys */ if (NULL == keys) { keys = make_key_container (); for (x=0; x < get_max_keys (); x++) { if (TEST_KEY_1 == x) { keys->keys[x] = test_key_14; } else if (TEST_KEY_2 == x) { keys->keys[x] = test_key_15; } else { keys->keys[x] = get_random (fd, false); } } free_keys = true; } bool status = true; for (x=0; x < get_max_keys () && status; x++) { const unsigned int WORD_OFFSET = 8; unsigned int addr = WORD_OFFSET * x; status = write32 (fd, DATA_ZONE, addr, keys->keys[x], NULL); } if (status) { data_zone->len = get_max_keys () * keys->keys[0].len; data_zone->ptr = malloc_wipe (data_zone->len); for (x=0; x < get_max_keys (); x++) { CTX_LOG(DEBUG, "Writing key %u", x); unsigned int offset = x * keys->keys[x].len; memcpy(data_zone->ptr + offset, keys->keys[x].ptr, keys->keys[x].len); } status = record_keys (keys); } if (free_keys) free_key_container (keys); return status; }
static int intel_gma_init(struct northbridge_intel_i945_config *conf, unsigned int pphysbase, unsigned int piobase, unsigned int pmmio, unsigned int pgfx) { struct edid edid; u8 edid_data[128]; unsigned long temp; int hpolarity, vpolarity; u32 candp1, candn; u32 best_delta = 0xffffffff; u32 target_frequency; u32 pixel_p1 = 1; u32 pixel_n = 1; u32 pixel_m1 = 1; u32 pixel_m2 = 1; u32 hactive, vactive, right_border, bottom_border; u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; u32 i, j; u32 uma_size; u16 reg16; printk(BIOS_SPEW, "i915lightup: graphics %p mmio %08x addrport %04x physbase %08x\n", (void *)pgfx, pmmio, piobase, pphysbase); intel_gmbus_read_edid(pmmio + GMBUS0, 3, 0x50, edid_data, 128); decode_edid(edid_data, sizeof(edid_data), &edid); hpolarity = (edid.phsync == '-'); vpolarity = (edid.pvsync == '-'); hactive = edid.x_resolution; vactive = edid.y_resolution; right_border = edid.hborder; bottom_border = edid.vborder; vblank = edid.vbl; hblank = edid.hbl; vsync = edid.vspw; hsync = edid.hspw; hfront_porch = edid.hso; vfront_porch = edid.vso; for (i = 0; i < 2; i++) for (j = 0; j < 0x100; j++) /* R=j, G=j, B=j. */ write32(pmmio + PALETTE(i) + 4 * j, 0x10101 * j); write32(pmmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | (read32(pmmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK)); write32(pmmio + MI_ARB_STATE, MI_ARB_C3_LP_WRITE_ENABLE | (1 << 27)); /* Clean registers. */ for (i = 0; i < 0x20; i += 4) write32(pmmio + RENDER_RING_BASE + i, 0); for (i = 0; i < 0x20; i += 4) write32(pmmio + FENCE_REG_965_0 + i, 0); write32(pmmio + PP_ON_DELAYS, 0); write32(pmmio + PP_OFF_DELAYS, 0); /* Disable VGA. */ write32(pmmio + VGACNTRL, VGA_DISP_DISABLE); /* Disable pipes. */ write32(pmmio + PIPECONF(0), 0); write32(pmmio + PIPECONF(1), 0); /* Init PRB0. */ write32(pmmio + HWS_PGA, 0x352d2000); write32(pmmio + PRB0_CTL, 0); write32(pmmio + PRB0_HEAD, 0); write32(pmmio + PRB0_TAIL, 0); write32(pmmio + PRB0_START, 0); write32(pmmio + PRB0_CTL, 0x0001f001); write32(pmmio + D_STATE, DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | DSTATE_DOT_CLOCK_GATING); write32(pmmio + ECOSKPD, 0x00010000); write32(pmmio + HWSTAM, 0xeffe); write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug); write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS); target_frequency = conf->gpu_lvds_is_dual_channel ? edid.pixel_clock : (2 * edid.pixel_clock); /* Find suitable divisors. */ for (candp1 = 1; candp1 <= 8; candp1++) { for (candn = 5; candn <= 10; candn++) { u32 cur_frequency; u32 m; /* 77 - 131. */ u32 denom; /* 35 - 560. */ u32 current_delta; denom = candn * candp1 * 7; /* Doesnt overflow for up to 5000000 kHz = 5 GHz. */ m = (target_frequency * denom + BASE_FREQUENCY / 2) / BASE_FREQUENCY; if (m < 77 || m > 131) continue; cur_frequency = (BASE_FREQUENCY * m) / denom; if (target_frequency > cur_frequency) current_delta = target_frequency - cur_frequency; else current_delta = cur_frequency - target_frequency; if (best_delta > current_delta) { best_delta = current_delta; pixel_n = candn; pixel_p1 = candp1; pixel_m2 = ((m + 3) % 5) + 7; pixel_m1 = (m - pixel_m2) / 5; } } } if (best_delta == 0xffffffff) { printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); return -1; } printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", hactive, vactive); printk(BIOS_DEBUG, "Borders %d x %d\n", right_border, bottom_border); printk(BIOS_DEBUG, "Blank %d x %d\n", hblank, vblank); printk(BIOS_DEBUG, "Sync %d x %d\n", hsync, vsync); printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch); printk(BIOS_DEBUG, (conf->gpu_lvds_use_spread_spectrum_clock ? "Spread spectrum clock\n" : "DREF clock\n")); printk(BIOS_DEBUG, (conf->gpu_lvds_is_dual_channel ? "Dual channel\n" : "Single channel\n")); printk(BIOS_DEBUG, "Polarities %d, %d\n", hpolarity, vpolarity); printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", pixel_n, pixel_m1, pixel_m2, pixel_p1); printk(BIOS_DEBUG, "Pixel clock %d kHz\n", BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n / (pixel_p1 * 7)); #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); write32(pmmio + PF_WIN_POS(0), 0); write32(pmmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); write32(pmmio + PFIT_CONTROL, PFIT_ENABLE | (1 << PFIT_PIPE_SHIFT) | HORIZ_AUTO_SCALE | VERT_AUTO_SCALE); #else /* Disable panel fitter (we're in native resolution). */ write32(pmmio + PF_CTL(0), 0); write32(pmmio + PF_WIN_SZ(0), 0); write32(pmmio + PF_WIN_POS(0), 0); write32(pmmio + PFIT_PGM_RATIOS, 0); write32(pmmio + PFIT_CONTROL, 0); #endif mdelay(1); write32(pmmio + DSPCNTR(0), DISPPLANE_BGRX888 | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE); mdelay(1); write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); write32(pmmio + FP0(1), ((pixel_n - 2) << 16) | ((pixel_m1 - 2) << 8) | pixel_m2); write32(pmmio + DPLL(1), DPLL_VGA_MODE_DIS | DPLL_VCO_ENABLE | DPLLB_MODE_LVDS | (conf->gpu_lvds_is_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (conf->gpu_lvds_use_spread_spectrum_clock ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV : 0) | (pixel_p1 << 16) | (pixel_p1)); mdelay(1); write32(pmmio + DPLL(1), DPLL_VGA_MODE_DIS | DPLL_VCO_ENABLE | DPLLB_MODE_LVDS | (conf->gpu_lvds_is_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) | (pixel_p1 << 16) | (pixel_p1)); mdelay(1); write32(pmmio + HTOTAL(1), ((hactive + right_border + hblank - 1) << 16) | (hactive - 1)); write32(pmmio + HBLANK(1), ((hactive + right_border + hblank - 1) << 16) | (hactive + right_border - 1)); write32(pmmio + HSYNC(1), ((hactive + right_border + hfront_porch + hsync - 1) << 16) | (hactive + right_border + hfront_porch - 1)); write32(pmmio + VTOTAL(1), ((vactive + bottom_border + vblank - 1) << 16) | (vactive - 1)); write32(pmmio + VBLANK(1), ((vactive + bottom_border + vblank - 1) << 16) | (vactive + bottom_border - 1)); write32(pmmio + VSYNC(1), (vactive + bottom_border + vfront_porch + vsync - 1) | (vactive + bottom_border + vfront_porch - 1)); #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) write32(pmmio + PIPESRC(1), (639 << 16) | 399); #else write32(pmmio + PIPESRC(1), ((hactive - 1) << 16) | (vactive - 1)); #endif mdelay(1); write32(pmmio + DSPSIZE(0), (hactive - 1) | ((vactive - 1) << 16)); write32(pmmio + DSPPOS(0), 0); /* Backlight init. */ write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); write32(pmmio + FW_BLC, 0x011d011a); write32(pmmio + FW_BLC2, 0x00000102); write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); write32(pmmio + FW_BLC_SELF, 0x0001003f); write32(pmmio + FW_BLC, 0x011d0109); write32(pmmio + FW_BLC2, 0x00000102); write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); write32(pmmio + BLC_PWM_CTL, conf->gpu_backlight); edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; write32(pmmio + DSPADDR(0), 0); write32(pmmio + DSPSURF(0), 0); write32(pmmio + DSPSTRIDE(0), edid.bytes_per_line); write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888 | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE); mdelay(1); write32(pmmio + PIPECONF(1), PIPECONF_ENABLE); write32(pmmio + LVDS, LVDS_ON | (hpolarity << 20) | (vpolarity << 21) | (conf->gpu_lvds_is_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_CLOCK_A_POWERUP_ALL | LVDS_PIPE(1)); write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET); mdelay(1); write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_ON | PANEL_POWER_RESET); printk (BIOS_DEBUG, "waiting for panel powerup\n"); while (1) { u32 reg32; reg32 = read32(pmmio + PP_STATUS); if ((reg32 & PP_SEQUENCE_MASK) == PP_SEQUENCE_NONE) break; } printk (BIOS_DEBUG, "panel powered up\n"); write32(pmmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); /* Clear interrupts. */ write32(pmmio + DEIIR, 0xffffffff); write32(pmmio + SDEIIR, 0xffffffff); write32(pmmio + IIR, 0xffffffff); write32(pmmio + IMR, 0xffffffff); write32(pmmio + EIR, 0xffffffff); if (gtt_setup(pmmio)) { printk(BIOS_ERR, "ERROR: GTT Setup Failed!!!\n"); return 0; } /* Setup GTT. */ reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); uma_size = 0; if (!(reg16 & 2)) { reg16 >>= 4; reg16 &= 7; switch (reg16) { case 1: uma_size = 1024; break; case 3: uma_size = 8192; break; } printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); }
static int rk_edp_dpcd_transfer(struct rk_edp *edp, unsigned int val_addr, u8 *data, unsigned int length, enum dpcd_request request) { int val; int i, try_times; int retval = 0; u32 len = 0; while (length) { len = MIN(length, 16); for (try_times = 0; try_times < 10; try_times++) { /* Clear AUX CH data buffer */ val = BUF_CLR; write32(&edp->regs->buf_data_ctl, val); /* Select DPCD device address */ val = AUX_ADDR_7_0(val_addr); write32(&edp->regs->aux_addr_7_0, val); val = AUX_ADDR_15_8(val_addr); write32(&edp->regs->aux_addr_15_8, val); val = AUX_ADDR_19_16(val_addr); write32(&edp->regs->aux_addr_19_16, val); /* * Set DisplayPort transaction and read 1 byte * If bit 3 is 1, DisplayPort transaction. * If Bit 3 is 0, I2C transaction. */ if (request == DPCD_WRITE) { val = AUX_LENGTH(len) | AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; for (i = 0; i < len; i++) write32(&edp->regs->buf_data[i], *data++); } else val = AUX_LENGTH(len) | AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; write32(&edp->regs->aux_ch_ctl_1, val); /* Start AUX transaction */ retval = rk_edp_start_aux_transaction(edp); if (retval == 0) break; else printk(BIOS_WARNING, "read dpcd Aux Transaction fail!\n"); } if (retval) return -1; if (request == DPCD_READ) { for (i = 0; i < len; i++) *data++ = (u8)read32(&edp->regs->buf_data[i]); } length -= len; val_addr += 16; } return 0; }
static void rk_edp_init_interrupt(struct rk_edp *edp) { /* Set interrupt pin assertion polarity as high */ write32(&edp->regs->int_ctl, INT_POL); /* Clear pending registers */ write32(&edp->regs->common_int_sta_1, 0xff); write32(&edp->regs->common_int_sta_2, 0x4f); write32(&edp->regs->common_int_sta_3, 0xff); write32(&edp->regs->common_int_sta_4, 0x27); write32(&edp->regs->dp_int_sta, 0x7f); /* 0:mask,1: unmask */ write32(&edp->regs->common_int_mask_1, 0x00); write32(&edp->regs->common_int_mask_2, 0x00); write32(&edp->regs->common_int_mask_3, 0x00); write32(&edp->regs->common_int_mask_4, 0x00); write32(&edp->regs->int_sta_mask, 0x00); }
static void sata_init(struct device *dev) { u8 byte; u16 word; u32 dword; u8 rev_id; u32 sata_bar5; u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4; int i, j; struct southbridge_ati_sb700_config *conf; conf = dev->chip_info; device_t sm_dev; /* SATA SMBus Disable */ /* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); /* Disable SATA SMBUS */ byte = pci_read_config8(sm_dev, 0xad); byte |= (1 << 1); /* Enable SATA and power saving */ byte = pci_read_config8(sm_dev, 0xad); byte |= (1 << 0); byte |= (1 << 5); pci_write_config8(sm_dev, 0xad, byte); /* RPR 7.2 SATA Initialization */ /* Set the interrupt Mapping to INTG# */ byte = pci_read_config8(sm_dev, 0xaf); byte = 0x6 << 2; pci_write_config8(sm_dev, 0xaf, byte); /* get rev_id */ rev_id = pci_read_config8(sm_dev, 0x08) - 0x28; /* get base address */ sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF; sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7; sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3; sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7; sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x3; sata_bar4 = pci_read_config16(dev, 0x20) & ~0xf; printk(BIOS_SPEW, "sata_bar0=%x\n", sata_bar0); /* 3030 */ printk(BIOS_SPEW, "sata_bar1=%x\n", sata_bar1); /* 3070 */ printk(BIOS_SPEW, "sata_bar2=%x\n", sata_bar2); /* 3040 */ printk(BIOS_SPEW, "sata_bar3=%x\n", sata_bar3); /* 3080 */ printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4); /* 3000 */ printk(BIOS_SPEW, "sata_bar5=%x\n", sata_bar5); /* e0309000 */ /* disable combined mode */ byte = pci_read_config8(sm_dev, 0xAD); byte &= ~(1 << 3); pci_write_config8(sm_dev, 0xAD, byte); /* Program the 2C to 0x43801002 */ dword = 0x43801002; pci_write_config32(dev, 0x2c, dword); /* SERR-Enable */ word = pci_read_config16(dev, 0x04); word |= (1 << 8); pci_write_config16(dev, 0x04, word); /* Dynamic power saving */ byte = pci_read_config8(dev, 0x40); byte |= (1 << 2); pci_write_config8(dev, 0x40, byte); /* Set SATA Operation Mode, Set to IDE mode */ byte = pci_read_config8(dev, 0x40); byte |= (1 << 0); byte |= (1 << 4); pci_write_config8(dev, 0x40, byte); dword = 0x01018f00; pci_write_config32(dev, 0x8, dword); byte = pci_read_config8(dev, 0x40); byte &= ~(1 << 0); pci_write_config8(dev, 0x40, byte); /* Enable the SATA watchdog counter */ byte = pci_read_config8(dev, 0x44); byte |= (1 << 0); pci_write_config8(dev, 0x44, byte); /* Set bit 29 and 24 for A12 */ dword = pci_read_config32(dev, 0x40); if (rev_id < 0x14) /* before A12 */ dword |= (1 << 29); else dword &= ~(1 << 29); /* A14 and above */ pci_write_config32(dev, 0x40, dword); /* set bit 21 for A12 */ dword = pci_read_config32(dev, 0x48); if (rev_id < 0x14) /* before A12 */ dword |= 1 << 24 | 1 << 21; else { dword &= ~(1 << 24 | 1 << 21); /* A14 and above */ dword &= ~0xFF80; /* 15:7 */ dword |= 1 << 15 | 0x7F << 7; } pci_write_config32(dev, 0x48, dword); /* Program the watchdog counter to 0x10 */ byte = 0x10; pci_write_config8(dev, 0x46, byte); sb700_setup_sata_phys(dev); /* Enable the I/O, MM, BusMaster access for SATA */ byte = pci_read_config8(dev, 0x4); byte |= 7 << 0; pci_write_config8(dev, 0x4, byte); /* RPR7.7 SATA drive detection. */ /* Use BAR5+0x128,BAR0 for Primary Slave */ /* Use BAR5+0x1A8,BAR0 for Primary Slave */ /* Use BAR5+0x228,BAR2 for Secondary Master */ /* Use BAR5+0x2A8,BAR2 for Secondary Slave */ /* Use BAR5+0x328,PATA_BAR0/2 for Primary/Secondary master emulation */ /* Use BAR5+0x3A8,PATA_BAR0/2 for Primary/Secondary Slave emulation */ /* TODO: port 4,5, which are PATA emulations. What are PATA_BARs? */ for (i = 0; i < 4; i++) { byte = read8(sata_bar5 + 0x128 + 0x80 * i); printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte); byte &= 0xF; if( byte == 0x1 ) { /* If the drive status is 0x1 then we see it but we aren't talking to it. */ /* Try to do something about it. */ printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n"); /* Read in Port-N Serial ATA Control Register */ byte = read8(sata_bar5 + 0x12C + 0x80 * i); /* Set Reset Bit and 1.5g bit */ byte |= 0x11; write8((sata_bar5 + 0x12C + 0x80 * i), byte); /* Wait 1ms */ mdelay(1); /* Clear Reset Bit */ byte &= ~0x01; write8((sata_bar5 + 0x12C + 0x80 * i), byte); /* Wait 1ms */ mdelay(1); /* Reread status */ byte = read8(sata_bar5 + 0x128 + 0x80 * i); printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte); byte &= 0xF; } if (byte == 0x3) { for (j = 0; j < 10; j++) { if (!sata_drive_detect(i, ((i / 2) == 0) ? sata_bar0 : sata_bar2)) break; } printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n", (i / 2) ? "Secondary" : "Primary", (i % 2 ) ? "Slave" : "Master", (j == 10) ? "not " : "", (j == 10) ? j : j + 1); } else { printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n", (i / 2) ? "Secondary" : "Primary", (i % 2 ) ? "Slave" : "Master", i); } } /* Below is CIM InitSataLateFar */ /* Enable interrupts from the HBA */ byte = read8(sata_bar5 + 0x4); byte |= 1 << 1; write8((sata_bar5 + 0x4), byte); /* Clear error status */ write32((sata_bar5 + 0x130), 0xFFFFFFFF); write32((sata_bar5 + 0x1b0), 0xFFFFFFFF); write32((sata_bar5 + 0x230), 0xFFFFFFFF); write32((sata_bar5 + 0x2b0), 0xFFFFFFFF); write32((sata_bar5 + 0x330), 0xFFFFFFFF); write32((sata_bar5 + 0x3b0), 0xFFFFFFFF); /* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */ /* ????? why CIM does not set the AcpiGpe0BlkAddr , but use it??? */ /* word = 0x0000; */ /* word = pm_ioread(0x28); */ /* byte = pm_ioread(0x29); */ /* word |= byte<<8; */ /* printk(BIOS_DEBUG, "AcpiGpe0Blk addr = %x\n", word); */ /* write32(word, 0x80000000); */ }
static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int bus_isa; u32 dword; u8 byte; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); memcpy(mc->mpc_oem, "AMD ", 8); smp_write_processors(mc); //mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; my_smp_write_bus(mc, bus_isa, "ISA "); /* I/O APICs: APIC ID Version State Address */ dword = 0; dword = pm_read8(0x34) & 0xF0; dword |= (pm_read8(0x35) & 0xFF) << 8; dword |= (pm_read8(0x36) & 0xFF) << 16; dword |= (pm_read8(0x37) & 0xFF) << 24; /* Set IO APIC ID onto IO_APIC_ID */ write32 (dword, 0x00); write32 (dword + 0x10, IO_APIC_ID << 24); apicid_hudson = IO_APIC_ID; smp_write_ioapic(mc, apicid_hudson, 0x21, dword); /* PIC IRQ routine */ for (byte = 0x0; byte < sizeof(picr_data); byte ++) { outb(byte, 0xC00); outb(picr_data[byte], 0xC01); } /* APIC IRQ routine */ for (byte = 0x0; byte < sizeof(intr_data); byte ++) { outb(byte | 0x80, 0xC00); outb(intr_data[byte], 0xC01); } /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_hudson, 0); /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ #define PCI_INT(bus, dev, int_sign, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin)) /* Internal VGA */ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); /* SMBUS */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* HD Audio */ PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); /* USB */ PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); /* sata */ PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); /* on board NIC & Slot PCIE. */ /* PCI slots */ /* PCI_SLOT 0. */ PCI_INT(bus_hudson[1], 0x5, 0x0, 0x14); PCI_INT(bus_hudson[1], 0x5, 0x1, 0x15); PCI_INT(bus_hudson[1], 0x5, 0x2, 0x16); PCI_INT(bus_hudson[1], 0x5, 0x3, 0x17); /* PCI_SLOT 1. */ PCI_INT(bus_hudson[1], 0x6, 0x0, 0x15); PCI_INT(bus_hudson[1], 0x6, 0x1, 0x16); PCI_INT(bus_hudson[1], 0x6, 0x2, 0x17); PCI_INT(bus_hudson[1], 0x6, 0x3, 0x14); /* PCI_SLOT 2. */ PCI_INT(bus_hudson[1], 0x7, 0x0, 0x16); PCI_INT(bus_hudson[1], 0x7, 0x1, 0x17); PCI_INT(bus_hudson[1], 0x7, 0x2, 0x14); PCI_INT(bus_hudson[1], 0x7, 0x3, 0x15); PCI_INT(bus_hudson[2], 0x0, 0x0, 0x12); PCI_INT(bus_hudson[2], 0x0, 0x1, 0x13); PCI_INT(bus_hudson[2], 0x0, 0x2, 0x14); /* PCIe Lan*/ PCI_INT(0x0, 0x06, 0x0, 0x13); /* FCH PCIe PortA */ PCI_INT(0x0, 0x15, 0x0, 0x10); /* FCH PCIe PortB */ PCI_INT(0x0, 0x15, 0x1, 0x11); /* FCH PCIe PortC */ PCI_INT(0x0, 0x15, 0x2, 0x12); /* FCH PCIe PortD */ PCI_INT(0x0, 0x15, 0x3, 0x13); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ return mptable_finalize(mc); }
void send_mcu_msg(void *msg, u32 size) { printk(BIOS_DEBUG, "sending msg to MCU...\n"); write32(&mvmap2315_sp_ipc->wdr0, (u32)msg); setbits_le32(&mvmap2315_sp_ipc->isrw, MVMAP2315_IPC_IRQSET_MSGSENT); }
static void usb_xhci_init(device_t dev) { u32 reg32; u16 reg16; u8 *mem_base = usb_xhci_mem_base(dev); config_t *config = dev->chip_info; /* D20:F0:74h[1:0] = 00b (set D0 state) */ reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS); reg16 &= ~PWR_CTL_SET_MASK; reg16 |= PWR_CTL_SET_D0; pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16); /* Enable clock gating first */ usb_xhci_clock_gating(dev); reg32 = read32(mem_base + 0x8144); if (pch_is_lp()) { /* XHCIBAR + 8144h[8,7,6] = 111b */ reg32 |= (1 << 8) | (1 << 7) | (1 << 6); } else { /* XHCIBAR + 8144h[8,7,6] = 100b */ reg32 &= ~((1 << 7) | (1 << 6)); reg32 |= (1 << 8); } write32(mem_base + 0x8144, reg32); if (pch_is_lp()) { /* XHCIBAR + 816Ch[19:0] = 000e0038h */ reg32 = read32(mem_base + 0x816c); reg32 &= ~0x000fffff; reg32 |= 0x000e0038; write32(mem_base + 0x816c, reg32); /* D20:F0:B0h[17,14,13] = 100b */ reg32 = pci_read_config32(dev, 0xb0); reg32 &= ~((1 << 14) | (1 << 13)); reg32 |= (1 << 17); pci_write_config32(dev, 0xb0, reg32); } reg32 = pci_read_config32(dev, 0x50); if (pch_is_lp()) { /* D20:F0:50h[28:0] = 0FCE2E5Fh */ reg32 &= ~0x1fffffff; reg32 |= 0x0fce2e5f; } else { /* D20:F0:50h[26:0] = 07886E9Fh */ reg32 &= ~0x07ffffff; reg32 |= 0x07886e9f; } pci_write_config32(dev, 0x50, reg32); /* D20:F0:44h[31] = 1 (Access Control Bit) */ reg32 = pci_read_config32(dev, 0x44); reg32 |= (1 << 31); pci_write_config32(dev, 0x44, reg32); /* D20:F0:40h[31,23] = 10b (OC Configuration Done) */ reg32 = pci_read_config32(dev, 0x40); reg32 &= ~(1 << 23); /* unsupported request */ reg32 |= (1 << 31); pci_write_config32(dev, 0x40, reg32); if (acpi_is_wakeup_s3()) { /* Reset ports that are disabled or * polling before returning to the OS. */ usb_xhci_reset_usb3(dev, 0); } else if (config->xhci_default) { /* Route all ports to XHCI */ outb(0xca, 0xb2); } }
static void sata_init(struct device *dev) { config_t *config = dev->chip_info; u32 reg32; u16 reg16; u8 reg8; printk(BIOS_DEBUG, "SATA: Initializing...\n"); if (config == NULL) { printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n"); return; } if (!config->sata_ahci) { /* Set legacy or native decoding mode */ if (config->ide_legacy_combined) { reg8 = pci_read_config8(dev, 0x09); reg8 &= ~0x5; pci_write_config8(dev, 0x09, reg8); } else { reg8 = pci_read_config8(dev, 0x09); reg8 |= 0x5; pci_write_config8(dev, 0x09, reg8); } /* Set capabilities pointer */ pci_write_config8(dev, 0x34, 0x70); reg16 = pci_read_config16(dev, 0x70); reg16 &= ~0xFF00; pci_write_config16(dev, 0x70, reg16); } /* Primary timing - decode enable */ reg16 = pci_read_config16(dev, 0x40); reg16 |= 1 << 15; pci_write_config16(dev, 0x40, reg16); /* Secondary timing - decode enable */ reg16 = pci_read_config16(dev, 0x42); reg16 |= 1 << 15; pci_write_config16(dev, 0x42, reg16); /* Port mapping enables */ reg16 = pci_read_config16(dev, 0x90); reg16 |= (config->sata_port_map ^ 0x3) << 8; pci_write_config16(dev, 0x90, reg16); /* Port control enables */ reg16 = pci_read_config16(dev, 0x92); reg16 &= ~0x003f; reg16 |= config->sata_port_map; pci_write_config16(dev, 0x92, reg16); if (config->sata_ahci) { u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); /* Enable CR memory space decoding */ reg16 = pci_read_config16(dev, 0x04); reg16 |= 0x2; pci_write_config16(dev, 0x04, reg16); /* Set capability register */ reg32 = read32(abar + 0x00); reg32 |= 0x0c046000; // set PSC+SSC+SALP+SSS+SAM reg32 &= ~0x00f20060; // clear SXS+EMS+PMS+gen bits reg32 |= (0x3 << 20); // Gen3 SATA write32(abar + 0x00, reg32); /* Ports enabled */ reg32 = read32(abar + 0x0c); reg32 &= (u32)(~0x3f); reg32 |= config->sata_port_map; write32(abar + 0xc, reg32); /* Two extra reads to latch */ read32(abar + 0x0c); read32(abar + 0x0c); /* Set cap2 - Support devslp */ reg32 = (1 << 5) | (1 << 4) | (1 << 3); write32(abar + 0x24, reg32); /* Set PxCMD registers */ reg32 = read32(abar + 0x118); reg32 &= ~((1 << 27) | (1 << 26) | (1 << 22) | (1 << 21) | (1 << 19) | (1 << 18) | (1 << 1)); reg32 |= 2; write32(abar + 0x118, reg32); reg32 = read32(abar + 0x198); reg32 &= ~((1 << 27) | (1 << 26) | (1 << 22) | (1 << 21) | (1 << 19) | (1 << 18) | (1 << 1)); reg32 |= 2; write32(abar + 0x198, reg32); /* Clear reset features */ write32(abar + 0xc8, 0); /* Enable interrupts */ reg8 = read8(abar + 0x04); reg8 |= 0x02; write8(abar + 0x04, reg8); } else { /* TODO(shawnn): Configure IDE SATA speed regs */ } /* 1.4 us delay after configuring port / enable bits */ udelay(2); /* Enable clock for ports */ reg32 = pci_read_config32(dev, 0x94); reg32 |= 0x3f << 24; pci_write_config32(dev, 0x94, reg32); reg32 &= (config->sata_port_map ^ 0x3) << 24; pci_write_config32(dev, 0x94, reg32); /* Lock SataGc register */ reg32 = (0x1 << 31) | (0x7 << 12); pci_write_config32(dev, 0x98, reg32); }
static void usb_init2(struct device *dev) { u32 dword; u32 usb2_bar0; device_t sm_dev; sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); //rev = get_sb800_revision(sm_dev); /* dword = pci_read_config32(dev, 0xf8); */ /* dword |= 40; */ /* pci_write_config32(dev, 0xf8, dword); */ usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF; printk(BIOS_INFO, "usb2_bar0=0x%x\n", usb2_bar0); /* RPR7.3 Enables the USB PHY auto calibration resister to match 45ohm resistence */ dword = 0x00020F00; write32(usb2_bar0 + 0xC0, dword); /* RPR7.8 Sets In/OUT FIFO threshold for best performance */ dword = 0x00400040; write32(usb2_bar0 + 0xA4, dword); /* RPR7.10 Disable EHCI MSI support */ dword = pci_read_config32(dev, 0x50); dword |= (1 << 6); pci_write_config32(dev, 0x50, dword); /* RPR7.12 EHCI Async Park Mode */ dword = pci_read_config32(dev, 0x50); dword &= ~(0xF << 8); dword &= ~(0xF << 12); dword |= 1 << 8; dword |= 2 << 12; pci_write_config32(dev, 0x50, dword); /* RPR 6.12 EHCI Advance PHY Power Savings */ /* RPR says it is just for A12. CIMM sets it when it is above A11. */ /* But it makes the linux crash, so we skip it */ #if 0 dword = pci_read_config32(dev, 0x50); dword |= 1 << 31; pci_write_config32(dev, 0x50, dword); #endif /* Each step below causes the linux crashes. Leave them here * for future debugging. */ #if 0 u8 byte; u16 word; /* RPR6.17 Disable the EHCI Dynamic Power Saving feature */ word = read32(usb2_bar0 + 0xBC); word &= ~(1 << 12); write16(usb2_bar0 + 0xBC, word); /* RPR6.19 USB Controller DMA Read Delay Tolerant. */ if (rev >= REV_SB800_A14) { byte = pci_read_config8(dev, 0x50); byte |= (1 << 7); pci_write_config8(dev, 0x50, byte); } /* RPR6.20 Async Park Mode. */ /* RPR recommends not to set these bits. */ #if 0 dword = pci_read_config32(dev, 0x50); dword |= 1 << 23; if (rev >= REV_SB800_A14) { dword &= ~(1 << 2); } pci_write_config32(dev, 0x50, dword); #endif /* RPR6.22 Advance Async Enhancement */ /* RPR6.23 USB Periodic Cache Setting */ dword = pci_read_config32(dev, 0x50); if (rev == REV_SB800_A12) { dword |= 1 << 28; /* 6.22 */ dword |= 1 << 27; /* 6.23 */ } else if (rev >= REV_SB800_A14) { dword |= 1 << 3; dword &= ~(1 << 28); /* 6.22 */ dword |= 1 << 8; dword &= ~(1 << 27); /* 6.23 */ } printk(BIOS_DEBUG, "rpr 6.23, final dword=%x\n", dword); #endif }
void init_timer(void) { write32(&exynos_mct->g_tcon, read32(&exynos_mct->g_tcon) | (0x1 << 8)); }
static inline void write_iosf_reg(int reg, uint32_t value) { write32((void *)(IOSF_PCI_BASE + reg), value); }
bool Mda32::write32(const QString& path) const { return write32(path.toLatin1().data()); }
static void set_clock_sources(void) { /* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */ write32(CLK_RST_REG(clk_src_uarta), PLLP << CLK_SOURCE_SHIFT); }
static void usb_xhci_reset_port_usb3(u8 *mem_base, int port) { u8 *portsc = mem_base + XHCI_USB3_PORTSC(port); write32(portsc, read32(portsc) | XHCI_USB3_PORTSC_WPR); }
U_CAPI void U_EXPORT2 writeAssemblyCode(const char *filename, const char *destdir, const char *optEntryPoint, const char *optFilename, char *outFilePath) { uint32_t column = MAX_COLUMN; char entry[64]; uint32_t buffer[1024]; char *bufferStr = (char *)buffer; FileStream *in, *out; size_t i, length; in=T_FileStream_open(filename, "rb"); if(in==NULL) { fprintf(stderr, "genccode: unable to open input file %s\n", filename); exit(U_FILE_ACCESS_ERROR); } getOutFilename(filename, destdir, bufferStr, entry, ".S", optFilename); out=T_FileStream_open(bufferStr, "w"); if(out==NULL) { fprintf(stderr, "genccode: unable to open output file %s\n", bufferStr); exit(U_FILE_ACCESS_ERROR); } if (outFilePath != NULL) { uprv_strcpy(outFilePath, bufferStr); } #if defined (WINDOWS_WITH_GNUC) && U_PLATFORM != U_PF_CYGWIN /* Need to fix the file separator character when using MinGW. */ swapFileSepChar(outFilePath, U_FILE_SEP_CHAR, '/'); #endif if(optEntryPoint != NULL) { uprv_strcpy(entry, optEntryPoint); uprv_strcat(entry, "_dat"); } /* turn dashes or dots in the entry name into underscores */ length=uprv_strlen(entry); for(i=0; i<length; ++i) { if(entry[i]=='-' || entry[i]=='.') { entry[i]='_'; } } sprintf(bufferStr, assemblyHeader[assemblyHeaderIndex].header, entry, entry, entry, entry, entry, entry, entry, entry); T_FileStream_writeLine(out, bufferStr); T_FileStream_writeLine(out, assemblyHeader[assemblyHeaderIndex].beginLine); for(;;) { length=T_FileStream_read(in, buffer, sizeof(buffer)); if(length==0) { break; } if (length != sizeof(buffer)) { /* pad with extra 0's when at the end of the file */ for(i=0; i < (length % sizeof(uint32_t)); ++i) { buffer[length+i] = 0; } } for(i=0; i<(length/sizeof(buffer[0])); i++) { column = write32(out, buffer[i], column); } } T_FileStream_writeLine(out, "\n"); sprintf(bufferStr, assemblyHeader[assemblyHeaderIndex].footer, entry, entry, entry, entry, entry, entry, entry, entry); T_FileStream_writeLine(out, bufferStr); if(T_FileStream_error(in)) { fprintf(stderr, "genccode: file read error while generating from file %s\n", filename); exit(U_FILE_ACCESS_ERROR); } if(T_FileStream_error(out)) { fprintf(stderr, "genccode: file write error while generating from file %s\n", filename); exit(U_FILE_ACCESS_ERROR); } T_FileStream_close(out); T_FileStream_close(in); }
/* Set D3Hot Power State in ACPI mode */ static void serialio_enable_d3hot(struct resource *res) { u32 reg32 = read32(res2mmio(res, PCH_PCS, 0)); reg32 |= PCH_PCS_PS_D3HOT; write32(res2mmio(res, PCH_PCS, 0), reg32); }
static void writeWord (git_sint32 word) { char buffer [4]; write32 (buffer, word); glk_put_buffer (buffer, 4); }
/* Enable clock in PCI mode */ static void serialio_enable_clock(struct resource *bar0) { u32 reg32 = read32(res2mmio(bar0, SIO_REG_PPR_CLOCK, 0)); reg32 |= SIO_REG_PPR_CLOCK_EN; write32(res2mmio(bar0, SIO_REG_PPR_CLOCK, 0), reg32); }
static inline void tegra_mipi_writel(struct tegra_mipi *mipi, unsigned long value, unsigned long reg) { write32(mipi->regs + (reg << 2), value); }
static void clock_reset_dev(u32 *setaddr, u32 *clraddr, u32 bit) { write32(setaddr, bit); udelay(LOGIC_STABILIZATION_DELAY); write32(clraddr, bit); }
static int rk_edp_link_train_cr(struct rk_edp *edp) { int clock_recovery; u8 voltage, tries = 0; u8 status[DP_LINK_STATUS_SIZE]; int i; u8 value; value = DP_TRAINING_PATTERN_1; write32(&edp->regs->dp_training_ptn_set, value); rk_edp_dpcd_write(edp, DPCD_TRAINING_PATTERN_SET, &value, 1); memset(edp->train_set, 0, 4); /* clock recovery loop */ clock_recovery = 0; tries = 0; voltage = 0xff; while (1) { rk_edp_set_link_training(edp, edp->train_set); rk_edp_dpcd_write(edp, DPCD_TRAINING_LANE0_SET, edp->train_set, edp->link_train.lane_count); mdelay(1); if (rk_edp_dpcd_read_link_status(edp, status) < 0) { printk(BIOS_ERR, "displayport link status failed\n"); break; } if (rk_edp_clock_recovery_ok(status, edp->link_train.lane_count)) { clock_recovery = 1; break; } for (i = 0; i < edp->link_train.lane_count; i++) { if ((edp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) break; } if (i == edp->link_train.lane_count) { printk(BIOS_ERR, "clock recovery reached max voltage\n"); break; } if ((edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { ++tries; if (tries == MAX_CR_LOOP) { printk(BIOS_ERR, "clock recovery tried 5 times\n"); break; } } else tries = 0; voltage = edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; /* Compute new train_set as requested by sink */ edp_get_adjust_train(status, edp->link_train.lane_count, edp->train_set); } if (!clock_recovery) { printk(BIOS_ERR, "clock recovery failed\n"); return -1; } else { printk(BIOS_DEBUG, "clock recovery at voltage %d pre-emphasis %d\n", edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, (edp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT); return 0; } }
void elog_add_watchdog_reset(void) { if (read32(_watchdog_tombstone) == WATCHDOG_TOMBSTONE_MAGIC) elog_add_event(ELOG_TYPE_ASYNC_HW_TIMER_EXPIRED); write32(_watchdog_tombstone, 0); }
void hard_reset(void) { /* Generate system reset */ write32(PISTACHIO_WD_ADDR + PISTACHIO_WD_SW_RST_OFFSET, 0x1); }
void reboot_from_watchdog(void) { printk(BIOS_INFO, "Last reset was watchdog, reboot again to reset TPM!\n"); write32(_watchdog_tombstone, WATCHDOG_TOMBSTONE_MAGIC); hard_reset(); }
void send(unsigned long cid, int mid, uint32_t content) { write32(MSIM_ORDER_MAILBOX_BASE+cid*MSIM_ORDER_MAILBOX_SIZE+mid*4, content); }
s32 DVDSelectGame( void ) { FIL BootInfo; char *str = (char *)malloca( 0x400, 32 ); if( ConfigGetConfig(DML_CFG_GAME_PATH) ) { sprintf( str, "%s", ConfigGetGamePath() ); } else { sprintf( str, "/games/boot.bin" ); switch( f_open( &BootInfo, str, FA_READ ) ) { case FR_OK: { char *Path = (char*)malloca( BootInfo.fsize, 32 ); f_read( &BootInfo, Path, BootInfo.fsize, &read ); f_close( &BootInfo ); f_unlink(str); // Delete the boot.bin, so retail discs can be loaded via the disc channel sprintf( str, "/games/%s/game.iso", Path ); free( Path ); } break; default: { dbgprintf("DIP:Couldn't open /games/boot.bin!\n"); return -1; } break; } } s32 fres = f_open( &GameFile, str, FA_READ ); if( fres != FR_OK ) { dbgprintf("Failed to open:\"%s\" fres:%d\n", str, fres ); return -2; } f_lseek( &GameFile, 0 ); f_read( &GameFile, (void*)0, 0x20, &read ); f_lseek( &GameFile, 0 ); f_read( &GameFile, str, 0x400, &read ); dbgprintf("DIP:Loading game %.6s: %s\n", str, (char *)(str+0x20)); f_lseek( &GameFile, 0x420 ); f_read( &GameFile, str, 0x40, &read ); #ifdef SPEEDTEST SpeedTest(); #endif GC_SRAM *sram = SRAM_Unlock(); dbgprintf("DIP:Region:%u\n", *(u32*)(str+0x38) ); dbgprintf("SRAM:Mode:%u(%u) EURGB60:%u Prog:%u\n", sram->Flags&3, read32(0xCC), !!(sram->BootMode&0x40), !!(sram->Flags&0x80) ); switch( ConfigGetVideMode() & 0xFFFF0000 ) { case DML_VID_FORCE: { if( ConfigGetVideMode() & DML_VID_FORCE_PAL50 ) SRAM_SetVideoMode( GCVideoModeNone ); if( ConfigGetVideMode() & DML_VID_FORCE_PAL60 ) SRAM_SetVideoMode( GCVideoModePAL60 ); if( ConfigGetVideMode() & DML_VID_FORCE_NTSC ) SRAM_SetVideoMode( GCVideoModeNTSC ); if( ConfigGetVideMode() & DML_VID_FORCE_PROG ) SRAM_SetVideoMode( GCVideoModePROG ); } break; case DML_VID_NONE: { } break; case DML_VID_DML_AUTO: default: { switch( *(u32*)(str+0x38) ) { default: case 0: // JAP case 1: // USA { switch( sram->Flags&3 ) { case 0: // NTSC { if( !(sram->Flags&0x80) ) // PROG flag SRAM_SetVideoMode( GCVideoModePROG ); } break; case 1: // PAL case 2: // MPAL { SRAM_SetVideoMode( GCVideoModeNTSC ); SRAM_SetVideoMode( GCVideoModePROG ); write32( 0x1312078, 0x60000000 ); write32( 0x1312070, 0x38000001 ); } break; default: { dbgprintf("SRAM:Invalid Video mode setting:%d\n", SRAM_GetVideoMode() ); } break; } } break; case 2: // EUR { switch( sram->Flags&3 ) { case 0: { SRAM_SetVideoMode( GCVideoModePAL60 ); SRAM_SetVideoMode( GCVideoModePROG ); write32( 0x1312078, 0x60000000 ); write32( 0x1312070, 0x38000001 ); } break; case 1: case 2: { if( !(sram->BootMode&0x40) ) // PAL60 flag if( !(sram->Flags&0x80) ) // PROG flag SRAM_SetVideoMode( GCVideoModePAL60 ); } break; default: { dbgprintf("SRAM:Invalid Video mode setting:%d\n", SRAM_GetVideoMode() ); } break; } } break; } } break; } SRAM_Flush(); dbgprintf("SRAM:Mode:%u(%u) EURGB60:%u Prog:%u\n", sram->Flags&3, read32(0xCC), !!(sram->BootMode&0x40), !!(sram->Flags&0x80) ); free( str ); return DI_SUCCESS; }
void gtt_write(u32 reg, u32 data) { write32(res2mmio(gtt_res, reg, 0), data); }
static void logger_init(struct logger_t * logger) { struct logger_pdata_t * pdat = (struct logger_pdata_t *)logger->priv; write32(pdat->virt + 0x30, (1 << 0) | (1 << 8) | (1 << 9)); }