/* Set clock divider for SDC peripheral */
void Chip_SDC_SetClockDiv(LPC_SDC_T *pSDC, uint8_t div)
{
uint32_t temp;
temp = (pSDC->CLOCK & (~SDC_CLOCK_CLKDIV_BITMASK));
pSDC->CLOCK = temp | (SDC_CLOCK_CLKDIV(div));
writeDelay();
}
/* Reset Command Info */
void IP_SDC_ResetCommand(IP_SDC_001_Type *pSDC)
{
pSDC->CLEAR = SDC_CLEAR_ALL;
pSDC->ARGUMENT = 0xFFFFFFFF;
pSDC->COMMAND = 0;
writeDelay();
}
/* Set Command Info */
void IP_SDC_SetCommand(IP_SDC_001_Type *pSDC, IP_SDC_001_CMD_Type *pCmd)
{
pSDC->CLEAR = SDC_CLEAR_ALL;/* Clear status register */
pSDC->ARGUMENT = pCmd->Argument; /* Set the argument first, finally command */
pSDC->COMMAND = SDC_COMMAND_INDEX(pCmd->CmdIndex) | pCmd->RespType | pCmd->Flag | SDC_COMMAND_ENABLE;
writeDelay();
}
/* Reset Command Info */
void Chip_SDC_ResetCommand(LPC_SDC_T *pSDC)
{
pSDC->CLEAR = SDC_CLEAR_ALL;
pSDC->ARGUMENT = 0xFFFFFFFF;
pSDC->COMMAND = 0;
writeDelay();
}
/* Clock control for SDC peripheral*/
void IP_SDC_ClockControl(IP_SDC_001_Type *pSDC, IP_SDC_001_CLOCK_CTRL_T ctrlType,
FunctionalState NewState)
{
if (NewState) {
pSDC->CLOCK |= (1 << ctrlType) & SDC_CLOCK_BITMASK;
}
else {
pSDC->CLOCK &= (~(1 << ctrlType)) & SDC_CLOCK_BITMASK;
}
writeDelay();
}
/* Clock control for SDC peripheral*/
void Chip_SDC_ClockControl(LPC_SDC_T *pSDC, SDC_CLOCK_CTRL_T ctrlType,
FunctionalState NewState)
{
if (NewState) {
pSDC->CLOCK |= (1 << ctrlType);
}
else {
pSDC->CLOCK &= (~(1 << ctrlType));
}
writeDelay();
}
/* Setup Data Transfer Information */
void IP_SDC_SetDataTransfer(IP_SDC_001_Type *pSDC, IP_SDC_001_DATA_TRANSFER_Type *pTransfer)
{
uint32_t DataCtrl = 0;
pSDC->DATATIMER = pTransfer->Timeout;
pSDC->DATALENGTH = pTransfer->BlockNum * SDC_DATACTRL_BLOCKSIZE_VAL(pTransfer->BlockSize);
DataCtrl = SDC_DATACTRL_ENABLE;
DataCtrl |= pTransfer->Dir | pTransfer->Mode | SDC_DATACTRL_BLOCKSIZE(pTransfer->BlockSize);
if (pTransfer->DMAUsed) {
DataCtrl |= SDC_DATACTRL_DMA_ENABLE;
}
pSDC->DATACTRL = DataCtrl;
writeDelay();
}
/* Set Command Info */
void Chip_SDC_SetCommand(LPC_SDC_T *pSDC, uint32_t Cmd, uint32_t Arg)
{
/* Clear status register */
pSDC->CLEAR = SDC_CLEAR_ALL;
/* Set the argument first, finally command */
pSDC->ARGUMENT = Arg;
/* Write command value, enable the command */
pSDC->COMMAND = Cmd | SDC_COMMAND_ENABLE;
writeDelay();
}
/* Setup Data Transfer Information */
void Chip_SDC_SetDataTransfer(LPC_SDC_T *pSDC, SDC_DATA_TRANSFER_T *pTransfer)
{
uint32_t DataCtrl = 0;
pSDC->DATATIMER = pTransfer->Timeout;
pSDC->DATALENGTH = pTransfer->BlockNum * SDC_DATACTRL_BLOCKSIZE_VAL(pTransfer->BlockSize);
DataCtrl = SDC_DATACTRL_ENABLE;
DataCtrl |= ((uint32_t) pTransfer->Dir) | ((uint32_t) pTransfer->Mode) | SDC_DATACTRL_BLOCKSIZE(
pTransfer->BlockSize);
if (pTransfer->DMAUsed) {
DataCtrl |= SDC_DATACTRL_DMA_ENABLE;
}
pSDC->DATACTRL = DataCtrl;
writeDelay();
}
/* Initialize SDC peripheral */
void IP_SDC_Init(IP_SDC_001_Type *pSDC)
{
/* Disable SD_CLK */
IP_SDC_ClockControl(pSDC, SDC_CLOCK_ENABLE, DISABLE);
/* Power-off */
IP_SDC_PowerControl(pSDC, SDC_POWER_OFF, 0);
writeDelay();
/* Disable all interrupts */
pSDC->MASK0 = 0;
/*Setting for timeout problem */
pSDC->DATATIMER = 0x1FFFFFFF;
pSDC->COMMAND = 0;
writeDelay();
pSDC->DATACTRL = 0;
writeDelay();
pSDC->CLEAR = SDC_CLEAR_ALL; /* clear all pending interrupts */
}
int PressSensor::set_delay(int64_t ns) {
return writeDelay(ns);
}
int AccelSensor::set_delay(int64_t ns) {
return writeDelay(ns);
}
/* Set clock divider for SDC peripheral */
void IP_SDC_SetClockDiv(IP_SDC_001_Type *pSDC, uint8_t div)
{
pSDC->CLOCK &= (~SDC_CLOCK_CLKDIV_BITMASK) & SDC_CLOCK_BITMASK;
pSDC->CLOCK |= SDC_CLOCK_CLKDIV(div);
writeDelay();
}
/* Set power status of SDC peripheral */
void IP_SDC_PowerControl(IP_SDC_001_Type *pSDC, IP_SDC_001_PWR_CTRL_T pwrMode, uint32_t flag)
{
pSDC->POWER = SDC_PWR_CTRL(pwrMode) | flag;
writeDelay();
}
/* Set power state of SDC peripheral */
void Chip_SDC_PowerControl(LPC_SDC_T *pSDC, SDC_PWR_CTRL_T pwrMode, uint32_t flag)
{
pSDC->POWER = SDC_PWR_CTRL(pwrMode) | flag;
writeDelay();
}
