__init void plat_time_init(void) { unsigned int configPR; unsigned int n; unsigned int m; unsigned int p; unsigned int pow2p; pnx8xxx_clockevent.cpumask = cpu_none_mask; clockevents_register_device(&pnx8xxx_clockevent); clocksource_register(&pnx_clocksource); /* Timer 1 start */ configPR = read_c0_config7(); configPR &= ~0x00000008; write_c0_config7(configPR); /* Timer 2 start */ configPR = read_c0_config7(); configPR &= ~0x00000010; write_c0_config7(configPR); /* Timer 3 stop */ configPR = read_c0_config7(); configPR |= 0x00000020; write_c0_config7(configPR); /* PLL0 sets MIPS clock (PLL1 <=> TM1, PLL6 <=> TM2, PLL5 <=> mem) */ /* (but only if CLK_MIPS_CTL select value [bits 3:1] is 1: FIXME) */ n = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_N_MASK) >> 16; m = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_M_MASK) >> 8; p = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_P_MASK) >> 2; pow2p = (1 << p); db_assert(m != 0 && pow2p != 0); /* * Compute the frequency as in the PNX8550 User Manual 1.0, p.186 * (a.k.a. 8-10). Divide by HZ for a timer offset that results in * HZ timer interrupts per second. */ mips_hpt_frequency = 27UL * ((1000000UL * n)/(m * pow2p)); cpj = (mips_hpt_frequency + HZ / 2) / HZ; write_c0_count(0); timer_ack(); /* Setup Timer 2 */ write_c0_count2(0); write_c0_compare2(0xffffffff); setup_irq(PNX8550_INT_TIMER1, &pnx8xxx_timer_irq); setup_irq(PNX8550_INT_TIMER2, &monotonic_irqaction); }
void __init board_setup(void) { unsigned long configpr; configpr = read_c0_config7(); configpr |= (1<<19); write_c0_config7(configpr); }
void __init plat_timer_setup(struct irqaction *irq) { int configPR; setup_irq(PNX8550_INT_TIMER1, irq); /* Start timer1 */ configPR = read_c0_config7(); configPR &= ~0x00000008; write_c0_config7(configPR); /* Timer 2 stop */ configPR = read_c0_config7(); configPR |= 0x00000010; write_c0_config7(configPR); write_c0_count2(0); write_c0_compare2(0xffffffff); /* Timer 3 stop */ configPR = read_c0_config7(); configPR |= 0x00000020; write_c0_config7(configPR); }
void __init board_setup(void) { unsigned long config0, configpr; config0 = read_c0_config(); /* clear all three cache coherency fields */ config0 &= ~(0x7 | (7<<25) | (7<<28)); config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) | (CONF_CM_DEFAULT<<28)); write_c0_config(config0); BARRIER; configpr = read_c0_config7(); configpr |= (1<<19); /* enable tlb */ write_c0_config7(configpr); BARRIER; }
int timer_init(void) { #ifdef CONFIG_MIPS_CPU_PR4450 unsigned int config7; /* enable and start counter */ config7 = read_c0_config7(); config7 &= ~0x00000008; write_c0_config7(config7); #endif // CONFIG_MIPS_CPU_PR4450 /* Set up the timer for the first expiration. */ timestamp = 0; write_c0_count(0); write_c0_compare(~0); return 0; }