static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) { struct mii_ioctl_data *data = if_mii(rq); struct am_net_private *np = netdev_priv(dev); char addr[MAX_ADDR_LEN]; if (debug > 0) printk("Ethernet Driver ioctl (%x) \n", cmd); switch (cmd) { case SIOCGMIIPHY: /* Get address of MII PHY in use. */ data->phy_id = ((struct am_net_private *)netdev_priv(dev))->phys[0] & 0x1f; /* Fall Through */ case SIOCGMIIREG: /* Read MII PHY register. */ spin_lock_irq(&np->lock); data->val_out = mdio_read(dev, data->phy_id & 0x1f, data->reg_num & 0x1f); spin_unlock_irq(&np->lock); return 0; case SIOCSMIIREG: /* Write MII PHY register. */ if (!capable(CAP_NET_ADMIN)) return -EPERM; spin_lock_irq(&np->lock); mdio_write(dev, data->phy_id & 0x1f, data->reg_num & 0x1f,data->val_in); spin_unlock_irq(&np->lock); return 0; case SIOCSIFHWADDR: if (copy_from_user(&addr, (void __user *)rq->ifr_hwaddr.sa_data, MAX_ADDR_LEN)) { return -EFAULT; } if (debug > 0) printk("set mac addr to %02x:%02x:%02x:%02x:%02x:%02x\n", addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); spin_lock_irq(&np->lock); memcpy(dev->dev_addr, &addr, MAX_ADDR_LEN); write_mac_addr(dev, addr); spin_unlock_irq(&np->lock); default: if (debug > 0) printk("Ethernet Driver unknow ioctl (%x) \n", cmd); return -EOPNOTSUPP; } return 0; }
static void init_rx(void) { int i; // Head should point to the first valid receive descriptor in the // descriptor ring and tail should point to one descriptor beyond // the last valid descriptor in the descriptor ring? e1000_mmio_beg[E1000_RDH] = 0; e1000_mmio_beg[E1000_RDT] = RX_NUM_OF_DESC - 1; e1000_mmio_beg[E1000_RDBAL] = PADDR(&rx_desc_lst); e1000_mmio_beg[E1000_RDBAH] = 0; e1000_mmio_beg[E1000_RDLEN] = sizeof(rx_desc_lst); e1000_mmio_beg[E1000_RAH0] = 0; e1000_mmio_beg[E1000_RAL0] = 0; write_mac_addr(); // address valid e1000_mmio_beg[E1000_RAH0] |= E1000_RAH_AV; // interrupt mask set e1000_mmio_beg[E1000_IMS] |= E1000_IMS_RXT0; /* e1000_mmio_beg[E1000_IMS] |= E1000_IMS_RXO; */ /* e1000_mmio_beg[E1000_IMS] |= E1000_IMS_RXSEQ; */ // long packet enable e1000_mmio_beg[E1000_RCTL] &= ~E1000_RCTL_LPE; // loppback mode e1000_mmio_beg[E1000_RCTL] |= E1000_RCTL_LBM_NO; // broadcast accept mode e1000_mmio_beg[E1000_RCTL] |= E1000_RCTL_BAM; // buffer size extended e1000_mmio_beg[E1000_RCTL] &= ~E1000_RCTL_BSEX; e1000_mmio_beg[E1000_RCTL] |= E1000_RCTL_SZ_4096; // strip ethernet crc e1000_mmio_beg[E1000_RCTL] |= E1000_RCTL_SECRC; // receiver enable e1000_mmio_beg[E1000_RCTL] |= E1000_RCTL_EN; // multicast table array /* for (i = 0; i < 128; i++) */ /* e1000_mmio_beg[E1000_MTA + (i * 4)] = 0; */ for (i = 0; i < RX_NUM_OF_DESC; i++) rx_desc_lst[i].addr = PADDR(rx_pkt_buffer_lst[i]); }