void set_misc_enable(int package, struct misc_enable *s)
{
uint64_t msrVal;
read_msr_by_coord(package, 0, 0, IA32_MISC_ENABLE, &msrVal);
//msrVal = 64; //temp value
assert(s->fast_string_enable == 0 || s->fast_string_enable == 1);
assert(s->auto_TCC_enable == 0 || s->auto_TCC_enable == 1);
assert(s->TM2_enable == 0 || s->TM2_enable == 1);
assert(s->enhanced_Intel_SpeedStep_Tech_enable == 0 || s->enhanced_Intel_SpeedStep_Tech_enable == 1);
assert(s->limit_CPUID_maxval == 0 || s->limit_CPUID_maxval == 1);
assert(s->xTPR_message_disable == 0 || s->xTPR_message_disable == 1);
assert(s->XD_bit_disable == 0 || s->XD_bit_disable == 1);
assert(s->turbo_mode_disable == 0 || s->turbo_mode_disable == 1);
msrVal = (msrVal & (~(1<< 0))) | (s->fast_string_enable << 0);
msrVal = (msrVal & (~(1<< 3))) | (s->auto_TCC_enable << 3);
msrVal = (msrVal & (~(1<< 13))) | (s->TM2_enable << 13);
msrVal = (msrVal & (~(1<< 16))) | (s->enhanced_Intel_SpeedStep_Tech_enable << 16);
msrVal = (msrVal & (~(1<< 22))) | (s->limit_CPUID_maxval << 22);
msrVal = (msrVal & (~(1<< 23))) | (s->xTPR_message_disable << 23);
msrVal = (msrVal & (~((uint64_t)1<< (uint64_t)34))) | ((uint64_t)s->XD_bit_disable << (uint64_t)34);
msrVal = (msrVal & (~((uint64_t)1<< (uint64_t)38))) | ((uint64_t)s->turbo_mode_disable << (uint64_t)38);
write_msr_by_coord(package, 0, 0, IA32_MISC_ENABLE, msrVal);
}
int set_clock_mod(int socket, int core, struct clock_mod *s)
{
uint64_t msrVal;
read_msr_by_coord(socket, core, 0, IA32_CLOCK_MODULATION, &msrVal);
//msrVal = 64; // temp value
// replaced asserts with these two conditionals
if (!(s->duty_cycle > 0 && s->duty_cycle < 8))
{
return -1;
}
if (!(s->duty_cycle_enable == 0 || s->duty_cycle_enable == 1))
{
return -1;
}
msrVal = (msrVal & (~(3<<1))) | (s->duty_cycle << 1);
msrVal = (msrVal & (~(1<<4))) | (s->duty_cycle_enable << 4);
write_msr_by_coord(socket, core, 0, IA32_CLOCK_MODULATION, msrVal);
return 0;
}
int set_dram_rapl_limit(const unsigned socket, struct rapl_limit *limit)
{
uint64_t dram_limit = 0;
static uint64_t *rapl_flags = NULL;
sockets_assert(&socket, __LINE__, __FILE__);
if (rapl_flags == NULL)
{
if (rapl_storage(NULL, &rapl_flags))
{
return -1;
}
}
#ifdef LIBMSR_DEBUG
fprintf(stderr, "%s %s::%d DEBUG: (set_dram_rapl_limit)\n", getenv("HOSTNAME"), __FILE__, __LINE__);
#endif
/* Make sure the dram power limit register exists. */
if (*rapl_flags & DRAM_POWER_LIMIT)
{
if (limit != NULL)
{
if (calc_std_rapl_limit(socket, limit))
{
return -1;
}
dram_limit |= limit->bits | (1LL << 15);
write_msr_by_coord(socket, 0, 0, MSR_DRAM_POWER_LIMIT, dram_limit);
}
}
else
{
libmsr_error_handler("set_dram_rapl_limit(): DRAM domain RAPL limit not supported on this architecture", LIBMSR_ERROR_PLATFORM_NOT_SUPPORTED, getenv("HOSTNAME"), __FILE__, __LINE__);
return -1;
}
return 0;
}
int set_pkg_rapl_limit(const unsigned socket, struct rapl_limit *limit1, struct rapl_limit *limit2)
{
uint64_t pkg_limit = 0;
static uint64_t *rapl_flags = NULL;
uint64_t currentval = 0;
int ret = 0;
sockets_assert(&socket, __LINE__, __FILE__);
if (rapl_flags == NULL)
{
if (rapl_storage(NULL, &rapl_flags))
{
return -1;
}
}
#ifdef LIBMSR_DEBUG
fprintf(stderr, "%s %s::%d DEBUG: (set_pkg_rapl_limit) flags are at %p\n", getenv("HOSTNAME"), __FILE__, __LINE__, rapl_flags);
#endif
/* Make sure the pkg power limit register exists. */
if (*rapl_flags & PKG_POWER_LIMIT)
{
/* If there is only one limit, grab the other existing one. */
if (limit1 == NULL)
{
#ifdef LIBMSR_DEBUG
fprintf(stderr, "%s %s::%d DEBUG: only one rapl limit, retrieving any existing power limits\n", getenv("HOSTNAME"), __FILE__, __LINE__);
#endif
ret = read_msr_by_coord(socket, 0, 0, MSR_PKG_POWER_LIMIT, ¤tval);
/* We want to keep the lower limit so mask off all other bits. */
pkg_limit |= currentval & 0x00000000FFFFFFFF;
}
else if (limit2 == NULL)
{
#ifdef LIBMSR_DEBUG
fprintf(stderr, "%s %s::%d DEBUG: only one rapl limit, retrieving any existing power limits\n", getenv("HOSTNAME"), __FILE__, __LINE__);
#endif
ret = read_msr_by_coord(socket, 0, 0, MSR_PKG_POWER_LIMIT, ¤tval);
/* We want to keep the upper limit so mask off all other bits. */
pkg_limit |= currentval & 0xFFFFFFFF00000000;
}
if (calc_pkg_rapl_limit(socket, limit1, limit2))
{
return -1;
}
/* Enable the rapl limit (15 && 47) and turn on clamping (16 && 48). */
if (limit1 != NULL)
{
pkg_limit |= limit1->bits | (1LL << 15) | (1LL << 16);
}
if (limit2 != NULL)
{
pkg_limit |= limit2->bits | (1LL << 47) | (1LL << 48);
}
if (limit1 != NULL || limit2 != NULL)
{
ret += write_msr_by_coord(socket, 0, 0, MSR_PKG_POWER_LIMIT, pkg_limit);
}
}
else
{
libmsr_error_handler("set_pkg_rapl_limit(): PKG domain RAPL limit not supported on this architecture", LIBMSR_ERROR_PLATFORM_NOT_SUPPORTED, getenv("HOSTNAME"), __FILE__, __LINE__);
return -1;
}
#ifdef LIBMSR_DEBUG
fprintf(stderr, "pkg set\n");
#endif
return ret;
}