void OemAgesaSaveMtrr(void)
{
#ifndef __PRE_RAM__
msr_t msr_data;
u32 nvram_pos = S3_DATA_MTRR_POS;
u32 i;
struct spi_flash *flash;
if (!check_saved_mtrr_data(nvram_pos))
return;
spi_init();
flash = spi_flash_probe(0, 0, 0, 0);
if (!flash) {
printk(BIOS_DEBUG, "Could not find SPI device\n");
return;
}
flash->spi->rw = SPI_WRITE_FLAG;
spi_claim_bus(flash->spi);
flash->erase(flash, S3_DATA_MTRR_POS, S3_DATA_MTRR_SIZE);
/* Enable access to AMD RdDram and WrDram extension bits */
msr_data = rdmsr(SYS_CFG);
msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn;
wrmsr(SYS_CFG, msr_data);
/* Fixed MTRRs */
for (i = 0; i < (u32)sizeof(mtrr_table_fixed_MTRR)/sizeof(u32); i++)
write_mtrr(flash, &nvram_pos, mtrr_table_fixed_MTRR[i]);
/* Disable access to AMD RdDram and WrDram extension bits */
msr_data = rdmsr(SYS_CFG);
msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
wrmsr(SYS_CFG, msr_data);
/* Variable MTRRs, SYS_CFG, TOM, TOM2 */
for (i = 0; i < (u32)sizeof(mtrr_table_var_MTRR)/sizeof(u32); i++)
write_mtrr(flash, &nvram_pos, mtrr_table_var_MTRR[i]);
flash->spi->rw = SPI_WRITE_FLAG;
spi_release_bus(flash->spi);
#endif
}
void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size)
{
u8 *nvram_pos = mtrr_store;
msr_t msr_data;
u32 i;
/* Enable access to AMD RdDram and WrDram extension bits */
msr_data = rdmsr(SYSCFG_MSR);
msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn;
wrmsr(SYSCFG_MSR, msr_data);
/* Fixed MTRRs */
write_mtrr(&nvram_pos, 0x250);
write_mtrr(&nvram_pos, 0x258);
write_mtrr(&nvram_pos, 0x259);
for (i = 0x268; i < 0x270; i++)
write_mtrr(&nvram_pos, i);
/* Disable access to AMD RdDram and WrDram extension bits */
msr_data = rdmsr(SYSCFG_MSR);
msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
wrmsr(SYSCFG_MSR, msr_data);
/* Variable MTRRs */
for (i = 0x200; i < 0x210; i++)
write_mtrr(&nvram_pos, i);
/* SYSCFG_MSR */
write_mtrr(&nvram_pos, SYSCFG_MSR);
/* TOM */
write_mtrr(&nvram_pos, 0xC001001A);
/* TOM2 */
write_mtrr(&nvram_pos, 0xC001001D);
*mtrr_store_size = nvram_pos - (u8*) mtrr_store;
}
