void iop13xx_restart(enum reboot_mode mode, const char *cmd)
{
/*
* Reset the internal bus (warning both cores are reset)
*/
write_wdtcr(IOP_WDTCR_EN_ARM);
write_wdtcr(IOP_WDTCR_EN);
write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
write_wdtcr(0x1000);
}
void iop13xx_restart(char mode, const char *cmd)
{
/*
*/
write_wdtcr(IOP_WDTCR_EN_ARM);
write_wdtcr(IOP_WDTCR_EN);
write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
write_wdtcr(0x1000);
}
static int __init iop_wdt_init(void)
{
int ret;
boot_status = (read_rcsr() & IOP_RCSR_WDT) ? WDIOF_CARDRESET : 0;
write_wdtsr(IOP13XX_WDTCR_IB_RESET);
ret = misc_register(&iop_wdt_miscdev);
if (ret == 0)
pr_info("timeout %lu sec\n", iop_watchdog_timeout());
return ret;
}
static int __init iop_wdt_init(void)
{
int ret;
ret = misc_register(&iop_wdt_miscdev);
if (ret == 0)
printk("iop watchdog timer: timeout %lu sec\n",
iop_watchdog_timeout());
/* check if the reset was caused by the watchdog timer */
boot_status = (read_rcsr() & IOP_RCSR_WDT) ? WDIOF_CARDRESET : 0;
/* Configure Watchdog Timeout to cause an Internal Bus (IB) Reset
* NOTE: An IB Reset will Reset both cores in the IOP342
*/
write_wdtsr(IOP13XX_WDTCR_IB_RESET);
return ret;
}
static int __init iop_wdt_init(void)
{
int ret;
spin_lock_init(&wdt_lock);
/* check if the reset was caused by the watchdog timer */
boot_status = (read_rcsr() & IOP_RCSR_WDT) ? WDIOF_CARDRESET : 0;
/* Configure Watchdog Timeout to cause an Internal Bus (IB) Reset
* NOTE: An IB Reset will Reset both cores in the IOP342
*/
write_wdtsr(IOP13XX_WDTCR_IB_RESET);
/* Register after we have the device set up so we cannot race
with an open */
ret = misc_register(&iop_wdt_miscdev);
if (ret == 0)
printk(KERN_INFO "iop watchdog timer: timeout %lu sec\n",
iop_watchdog_timeout());
return ret;
}
