static void msm_ssusb_qmp_enable_autonomous(struct msm_ssphy_qmp *phy) { u8 val; dev_info(phy->phy.dev, "enabling QMP autonomous mode with cable %s\n", get_cable_status_str(phy)); writeb_relaxed(1, phy->base + PCIE_USB3_PHY_LFPS_RXTERM_IRQ_CLEAR); wmb(); writeb_relaxed(0, phy->base + PCIE_USB3_PHY_LFPS_RXTERM_IRQ_CLEAR); val = readb_relaxed(phy->base + PCIE_USB3_PHY_AUTONOMOUS_MODE_CTRL); val |= ARCVR_DTCT_EN; if (phy->cable_connected) { val |= ALFPS_DTCT_EN; val &= ~ARCVR_DTCT_EVENT_SEL; } else { val &= ~ALFPS_DTCT_EN; val |= ARCVR_DTCT_EVENT_SEL; } writeb_relaxed(val, phy->base + PCIE_USB3_PHY_AUTONOMOUS_MODE_CTRL); }
static void msm_ssusb_qmp_enable_autonomous(struct msm_ssphy_qmp *phy) { u8 val; dev_dbg(phy->phy.dev, "enabling QMP autonomous mode with cable %s\n", get_cable_status_str(phy)); /* clear LFPS RXTERM interrupt */ writeb_relaxed(1, phy->base + PCIE_USB3_PHY_LFPS_RXTERM_IRQ_CLEAR); /* flush the previous write before next write */ wmb(); writeb_relaxed(0, phy->base + PCIE_USB3_PHY_LFPS_RXTERM_IRQ_CLEAR); val = readb_relaxed(phy->base + PCIE_USB3_PHY_AUTONOMOUS_MODE_CTRL); val |= ARCVR_DTCT_EN; if (phy->cable_connected) { val |= ALFPS_DTCT_EN; /* Detect detach */ val &= ~ARCVR_DTCT_EVENT_SEL; } else { val &= ~ALFPS_DTCT_EN; /* Detect attach */ val |= ARCVR_DTCT_EVENT_SEL; } writeb_relaxed(val, phy->base + PCIE_USB3_PHY_AUTONOMOUS_MODE_CTRL); }
static void config_pcm_i2s_mode(int mode) { void __iomem *cfg_ptr; u8 reg2; cfg_ptr = ioremap_nocache(FPGA_MSM_CNTRL_REG2, sizeof(char)); if (!cfg_ptr) return; if (mode) { /*enable the pcm mode in FPGA*/ reg2 = readb_relaxed(cfg_ptr); if (reg2 == 0) { reg2 = 1; writeb_relaxed(reg2, cfg_ptr); } } else { /*enable i2s mode in FPGA*/ reg2 = readb_relaxed(cfg_ptr); if (reg2 == 1) { reg2 = 0; writeb_relaxed(reg2, cfg_ptr); } } iounmap(cfg_ptr); }
static void digicolor_uart_set_termios(struct uart_port *port, struct ktermios *termios, struct ktermios *old) { unsigned int baud, divisor; u8 config = 0; unsigned long flags; /* Mask termios capabilities we don't support */ termios->c_cflag &= ~CMSPAR; termios->c_iflag &= ~(BRKINT | IGNBRK); /* Limit baud rates so that we don't need the fractional divider */ baud = uart_get_baud_rate(port, termios, old, port->uartclk / (0x10000*16), port->uartclk / 256); divisor = uart_get_divisor(port, baud) - 1; switch (termios->c_cflag & CSIZE) { case CS7: break; case CS8: default: config |= UA_CONFIG_CHAR_LEN; break; } if (termios->c_cflag & CSTOPB) config |= UA_CONFIG_STOP_BITS; if (termios->c_cflag & PARENB) { config |= UA_CONFIG_PARITY; if (termios->c_cflag & PARODD) config |= UA_CONFIG_ODD_PARITY; } /* Set read status mask */ port->read_status_mask = UA_STATUS_OVERRUN_ERR; if (termios->c_iflag & INPCK) port->read_status_mask |= UA_STATUS_PARITY_ERR | UA_STATUS_FRAME_ERR; /* Set status ignore mask */ port->ignore_status_mask = 0; if (!(termios->c_cflag & CREAD)) port->ignore_status_mask |= UA_STATUS_OVERRUN_ERR | UA_STATUS_PARITY_ERR | UA_STATUS_FRAME_ERR; spin_lock_irqsave(&port->lock, flags); uart_update_timeout(port, termios->c_cflag, baud); writeb_relaxed(config, port->membase + UA_CONFIG); writeb_relaxed(divisor & 0xff, port->membase + UA_HBAUD_LO); writeb_relaxed(divisor >> 8, port->membase + UA_HBAUD_HI); spin_unlock_irqrestore(&port->lock, flags); }
static int miphy365x_init_pcie_port(struct miphy365x_phy *miphy_phy, struct miphy365x_dev *miphy_dev) { u8 val; if (miphy_phy->pcie_tx_pol_inv) { /* Invert Tx polarity and clear pci_txdetect_pol bit */ val = TERM_EN | PCI_EN | DES_BIT_LOCK_EN | TX_POL; writeb_relaxed(val, miphy_phy->base + CTRL_REG); writeb_relaxed(0x00, miphy_phy->base + PCIE_REG); } return 0; }
static void ep93xx_gpio_update_int_params(unsigned port) { BUG_ON(port > 2); writeb_relaxed(0, EP93XX_GPIO_REG(int_en_register_offset[port])); writeb_relaxed(gpio_int_type2[port], EP93XX_GPIO_REG(int_type2_register_offset[port])); writeb_relaxed(gpio_int_type1[port], EP93XX_GPIO_REG(int_type1_register_offset[port])); writeb(gpio_int_unmasked[port] & gpio_int_enabled[port], EP93XX_GPIO_REG(int_en_register_offset[port])); }
static void digicolor_uart_stop_tx(struct uart_port *port) { u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); int_enable &= ~UA_INT_TX; writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); }
static void digicolor_uart_console_putchar(struct uart_port *port, int ch) { while (digicolor_uart_tx_full(port)) cpu_relax(); writeb_relaxed(ch, port->membase + UA_EMI_REC); }
static void neponset_set_mctrl(struct uart_port *port, u_int mctrl) { void __iomem *base = nep_base; u_int mdm_ctl0; if (!base) return; mdm_ctl0 = readb_relaxed(base + MDM_CTL_0); if (port->mapbase == _Ser1UTCR0) { if (mctrl & TIOCM_RTS) mdm_ctl0 &= ~MDM_CTL0_RTS2; else mdm_ctl0 |= MDM_CTL0_RTS2; if (mctrl & TIOCM_DTR) mdm_ctl0 &= ~MDM_CTL0_DTR2; else mdm_ctl0 |= MDM_CTL0_DTR2; } else if (port->mapbase == _Ser3UTCR0) { if (mctrl & TIOCM_RTS) mdm_ctl0 &= ~MDM_CTL0_RTS1; else mdm_ctl0 |= MDM_CTL0_RTS1; if (mctrl & TIOCM_DTR) mdm_ctl0 &= ~MDM_CTL0_DTR1; else mdm_ctl0 |= MDM_CTL0_DTR1; } writeb_relaxed(mdm_ctl0, base + MDM_CTL_0); }
static int cpc_write(struct cpc_reg *reg, u64 val) { int ret_val = 0; if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) { void __iomem *vaddr = GET_PCC_VADDR(reg->address); switch (reg->bit_width) { case 8: writeb_relaxed(val, vaddr); break; case 16: writew_relaxed(val, vaddr); break; case 32: writel_relaxed(val, vaddr); break; case 64: writeq_relaxed(val, vaddr); break; default: pr_debug("Error: Cannot write %u bit width to PCC\n", reg->bit_width); ret_val = -EFAULT; break; } } else ret_val = acpi_os_write_memory((acpi_physical_address)reg->address, val, reg->bit_width); return ret_val; }
static void stm_send(void __iomem *addr, const void *data, u32 size, u8 write_bytes) { u8 paload[8]; if (stm_addr_unaligned(data, write_bytes)) { memcpy(paload, data, size); data = paload; } /* now we are 64bit/32bit aligned */ switch (size) { #ifdef CONFIG_64BIT case 8: writeq_relaxed(*(u64 *)data, addr); break; #endif case 4: writel_relaxed(*(u32 *)data, addr); break; case 2: writew_relaxed(*(u16 *)data, addr); break; case 1: writeb_relaxed(*(u8 *)data, addr); break; default: break; } }
static void digicolor_uart_shutdown(struct uart_port *port) { struct digicolor_port *dp = container_of(port, struct digicolor_port, port); writeb_relaxed(0, port->membase + UA_ENABLE); cancel_delayed_work_sync(&dp->rx_poll_work); }
/* This function may sleep*/ static void sdhci_msm_writeb(struct sdhci_host *host, u8 val, int reg) { u32 req_type = 0; req_type = __sdhci_msm_check_write(host, val, reg); writeb_relaxed(val, host->ioaddr + reg); if (req_type) sdhci_msm_check_power_status(host, req_type); }
static irqreturn_t dc_i2c_irq(int irq, void *dev_id) { struct dc_i2c *i2c = dev_id; int cmd_status = dc_i2c_cmd_status(i2c); unsigned long flags; u8 addr_cmd; writeb_relaxed(1, i2c->regs + II_INTFLAG_CLEAR); spin_lock_irqsave(&i2c->lock, flags); if (cmd_status == II_CMD_STATUS_ACK_BAD || cmd_status == II_CMD_STATUS_ABORT) { i2c->error = -EIO; complete(&i2c->done); goto out; } switch (i2c->state) { case STATE_START: addr_cmd = dc_i2c_addr_cmd(i2c->msg); dc_i2c_write_byte(i2c, addr_cmd); i2c->state = STATE_ADDR; break; case STATE_ADDR: if (i2c->msg->flags & I2C_M_RD) { dc_i2c_next_read(i2c); i2c->state = STATE_READ; break; } i2c->state = STATE_WRITE; /* fall through */ case STATE_WRITE: if (i2c->msgbuf_ptr < i2c->msg->len) dc_i2c_write_buf(i2c); else dc_i2c_stop(i2c); break; case STATE_READ: if (i2c->msgbuf_ptr < i2c->msg->len) dc_i2c_read_buf(i2c); else dc_i2c_stop(i2c); break; case STATE_STOP: i2c->state = STATE_IDLE; complete(&i2c->done); break; } out: spin_unlock_irqrestore(&i2c->lock, flags); return IRQ_HANDLED; }
static void sdhci_sprd_hw_reset(struct sdhci_host *host) { int val; /* * Note: don't use sdhci_writeb() API here since it is redirected to * sdhci_sprd_writeb() in which we have a workaround for * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can * not be cleared. */ val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET); val &= ~SDHCI_HW_RESET_CARD; writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); /* wait for 10 us */ usleep_range(10, 20); val |= SDHCI_HW_RESET_CARD; writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); usleep_range(300, 500); }
static int dc_i2c_init_hw(struct dc_i2c *i2c) { unsigned long clk_rate = clk_get_rate(i2c->clk); unsigned int clocktime; writeb_relaxed(II_CONTROL_LOCAL_RESET, i2c->regs + II_CONTROL); udelay(100); writeb_relaxed(0, i2c->regs + II_CONTROL); udelay(100); clocktime = DIV_ROUND_UP(clk_rate, 64 * i2c->frequency); if (clocktime < 1 || clocktime > 0xff) { dev_err(i2c->dev, "can't set bus speed of %u Hz\n", i2c->frequency); return -EINVAL; } writeb_relaxed(clocktime - 1, i2c->regs + II_CLOCKTIME); return 0; }
static void digicolor_rx_poll(struct work_struct *work) { struct digicolor_port *dp = container_of(to_delayed_work(work), struct digicolor_port, rx_poll_work); if (!digicolor_uart_rx_empty(&dp->port)) /* force RX interrupt */ writeb_relaxed(UA_INT_RX, dp->port.membase + UA_INTFLAG_SET); schedule_delayed_work(&dp->rx_poll_work, msecs_to_jiffies(100)); }
static inline void miphy365x_set_comp(struct miphy365x_phy *miphy_phy, struct miphy365x_dev *miphy_dev) { u8 val, mask; if (miphy_phy->sata_gen == SATA_GEN1) writeb_relaxed(COMP_2MHZ_RAT_GEN1, miphy_phy->base + COMP_CTRL2_REG); else writeb_relaxed(COMP_2MHZ_RAT, miphy_phy->base + COMP_CTRL2_REG); if (miphy_phy->sata_gen != SATA_GEN3) { writeb_relaxed(COMSR_COMP_REF, miphy_phy->base + COMP_CTRL3_REG); /* * Force VCO current to value defined by address 0x5A * and disable PCIe100Mref bit * Enable auto load compensation for pll_i_bias */ writeb_relaxed(BYPASS_PLL_CAL, miphy_phy->base + PLL_CTRL2_REG); writeb_relaxed(COMZC_IDLL, miphy_phy->base + COMP_IDLL_REG); } /* * Force restart compensation and enable auto load * for Comzc_Tx, Comzc_Rx and Comsr on macro */ val = START_COMSR | START_COMZC | COMP_AUTO_LOAD; writeb_relaxed(val, miphy_phy->base + COMP_CTRL1_REG); mask = COMSR_DONE | COMZC_DONE; while ((readb_relaxed(miphy_phy->base + COMP_CTRL1_REG) & mask) != mask) cpu_relax(); }
static inline void miphy365x_set_ssc(struct miphy365x_phy *miphy_phy, struct miphy365x_dev *miphy_dev) { u8 val; /* * SSC Settings. SSC will be enabled through Link * SSC Ampl. = 0.4% * SSC Freq = 31KHz */ writeb_relaxed(PLL_SSC_STEP_MSB_VAL, miphy_phy->base + PLL_SSC_STEP_MSB_REG); writeb_relaxed(PLL_SSC_STEP_LSB_VAL, miphy_phy->base + PLL_SSC_STEP_LSB_REG); writeb_relaxed(PLL_SSC_PER_MSB_VAL, miphy_phy->base + PLL_SSC_PER_MSB_REG); writeb_relaxed(PLL_SSC_PER_LSB_VAL, miphy_phy->base + PLL_SSC_PER_LSB_REG); /* SSC Settings complete */ if (miphy_phy->sata_gen == SATA_GEN1) { val = PLL_START_CAL | BUF_EN | SYNCHRO_TX | CONFIG_PLL; writeb_relaxed(val, miphy_phy->base + PLL_CTRL1_REG); } else { val = SSC_EN | PLL_START_CAL | BUF_EN | SYNCHRO_TX | CONFIG_PLL; writeb_relaxed(val, miphy_phy->base + PLL_CTRL1_REG); } }
/* * Set the executing CPUs power mode as defined. This will be in * preparation for it executing a WFI instruction. * * This function must be called with preemption disabled, and as it * has the side effect of disabling coherency, caches must have been * flushed. Interrupts must also have been disabled. */ int scu_power_mode(void __iomem *scu_base, unsigned int mode) { unsigned int val; int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0); if (mode > 3 || mode == 1 || cpu > 3) return -EINVAL; val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu) & ~0x03; val |= mode; writeb_relaxed(val, scu_base + SCU_CPU_STATUS + cpu); return 0; }
static irqreturn_t digicolor_uart_int(int irq, void *dev_id) { struct uart_port *port = dev_id; u8 int_status = readb_relaxed(port->membase + UA_INT_STATUS); writeb_relaxed(UA_INT_RX | UA_INT_TX, port->membase + UA_INTFLAG_CLEAR); if (int_status & UA_INT_RX) digicolor_uart_rx(port); if (int_status & UA_INT_TX) digicolor_uart_tx(port); return IRQ_HANDLED; }
void neponset_ncr_frob(unsigned int mask, unsigned int val) { void __iomem *base = nep_base; if (base) { unsigned long flags; unsigned v; local_irq_save(flags); v = readb_relaxed(base + NCR_0); writeb_relaxed((v & ~mask) | val, base + NCR_0); local_irq_restore(flags); } else { WARN(1, "nep_base unset\n"); } }
static int dc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) { struct dc_pinmap *pmap = gpiochip_get_data(chip); int reg_off = GP_DRIVE0(gpio/PINS_PER_COLLECTION); int bit_off = gpio % PINS_PER_COLLECTION; u8 drive; unsigned long flags; spin_lock_irqsave(&pmap->lock, flags); drive = readb_relaxed(pmap->regs + reg_off); drive &= ~BIT(bit_off); writeb_relaxed(drive, pmap->regs + reg_off); spin_unlock_irqrestore(&pmap->lock, flags); return 0; }
static int dc_set_mux(struct pinctrl_dev *pctldev, unsigned selector, unsigned group) { struct dc_pinmap *pmap = pinctrl_dev_get_drvdata(pctldev); int bit_off, reg_off; u8 reg; dc_client_sel(group, ®_off, &bit_off); reg = readb_relaxed(pmap->regs + reg_off); reg &= ~(3 << bit_off); reg |= (selector << bit_off); writeb_relaxed(reg, pmap->regs + reg_off); return 0; }
/* * Set the executing CPUs power mode as defined. This will be in * preparation for it executing a WFI instruction. * * This function must be called with preemption disabled, and as it * has the side effect of disabling coherency, caches must have been * flushed. Interrupts must also have been disabled. */ int scu_set_power_mode(unsigned int mode) { int cpu; if (!scu_base) return -ENODEV; if (mode > 3 || mode == 1) return -EINVAL; cpu = get_cpu(); writeb_relaxed(mode, scu_base + SCU_POWER_STATUS_OFFSET + cpu); put_cpu(); return 0; }
static void dc_gpio_set(struct gpio_chip *chip, unsigned gpio, int value) { struct dc_pinmap *pmap = gpiochip_get_data(chip); int reg_off = GP_OUTPUT0(gpio/PINS_PER_COLLECTION); int bit_off = gpio % PINS_PER_COLLECTION; u8 output; unsigned long flags; spin_lock_irqsave(&pmap->lock, flags); output = readb_relaxed(pmap->regs + reg_off); if (value) output |= BIT(bit_off); else output &= ~BIT(bit_off); writeb_relaxed(output, pmap->regs + reg_off); spin_unlock_irqrestore(&pmap->lock, flags); }
static void at91_twi_write_next_byte(struct at91_twi_dev *dev) { if (!dev->buf_len) return; /* 8bit write works with and without FIFO */ writeb_relaxed(*dev->buf, dev->base + AT91_TWI_THR); /* send stop when last byte has been written */ if (--dev->buf_len == 0) if (!dev->use_alt_cmd) at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP); dev_dbg(dev->dev, "wrote 0x%x, to go %zu\n", *dev->buf, dev->buf_len); ++dev->buf; }
static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg) { /* * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the * standard specification, sdhci_reset() write this register directly * without checking other reserved bits, that will clear BIT(3) which * is defined as hardware reset on Spreadtrum's platform and clearing * it by mistake will lead the card not work. So here we need to work * around it. */ if (unlikely(reg == SDHCI_SOFTWARE_RESET)) { if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD) val |= SDHCI_HW_RESET_CARD; } writeb_relaxed(val, host->ioaddr + reg); }
void rk_fiq_init(void) { unsigned int gic_irqs, i; // read gic info to know how many irqs in our chip gic_irqs = readl_relaxed(GIC_DIST_BASE + GIC_DIST_CTR) & 0x1f; // set all the interrupt to non-secure state for (i = 0; i < (gic_irqs + 1); i++) { writel_relaxed(0xffffffff, GIC_DIST_BASE + GIC_DIST_SECURITY + (i<<2)); } dsb(); writel_relaxed(0x3, GIC_DIST_BASE + GIC_DIST_CTRL); writel_relaxed(0x0f, GIC_CPU_BASE + GIC_CPU_CTRL); #ifdef IRQ_DEBUG_UART // set the debug uart priority a little higher than other interrupts (normal is 0xa0) writeb_relaxed(0x90, GIC_DIST_BASE + GIC_DIST_PRI + IRQ_DEBUG_UART); #endif dsb(); }
static int dc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value) { struct dc_pinmap *pmap = container_of(chip, struct dc_pinmap, chip); int reg_off = GP_DRIVE0(gpio/PINS_PER_COLLECTION); int bit_off = gpio % PINS_PER_COLLECTION; u8 drive; unsigned long flags; dc_gpio_set(chip, gpio, value); spin_lock_irqsave(&pmap->lock, flags); drive = readb_relaxed(pmap->regs + reg_off); drive |= BIT(bit_off); writeb_relaxed(drive, pmap->regs + reg_off); spin_unlock_irqrestore(&pmap->lock, flags); return 0; }