/* VIU OSD1 Reset as workaround for GXL+ Alpha OSD Bug */ void meson_viu_osd1_reset(struct meson_drm *priv) { uint32_t osd1_fifo_ctrl_stat, osd1_ctrl_stat2; /* Save these 2 registers state */ osd1_fifo_ctrl_stat = readl_relaxed( priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT)); osd1_ctrl_stat2 = readl_relaxed( priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); /* Reset OSD1 */ writel_bits_relaxed(BIT(0), BIT(0), priv->io_base + _REG(VIU_SW_RESET)); writel_bits_relaxed(BIT(0), 0, priv->io_base + _REG(VIU_SW_RESET)); /* Rewrite these registers state lost in the reset */ writel_relaxed(osd1_fifo_ctrl_stat, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT)); writel_relaxed(osd1_ctrl_stat2, priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); /* Reload the conversion matrix */ meson_viu_load_matrix(priv); }
void meson_vpp_init(struct meson_drm *priv) { /* set dummy data default YUV black */ if (meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) writel_relaxed(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1)); else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu")) { writel_bits_relaxed(0xff << 16, 0xff << 16, priv->io_base + _REG(VIU_MISC_CTRL1)); writel_relaxed(0x20000, priv->io_base + _REG(VPP_DOLBY_CTRL)); writel_relaxed(0x1020080, priv->io_base + _REG(VPP_DUMMY_DATA1)); } /* Initialize vpu fifo control registers */ writel_relaxed(readl_relaxed(priv->io_base + _REG(VPP_OFIFO_SIZE)) | 0x77f, priv->io_base + _REG(VPP_OFIFO_SIZE)); writel_relaxed(0x08080808, priv->io_base + _REG(VPP_HOLD_LINES)); /* Turn off preblend */ writel_bits_relaxed(VPP_PREBLEND_ENABLE, 0, priv->io_base + _REG(VPP_MISC)); /* Turn off POSTBLEND */ writel_bits_relaxed(VPP_POSTBLEND_ENABLE, 0, priv->io_base + _REG(VPP_MISC)); /* Force all planes off */ writel_bits_relaxed(VPP_OSD1_POSTBLEND | VPP_OSD2_POSTBLEND | VPP_VD1_POSTBLEND | VPP_VD2_POSTBLEND | VPP_VD1_PREBLEND | VPP_VD2_PREBLEND, 0, priv->io_base + _REG(VPP_MISC)); /* Setup default VD settings */ writel_relaxed(4096, priv->io_base + _REG(VPP_PREBLEND_VD1_H_START_END)); writel_relaxed(4096, priv->io_base + _REG(VPP_BLEND_VD2_H_START_END)); /* Disable Scalers */ writel_relaxed(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0)); writel_relaxed(0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0)); writel_relaxed(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0)); writel_relaxed(4 | (4 << 8) | BIT(15), priv->io_base + _REG(VPP_SC_MISC)); writel_relaxed(1, priv->io_base + _REG(VPP_VADJ_CTRL)); /* Write in the proper filter coefficients. */ meson_vpp_write_scaling_filter_coefs(priv, vpp_filter_coefs_4point_bspline, false); meson_vpp_write_scaling_filter_coefs(priv, vpp_filter_coefs_4point_bspline, true); /* Write the VD proper filter coefficients. */ meson_vpp_write_vd_scaling_filter_coefs(priv, vpp_filter_coefs_bicubic, false); meson_vpp_write_vd_scaling_filter_coefs(priv, vpp_filter_coefs_bicubic, true); }
static int meson_ao_cec_adap_enable(struct cec_adapter *adap, bool enable) { struct meson_ao_cec_device *ao_cec = adap->priv; int ret; meson_ao_cec_irq_setup(ao_cec, false); writel_bits_relaxed(CEC_GEN_CNTL_RESET, CEC_GEN_CNTL_RESET, ao_cec->base + CEC_GEN_CNTL_REG); if (!enable) return 0; /* Enable gated clock (Normal mode). */ writel_bits_relaxed(CEC_GEN_CNTL_CLK_CTRL_MASK, FIELD_PREP(CEC_GEN_CNTL_CLK_CTRL_MASK, CEC_GEN_CNTL_CLK_ENABLE), ao_cec->base + CEC_GEN_CNTL_REG); udelay(100); /* Release Reset */ writel_bits_relaxed(CEC_GEN_CNTL_RESET, 0, ao_cec->base + CEC_GEN_CNTL_REG); /* Clear buffers */ ret = meson_ao_cec_clear(ao_cec); if (ret) return ret; /* CEC arbitration 3/5/7 bit time set. */ ret = meson_ao_cec_arbit_bit_time_set(ao_cec, CEC_SIGNAL_FREE_TIME_RETRY, 0x118); if (ret) return ret; ret = meson_ao_cec_arbit_bit_time_set(ao_cec, CEC_SIGNAL_FREE_TIME_NEW_INITIATOR, 0x000); if (ret) return ret; ret = meson_ao_cec_arbit_bit_time_set(ao_cec, CEC_SIGNAL_FREE_TIME_NEXT_XFER, 0x2aa); if (ret) return ret; meson_ao_cec_irq_setup(ao_cec, true); return 0; }
static inline void meson_ao_cec_irq_setup(struct meson_ao_cec_device *ao_cec, bool enable) { u32 cfg = CEC_INTR_TX | CEC_INTR_RX; writel_bits_relaxed(cfg, enable ? cfg : 0, ao_cec->base + CEC_INTR_MASKN_REG); }
static void meson_venc_hdmi_encoder_disable(struct drm_encoder *encoder) { struct meson_dw_hdmi *dw_hdmi = encoder_to_meson_dw_hdmi(encoder); struct meson_drm *priv = dw_hdmi->priv; DRM_DEBUG_DRIVER("\n"); writel_bits_relaxed(0x3, 0, priv->io_base + _REG(VPU_HDMI_SETTING)); writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); }
void meson_viu_init(struct meson_drm *priv) { uint32_t reg; /* Disable OSDs */ writel_bits_relaxed(BIT(0) | BIT(21), 0, priv->io_base + _REG(VIU_OSD1_CTRL_STAT)); writel_bits_relaxed(BIT(0) | BIT(21), 0, priv->io_base + _REG(VIU_OSD2_CTRL_STAT)); /* On GXL/GXM, Use the 10bit HDR conversion matrix */ if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") || meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) meson_viu_load_matrix(priv); /* Initialize OSD1 fifo control register */ reg = BIT(0) | /* Urgent DDR request priority */ (4 << 5) | /* hold_fifo_lines */ (3 << 10) | /* burst length 64 */ (32 << 12) | /* fifo_depth_val: 32*8=256 */ (2 << 22) | /* 4 words in 1 burst */ (2 << 24); writel_relaxed(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT)); writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT)); /* Set OSD alpha replace value */ writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT, 0xff << OSD_REPLACE_SHIFT, priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT, 0xff << OSD_REPLACE_SHIFT, priv->io_base + _REG(VIU_OSD2_CTRL_STAT2)); priv->viu.osd1_enabled = false; priv->viu.osd1_commit = false; priv->viu.osd1_interlace = false; }
void meson_viu_set_osd_matrix(struct meson_drm *priv, enum viu_matrix_sel_e m_select, int *m, bool csc_on) { if (m_select == VIU_MATRIX_OSD) { /* osd matrix, VIU_MATRIX_0 */ writel(((m[0] & 0xfff) << 16) | (m[1] & 0xfff), priv->io_base + _REG(VIU_OSD1_MATRIX_PRE_OFFSET0_1)); writel(m[2] & 0xfff, priv->io_base + _REG(VIU_OSD1_MATRIX_PRE_OFFSET2)); writel(((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff), priv->io_base + _REG(VIU_OSD1_MATRIX_COEF00_01)); writel(((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff), priv->io_base + _REG(VIU_OSD1_MATRIX_COEF02_10)); writel(((m[7] & 0x1fff) << 16) | (m[8] & 0x1fff), priv->io_base + _REG(VIU_OSD1_MATRIX_COEF11_12)); writel(((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff), priv->io_base + _REG(VIU_OSD1_MATRIX_COEF20_21)); if (m[21]) { writel(((m[11] & 0x1fff) << 16) | (m[12] & 0x1fff), priv->io_base + _REG(VIU_OSD1_MATRIX_COEF22_30)); writel(((m[13] & 0x1fff) << 16) | (m[14] & 0x1fff), priv->io_base + _REG(VIU_OSD1_MATRIX_COEF31_32)); writel(((m[15] & 0x1fff) << 16) | (m[16] & 0x1fff), priv->io_base + _REG(VIU_OSD1_MATRIX_COEF40_41)); writel(m[17] & 0x1fff, priv->io_base + _REG(VIU_OSD1_MATRIX_COLMOD_COEF42)); } else writel((m[11] & 0x1fff) << 16, priv->io_base + _REG(VIU_OSD1_MATRIX_COEF22_30)); writel(((m[18] & 0xfff) << 16) | (m[19] & 0xfff), priv->io_base + _REG(VIU_OSD1_MATRIX_OFFSET0_1)); writel(m[20] & 0xfff, priv->io_base + _REG(VIU_OSD1_MATRIX_OFFSET2)); writel_bits_relaxed(3 << 30, m[21] << 30, priv->io_base + _REG(VIU_OSD1_MATRIX_COLMOD_COEF42)); writel_bits_relaxed(7 << 16, m[22] << 16, priv->io_base + _REG(VIU_OSD1_MATRIX_COLMOD_COEF42)); /* 23 reserved for clipping control */ writel_bits_relaxed(BIT(0), csc_on ? BIT(0) : 0, priv->io_base + _REG(VIU_OSD1_MATRIX_CTRL)); writel_bits_relaxed(BIT(1), 0, priv->io_base + _REG(VIU_OSD1_MATRIX_CTRL)); } else if (m_select == VIU_MATRIX_OSD_EOTF) { int i; /* osd eotf matrix, VIU_MATRIX_OSD_EOTF */ for (i = 0; i < 5; i++) writel(((m[i * 2] & 0x1fff) << 16) | (m[i * 2 + 1] & 0x1fff), priv->io_base + _REG(VIU_OSD1_EOTF_CTL + i + 1)); writel_bits_relaxed(BIT(30), csc_on ? BIT(30) : 0, priv->io_base + _REG(VIU_OSD1_EOTF_CTL)); writel_bits_relaxed(BIT(31), csc_on ? BIT(31) : 0, priv->io_base + _REG(VIU_OSD1_EOTF_CTL)); } }
void meson_viu_set_osd_lut(struct meson_drm *priv, enum viu_lut_sel_e lut_sel, unsigned int *r_map, unsigned int *g_map, unsigned int *b_map, bool csc_on) { unsigned int addr_port; unsigned int data_port; unsigned int ctrl_port; int i; if (lut_sel == VIU_LUT_OSD_EOTF) { addr_port = VIU_OSD1_EOTF_LUT_ADDR_PORT; data_port = VIU_OSD1_EOTF_LUT_DATA_PORT; ctrl_port = VIU_OSD1_EOTF_CTL; } else if (lut_sel == VIU_LUT_OSD_OETF) { addr_port = VIU_OSD1_OETF_LUT_ADDR_PORT; data_port = VIU_OSD1_OETF_LUT_DATA_PORT; ctrl_port = VIU_OSD1_OETF_CTL; } else return; if (lut_sel == VIU_LUT_OSD_OETF) { writel(0, priv->io_base + _REG(addr_port)); for (i = 0; i < (OSD_OETF_LUT_SIZE / 2); i++) writel(r_map[i * 2] | (r_map[i * 2 + 1] << 16), priv->io_base + _REG(data_port)); writel(r_map[OSD_OETF_LUT_SIZE - 1] | (g_map[0] << 16), priv->io_base + _REG(data_port)); for (i = 0; i < (OSD_OETF_LUT_SIZE / 2); i++) writel(g_map[i * 2 + 1] | (g_map[i * 2 + 2] << 16), priv->io_base + _REG(data_port)); for (i = 0; i < (OSD_OETF_LUT_SIZE / 2); i++) writel(b_map[i * 2] | (b_map[i * 2 + 1] << 16), priv->io_base + _REG(data_port)); writel(b_map[OSD_OETF_LUT_SIZE - 1], priv->io_base + _REG(data_port)); if (csc_on) writel_bits_relaxed(0x7 << 29, 7 << 29, priv->io_base + _REG(ctrl_port)); else writel_bits_relaxed(0x7 << 29, 0, priv->io_base + _REG(ctrl_port)); } else if (lut_sel == VIU_LUT_OSD_EOTF) { writel(0, priv->io_base + _REG(addr_port)); for (i = 0; i < (OSD_EOTF_LUT_SIZE / 2); i++) writel(r_map[i * 2] | (r_map[i * 2 + 1] << 16), priv->io_base + _REG(data_port)); writel(r_map[OSD_EOTF_LUT_SIZE - 1] | (g_map[0] << 16), priv->io_base + _REG(data_port)); for (i = 0; i < (OSD_EOTF_LUT_SIZE / 2); i++) writel(g_map[i * 2 + 1] | (g_map[i * 2 + 2] << 16), priv->io_base + _REG(data_port)); for (i = 0; i < (OSD_EOTF_LUT_SIZE / 2); i++) writel(b_map[i * 2] | (b_map[i * 2 + 1] << 16), priv->io_base + _REG(data_port)); writel(b_map[OSD_EOTF_LUT_SIZE - 1], priv->io_base + _REG(data_port)); if (csc_on) writel_bits_relaxed(7 << 27, 7 << 27, priv->io_base + _REG(ctrl_port)); else writel_bits_relaxed(7 << 27, 0, priv->io_base + _REG(ctrl_port)); writel_bits_relaxed(BIT(31), BIT(31), priv->io_base + _REG(ctrl_port)); } }
static int meson_dw_hdmi_bind(struct device *dev, struct device *master, void *data) { struct platform_device *pdev = to_platform_device(dev); const struct meson_dw_hdmi_data *match; struct meson_dw_hdmi *meson_dw_hdmi; struct drm_device *drm = data; struct meson_drm *priv = drm->dev_private; struct dw_hdmi_plat_data *dw_plat_data; struct drm_encoder *encoder; struct resource *res; int irq; int ret; DRM_DEBUG_DRIVER("\n"); if (!meson_hdmi_connector_is_available(dev)) { dev_info(drm->dev, "HDMI Output connector not available\n"); return -ENODEV; } match = of_device_get_match_data(&pdev->dev); if (!match) { dev_err(&pdev->dev, "failed to get match data\n"); return -ENODEV; } meson_dw_hdmi = devm_kzalloc(dev, sizeof(*meson_dw_hdmi), GFP_KERNEL); if (!meson_dw_hdmi) return -ENOMEM; meson_dw_hdmi->priv = priv; meson_dw_hdmi->dev = dev; meson_dw_hdmi->data = match; dw_plat_data = &meson_dw_hdmi->dw_plat_data; encoder = &meson_dw_hdmi->encoder; meson_dw_hdmi->hdmi_supply = devm_regulator_get_optional(dev, "hdmi"); if (IS_ERR(meson_dw_hdmi->hdmi_supply)) { if (PTR_ERR(meson_dw_hdmi->hdmi_supply) == -EPROBE_DEFER) return -EPROBE_DEFER; meson_dw_hdmi->hdmi_supply = NULL; } else { ret = regulator_enable(meson_dw_hdmi->hdmi_supply); if (ret) return ret; } meson_dw_hdmi->hdmitx_apb = devm_reset_control_get_exclusive(dev, "hdmitx_apb"); if (IS_ERR(meson_dw_hdmi->hdmitx_apb)) { dev_err(dev, "Failed to get hdmitx_apb reset\n"); return PTR_ERR(meson_dw_hdmi->hdmitx_apb); } meson_dw_hdmi->hdmitx_ctrl = devm_reset_control_get_exclusive(dev, "hdmitx"); if (IS_ERR(meson_dw_hdmi->hdmitx_ctrl)) { dev_err(dev, "Failed to get hdmitx reset\n"); return PTR_ERR(meson_dw_hdmi->hdmitx_ctrl); } meson_dw_hdmi->hdmitx_phy = devm_reset_control_get_exclusive(dev, "hdmitx_phy"); if (IS_ERR(meson_dw_hdmi->hdmitx_phy)) { dev_err(dev, "Failed to get hdmitx_phy reset\n"); return PTR_ERR(meson_dw_hdmi->hdmitx_phy); } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); meson_dw_hdmi->hdmitx = devm_ioremap_resource(dev, res); if (IS_ERR(meson_dw_hdmi->hdmitx)) return PTR_ERR(meson_dw_hdmi->hdmitx); meson_dw_hdmi->hdmi_pclk = devm_clk_get(dev, "isfr"); if (IS_ERR(meson_dw_hdmi->hdmi_pclk)) { dev_err(dev, "Unable to get HDMI pclk\n"); return PTR_ERR(meson_dw_hdmi->hdmi_pclk); } clk_prepare_enable(meson_dw_hdmi->hdmi_pclk); meson_dw_hdmi->venci_clk = devm_clk_get(dev, "venci"); if (IS_ERR(meson_dw_hdmi->venci_clk)) { dev_err(dev, "Unable to get venci clk\n"); return PTR_ERR(meson_dw_hdmi->venci_clk); } clk_prepare_enable(meson_dw_hdmi->venci_clk); dw_plat_data->regm = devm_regmap_init(dev, NULL, meson_dw_hdmi, &meson_dw_hdmi_regmap_config); if (IS_ERR(dw_plat_data->regm)) return PTR_ERR(dw_plat_data->regm); irq = platform_get_irq(pdev, 0); if (irq < 0) { dev_err(dev, "Failed to get hdmi top irq\n"); return irq; } ret = devm_request_threaded_irq(dev, irq, dw_hdmi_top_irq, dw_hdmi_top_thread_irq, IRQF_SHARED, "dw_hdmi_top_irq", meson_dw_hdmi); if (ret) { dev_err(dev, "Failed to request hdmi top irq\n"); return ret; } /* Encoder */ drm_encoder_helper_add(encoder, &meson_venc_hdmi_encoder_helper_funcs); ret = drm_encoder_init(drm, encoder, &meson_venc_hdmi_encoder_funcs, DRM_MODE_ENCODER_TMDS, "meson_hdmi"); if (ret) { dev_err(priv->dev, "Failed to init HDMI encoder\n"); return ret; } encoder->possible_crtcs = BIT(0); DRM_DEBUG_DRIVER("encoder initialized\n"); /* Enable clocks */ regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100); /* Bring HDMITX MEM output of power down */ regmap_update_bits(priv->hhi, HHI_MEM_PD_REG0, 0xff << 8, 0); /* Reset HDMITX APB & TX & PHY */ reset_control_reset(meson_dw_hdmi->hdmitx_apb); reset_control_reset(meson_dw_hdmi->hdmitx_ctrl); reset_control_reset(meson_dw_hdmi->hdmitx_phy); /* Enable APB3 fail on error */ if (!meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) { writel_bits_relaxed(BIT(15), BIT(15), meson_dw_hdmi->hdmitx + HDMITX_TOP_CTRL_REG); writel_bits_relaxed(BIT(15), BIT(15), meson_dw_hdmi->hdmitx + HDMITX_DWC_CTRL_REG); } /* Bring out of reset */ meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_SW_RESET, 0); msleep(20); meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_CLK_CNTL, 0xff); /* Enable HDMI-TX Interrupt */ meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_STAT_CLR, HDMITX_TOP_INTR_CORE); meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_MASKN, HDMITX_TOP_INTR_CORE); /* Bridge / Connector */ dw_plat_data->mode_valid = dw_hdmi_mode_valid; dw_plat_data->phy_ops = &meson_dw_hdmi_phy_ops; dw_plat_data->phy_name = "meson_dw_hdmi_phy"; dw_plat_data->phy_data = meson_dw_hdmi; dw_plat_data->input_bus_format = MEDIA_BUS_FMT_YUV8_1X24; dw_plat_data->input_bus_encoding = V4L2_YCBCR_ENC_709; platform_set_drvdata(pdev, meson_dw_hdmi); meson_dw_hdmi->hdmi = dw_hdmi_bind(pdev, encoder, &meson_dw_hdmi->dw_plat_data); if (IS_ERR(meson_dw_hdmi->hdmi)) return PTR_ERR(meson_dw_hdmi->hdmi); DRM_DEBUG_DRIVER("HDMI controller initialized\n"); return 0; }
static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, struct drm_display_mode *mode) { struct meson_dw_hdmi *dw_hdmi = (struct meson_dw_hdmi *)data; struct meson_drm *priv = dw_hdmi->priv; unsigned int wr_clk = readl_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING)); DRM_DEBUG_DRIVER("\"%s\" div%d\n", mode->name, mode->clock > 340000 ? 40 : 10); /* Enable clocks */ regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100); /* Bring HDMITX MEM output of power down */ regmap_update_bits(priv->hhi, HHI_MEM_PD_REG0, 0xff << 8, 0); /* Bring out of reset */ dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_SW_RESET, 0); /* Enable internal pixclk, tmds_clk, spdif_clk, i2s_clk, cecclk */ dw_hdmi_top_write_bits(dw_hdmi, HDMITX_TOP_CLK_CNTL, 0x3, 0x3); dw_hdmi_top_write_bits(dw_hdmi, HDMITX_TOP_CLK_CNTL, 0x3 << 4, 0x3 << 4); /* Enable normal output to PHY */ dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12)); /* TMDS pattern setup (TOFIX Handle the YUV420 case) */ if (mode->clock > 340000) { dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01, 0); dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23, 0x03ff03ff); } else { dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01, 0x001f001f); dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23, 0x001f001f); } /* Load TMDS pattern */ dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x1); msleep(20); dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x2); /* Setup PHY parameters */ meson_hdmi_phy_setup_mode(dw_hdmi, mode); /* Setup PHY */ regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xffff << 16, 0x0390 << 16); /* BIT_INVERT */ if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxl-dw-hdmi") || dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxm-dw-hdmi") || dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-g12a-dw-hdmi")) regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, BIT(17), 0); else regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, BIT(17), BIT(17)); /* Disable clock, fifo, fifo_wr */ regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0); dw_hdmi_set_high_tmds_clock_ratio(hdmi); msleep(100); /* Reset PHY 3 times in a row */ meson_dw_hdmi_phy_reset(dw_hdmi); meson_dw_hdmi_phy_reset(dw_hdmi); meson_dw_hdmi_phy_reset(dw_hdmi); /* Temporary Disable VENC video stream */ if (priv->venc.hdmi_use_enci) writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); else writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); /* Temporary Disable HDMI video stream to HDMI-TX */ writel_bits_relaxed(0x3, 0, priv->io_base + _REG(VPU_HDMI_SETTING)); writel_bits_relaxed(0xf << 8, 0, priv->io_base + _REG(VPU_HDMI_SETTING)); /* Re-Enable VENC video stream */ if (priv->venc.hdmi_use_enci) writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN)); else writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN)); /* Push back HDMI clock settings */ writel_bits_relaxed(0xf << 8, wr_clk & (0xf << 8), priv->io_base + _REG(VPU_HDMI_SETTING)); /* Enable and Select HDMI video source for HDMI-TX */ if (priv->venc.hdmi_use_enci) writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCI, priv->io_base + _REG(VPU_HDMI_SETTING)); else writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCP, priv->io_base + _REG(VPU_HDMI_SETTING)); return 0; }