static xf86MonPtr
LgDoDDC(ScrnInfoPtr pScrn)
{
CirPtr pCir = CIRPTR(pScrn);
xf86MonPtr MonInfo = NULL;
/* Map the CIR memory and MMIO areas */
if (!CirMapMem(pCir, pScrn->scrnIndex))
return FALSE;
#if LGuseI2C
if (!LgI2CInit(pScrn)) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "I2C initialization failed\n");
goto unmap_out;
}
/* Read and output monitor info using DDC2 over I2C bus */
MonInfo = xf86DoEDID_DDC2(pScrn->scrnIndex, pCir->I2CPtr1);
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "I2C Monitor info: %p\n",
(void *)MonInfo);
xf86PrintEDID(MonInfo);
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "end of I2C Monitor info\n\n");
#endif /* LGuseI2C */
xf86SetDDCproperties(pScrn, MonInfo);
unmap_out:
CirUnmapMem(pCir, pScrn->scrnIndex);
return MonInfo;
}
xf86MonPtr
SMILynx_ddc1(ScrnInfoPtr pScrn)
{
SMIPtr pSmi = SMIPTR(pScrn);
xf86MonPtr pMon;
unsigned char tmp;
ENTER();
tmp = VGAIN8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x72);
VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x72, tmp | 0x20);
pMon = xf86PrintEDID(xf86DoEDID_DDC1(XF86_SCRN_ARG(pScrn),
vgaHWddc1SetSpeedWeak(),
SMILynx_ddc1Read));
VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x72, tmp);
LEAVE(pMon);
}
void
chips_ddc1(ScrnInfoPtr pScrn)
{
unsigned char FR0B, FR0C, XR62;
unsigned char mask_c = 0x00;
unsigned char val, tmp_val;
int i;
CHIPSPtr cPtr = CHIPSPTR(pScrn);
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Probing for DDC1\n");
FR0C = cPtr->readFR(cPtr, 0x0C);
XR62 = cPtr->readXR(cPtr, 0x62);
switch (cPtr->Chipset) {
case CHIPS_CT65550:
cPtr->ddc_mask = 0x1F; /* GPIO 0-4 */
FR0B = cPtr->readFR(cPtr, 0x0B);
if (!(FR0B & 0x10)) /* GPIO 2 is used as 32 kHz input */
cPtr->ddc_mask &= 0xFB;
if (cPtr->Bus == ChipsVLB) /* GPIO 3-7 are used as address bits */
cPtr->ddc_mask &= 0x07;
break;
case CHIPS_CT65554:
case CHIPS_CT65555:
case CHIPS_CT68554:
cPtr->ddc_mask = 0x0F; /* GPIO 0-3 */
break;
case CHIPS_CT69000:
case CHIPS_CT69030:
cPtr->ddc_mask = 0x9F; /* GPIO 0-4,7? */
break;
default:
cPtr->ddc_mask = 0x0C; /* GPIO 2,3 */
break;
}
if (!(FR0C & 0x80)) { /* GPIO 1 is not available */
mask_c |= 0xC0;
cPtr->ddc_mask &= 0xFE;
}
if (!(FR0C & 0x10)) { /* GPIO 0 is not available */
mask_c |= 0x18;
cPtr->ddc_mask &= 0xFD;
}
/* set GPIO 0,1 to read if available */
cPtr->writeFR(cPtr, 0x0C, (FR0C & mask_c) | (~mask_c & 0x90));
/* set remaining GPIO to read */
cPtr->writeXR(cPtr, 0x62, 0x00);
val = chips_ddc1Read(pScrn);
for (i = 0; i < 70; i++) {
tmp_val = chips_ddc1Read(pScrn);
if (tmp_val != val)
break;
}
cPtr->ddc_mask = val ^ tmp_val;
if (cPtr->ddc_mask)
xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "DDC1 found\n");
else return;
xf86PrintEDID(xf86DoEDID_DDC1(pScrn->scrnIndex,vgaHWddc1SetSpeed,
chips_ddc1Read));
/* restore */
cPtr->writeFR(cPtr, 0x0C, FR0C);
cPtr->writeXR(cPtr, 0x62, XR62);
}
