static void xgene_enet_rd_mac(struct xgene_enet_pdata *pdata, u32 rd_addr, u32 *rd_data) { void __iomem *addr, *rd, *cmd, *cmd_done; addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET; rd = pdata->mcx_mac_addr + MAC_READ_REG_OFFSET; cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET; cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET; if (!xgene_enet_rd_indirect(addr, rd, cmd, cmd_done, rd_addr, rd_data)) netdev_err(pdata->ndev, "MCX mac read failed, addr: %04x\n", rd_addr); }
static bool xgene_enet_rd_pcs(struct xgene_enet_pdata *pdata, u32 rd_addr, u32 *rd_data) { void __iomem *addr, *rd, *cmd, *cmd_done; bool success; addr = pdata->pcs_addr + PCS_ADDR_REG_OFFSET; rd = pdata->pcs_addr + PCS_READ_REG_OFFSET; cmd = pdata->pcs_addr + PCS_COMMAND_REG_OFFSET; cmd_done = pdata->pcs_addr + PCS_COMMAND_DONE_REG_OFFSET; success = xgene_enet_rd_indirect(addr, rd, cmd, cmd_done, rd_addr, rd_data); if (!success) netdev_err(pdata->ndev, "PCS read failed, addr: %04x\n", rd_addr); return success; }
static u32 xgene_enet_rd_mac(struct xgene_enet_pdata *p, u32 rd_addr) { struct xgene_indirect_ctl ctl = { .addr = p->mcx_mac_addr + MAC_ADDR_REG_OFFSET, .ctl = p->mcx_mac_addr + MAC_READ_REG_OFFSET, .cmd = p->mcx_mac_addr + MAC_COMMAND_REG_OFFSET, .cmd_done = p->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET }; return xgene_enet_rd_indirect(&ctl, rd_addr); } static int xgene_enet_ecc_init(struct xgene_enet_pdata *p) { struct net_device *ndev = p->ndev; u32 data; int i; xgene_enet_wr_diag_csr(p, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0); for (i = 0; i < 10 && data != ~0U ; i++) { usleep_range(100, 110); data = xgene_enet_rd_diag_csr(p, ENET_BLOCK_MEM_RDY_ADDR); } if (data != ~0U) { netdev_err(ndev, "Failed to release memory from shutdown\n"); return -ENODEV; } return 0; } static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *p) { u32 val = 0xffffffff; xgene_enet_wr_ring_if(p, ENET_CFGSSQMIWQASSOC_ADDR, val); xgene_enet_wr_ring_if(p, ENET_CFGSSQMIFPQASSOC_ADDR, val); }