static void xlx_spi_reset(DeviceState *d)
{
xlx_spi_do_reset(XILINX_SPI(d));
}
static void
spi_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
XilinxSPI *s = opaque;
uint32_t value = val64;
DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr, value);
addr >>= 2;
switch (addr) {
case R_SRR:
if (value != 0xa) {
DB_PRINT("Invalid write to SRR %x\n", value);
} else {
xlx_spi_do_reset(s);
}
break;
case R_SPIDTR:
s->regs[R_SPISR] &= ~SR_TX_EMPTY;
fifo8_push(&s->tx_fifo, (uint8_t)value);
if (fifo8_is_full(&s->tx_fifo)) {
s->regs[R_SPISR] |= SR_TX_FULL;
}
if (!spi_master_enabled(s)) {
goto done;
} else {
DB_PRINT("DTR and master enabled\n");
}
spi_flush_txfifo(s);
break;
case R_SPISR:
DB_PRINT("Invalid write to SPISR %x\n", value);
break;
case R_IPISR:
/* Toggle the bits. */
s->regs[addr] ^= value;
break;
/* Slave Select Register. */
case R_SPISSR:
s->regs[addr] = value;
xlx_spi_update_cs(s);
break;
case R_SPICR:
/* FIXME: reset irq and sr state to empty queues. */
if (value & R_SPICR_RXFF_RST) {
rxfifo_reset(s);
}
if (value & R_SPICR_TXFF_RST) {
txfifo_reset(s);
}
value &= ~(R_SPICR_RXFF_RST | R_SPICR_TXFF_RST);
s->regs[addr] = value;
if (!(value & R_SPICR_MTI)) {
spi_flush_txfifo(s);
}
break;
default:
if (addr < ARRAY_SIZE(s->regs)) {
s->regs[addr] = value;
}
break;
}
done:
xlx_spi_update_irq(s);
}
static void xlx_spi_reset(DeviceState *d)
{
xlx_spi_do_reset(DO_UPCAST(XilinxSPI, busdev.qdev, d));
}