bool
UnwindAssemblyInstEmulation::GetNonCallSiteUnwindPlanFromAssembly (AddressRange& range,
Thread& thread,
UnwindPlan& unwind_plan)
{
if (range.GetByteSize() > 0 &&
range.GetBaseAddress().IsValid() &&
m_inst_emulator_ap.get())
{
// The instruction emulation subclass setup the unwind plan for the
// first instruction.
m_inst_emulator_ap->CreateFunctionEntryUnwind (unwind_plan);
// CreateFunctionEntryUnwind should have created the first row. If it
// doesn't, then we are done.
if (unwind_plan.GetRowCount() == 0)
return false;
ExecutionContext exe_ctx;
thread.CalculateExecutionContext(exe_ctx);
const bool prefer_file_cache = true;
DisassemblerSP disasm_sp (Disassembler::DisassembleRange (m_arch,
NULL,
NULL,
exe_ctx,
range,
prefer_file_cache));
Log *log(GetLogIfAllCategoriesSet (LIBLLDB_LOG_UNWIND));
if (disasm_sp)
{
m_range_ptr = ⦥
m_thread_ptr = &thread;
m_unwind_plan_ptr = &unwind_plan;
const uint32_t addr_byte_size = m_arch.GetAddressByteSize();
const bool show_address = true;
const bool show_bytes = true;
m_inst_emulator_ap->GetRegisterInfo (unwind_plan.GetRegisterKind(),
unwind_plan.GetInitialCFARegister(),
m_cfa_reg_info);
m_fp_is_cfa = false;
m_register_values.clear();
m_pushed_regs.clear();
// Initialize the CFA with a known value. In the 32 bit case
// it will be 0x80000000, and in the 64 bit case 0x8000000000000000.
// We use the address byte size to be safe for any future address sizes
m_initial_sp = (1ull << ((addr_byte_size * 8) - 1));
RegisterValue cfa_reg_value;
cfa_reg_value.SetUInt (m_initial_sp, m_cfa_reg_info.byte_size);
SetRegisterValue (m_cfa_reg_info, cfa_reg_value);
const InstructionList &inst_list = disasm_sp->GetInstructionList ();
const size_t num_instructions = inst_list.GetSize();
if (num_instructions > 0)
{
Instruction *inst = inst_list.GetInstructionAtIndex (0).get();
const addr_t base_addr = inst->GetAddress().GetFileAddress();
// Make a copy of the current instruction Row and save it in m_curr_row
// so we can add updates as we process the instructions.
UnwindPlan::RowSP last_row = unwind_plan.GetLastRow();
UnwindPlan::Row *newrow = new UnwindPlan::Row;
if (last_row.get())
*newrow = *last_row.get();
m_curr_row.reset(newrow);
// Once we've seen the initial prologue instructions complete, save a
// copy of the CFI at that point into prologue_completed_row for possible
// use later.
int instructions_since_last_prologue_insn = 0; // # of insns since last CFI was update
bool reinstate_prologue_next_instruction = false; // Next iteration, re-install the prologue row of CFI
bool last_instruction_restored_return_addr_reg = false; // re-install the prologue row of CFI if the next instruction is a branch immediate
bool return_address_register_has_been_saved = false; // if we've seen the ra register get saved yet
UnwindPlan::RowSP prologue_completed_row; // copy of prologue row of CFI
// cache the pc register number (in whatever register numbering this UnwindPlan uses) for
// quick reference during instruction parsing.
uint32_t pc_reg_num = LLDB_INVALID_REGNUM;
RegisterInfo pc_reg_info;
if (m_inst_emulator_ap->GetRegisterInfo (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, pc_reg_info))
pc_reg_num = pc_reg_info.kinds[unwind_plan.GetRegisterKind()];
else
pc_reg_num = LLDB_INVALID_REGNUM;
// cache the return address register number (in whatever register numbering this UnwindPlan uses) for
// quick reference during instruction parsing.
uint32_t ra_reg_num = LLDB_INVALID_REGNUM;
RegisterInfo ra_reg_info;
if (m_inst_emulator_ap->GetRegisterInfo (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, ra_reg_info))
ra_reg_num = ra_reg_info.kinds[unwind_plan.GetRegisterKind()];
else
ra_reg_num = LLDB_INVALID_REGNUM;
for (size_t idx=0; idx<num_instructions; ++idx)
{
m_curr_row_modified = false;
m_curr_insn_restored_a_register = false;
inst = inst_list.GetInstructionAtIndex (idx).get();
if (inst)
{
if (log && log->GetVerbose ())
{
StreamString strm;
inst->Dump(&strm, inst_list.GetMaxOpcocdeByteSize (), show_address, show_bytes, NULL);
log->PutCString (strm.GetData());
}
m_inst_emulator_ap->SetInstruction (inst->GetOpcode(),
inst->GetAddress(),
exe_ctx.GetTargetPtr());
m_inst_emulator_ap->EvaluateInstruction (eEmulateInstructionOptionIgnoreConditions);
// Were there any changes to the CFI while evaluating this instruction?
if (m_curr_row_modified)
{
reinstate_prologue_next_instruction = false;
m_curr_row->SetOffset (inst->GetAddress().GetFileAddress() + inst->GetOpcode().GetByteSize() - base_addr);
// Append the new row
unwind_plan.AppendRow (m_curr_row);
// Allocate a new Row for m_curr_row, copy the current state into it
UnwindPlan::Row *newrow = new UnwindPlan::Row;
*newrow = *m_curr_row.get();
m_curr_row.reset(newrow);
// If m_curr_insn_restored_a_register == true, we're looking at an epilogue instruction.
// Set instructions_since_last_prologue_insn to a very high number so we don't append
// any of these epilogue instructions to our prologue_complete row.
if (m_curr_insn_restored_a_register == false && instructions_since_last_prologue_insn < 8)
instructions_since_last_prologue_insn = 0;
else
instructions_since_last_prologue_insn = 99;
UnwindPlan::Row::RegisterLocation pc_regloc;
UnwindPlan::Row::RegisterLocation ra_regloc;
// While parsing the instructions of this function, if we've ever
// seen the return address register (aka lr on arm) in a non-IsSame() state,
// it has been saved on the stack. If it's ever back to IsSame(), we've
// executed an epilogue.
if (ra_reg_num != LLDB_INVALID_REGNUM
&& m_curr_row->GetRegisterInfo (ra_reg_num, ra_regloc)
&& !ra_regloc.IsSame())
{
return_address_register_has_been_saved = true;
}
// If the caller's pc is "same", we've just executed an epilogue and we return to the caller
// after this instruction completes executing.
// If there are any instructions past this, there must have been flow control over this
// epilogue so we'll reinstate the original prologue setup instructions.
if (prologue_completed_row.get()
&& pc_reg_num != LLDB_INVALID_REGNUM
&& m_curr_row->GetRegisterInfo (pc_reg_num, pc_regloc)
&& pc_regloc.IsSame())
{
if (log && log->GetVerbose())
log->Printf("UnwindAssemblyInstEmulation::GetNonCallSiteUnwindPlanFromAssembly -- pc is <same>, restore prologue instructions.");
reinstate_prologue_next_instruction = true;
}
else if (prologue_completed_row.get()
&& return_address_register_has_been_saved
&& ra_reg_num != LLDB_INVALID_REGNUM
&& m_curr_row->GetRegisterInfo (ra_reg_num, ra_regloc)
&& ra_regloc.IsSame())
{
if (log && log->GetVerbose())
log->Printf("UnwindAssemblyInstEmulation::GetNonCallSiteUnwindPlanFromAssembly -- lr is <same>, restore prologue instruction if the next instruction is a branch immediate.");
last_instruction_restored_return_addr_reg = true;
}
}
else
{
// If the previous instruction was a return-to-caller (epilogue), and we're still executing
// instructions in this function, there must be a code path that jumps over that epilogue.
// Also detect the case where we epilogue & branch imm to another function (tail-call opt)
// instead of a normal pop lr-into-pc exit.
// Reinstate the frame setup from the prologue.
if (reinstate_prologue_next_instruction
|| (m_curr_insn_is_branch_immediate && last_instruction_restored_return_addr_reg))
{
if (log && log->GetVerbose())
log->Printf("UnwindAssemblyInstEmulation::GetNonCallSiteUnwindPlanFromAssembly -- Reinstating prologue instruction set");
UnwindPlan::Row *newrow = new UnwindPlan::Row;
*newrow = *prologue_completed_row.get();
m_curr_row.reset(newrow);
m_curr_row->SetOffset (inst->GetAddress().GetFileAddress() + inst->GetOpcode().GetByteSize() - base_addr);
unwind_plan.AppendRow(m_curr_row);
newrow = new UnwindPlan::Row;
*newrow = *m_curr_row.get();
m_curr_row.reset(newrow);
reinstate_prologue_next_instruction = false;
last_instruction_restored_return_addr_reg = false;
m_curr_insn_is_branch_immediate = false;
}
// clear both of these if either one wasn't set
if (last_instruction_restored_return_addr_reg)
{
last_instruction_restored_return_addr_reg = false;
}
if (m_curr_insn_is_branch_immediate)
{
m_curr_insn_is_branch_immediate = false;
}
// Stop updating the prologue instructions if we've seen 8 non-prologue instructions
// in a row.
if (instructions_since_last_prologue_insn++ < 8)
{
UnwindPlan::Row *newrow = new UnwindPlan::Row;
*newrow = *m_curr_row.get();
prologue_completed_row.reset(newrow);
if (log && log->GetVerbose())
log->Printf("UnwindAssemblyInstEmulation::GetNonCallSiteUnwindPlanFromAssembly -- saving a copy of the current row as the prologue row.");
}
}
}
}
}
// FIXME: The DisassemblerLLVMC has a reference cycle and won't go away if it has any active instructions.
// I'll fix that but for now, just clear the list and it will go away nicely.
disasm_sp->GetInstructionList().Clear();
}
if (log && log->GetVerbose ())
{
StreamString strm;
lldb::addr_t base_addr = range.GetBaseAddress().GetLoadAddress(thread.CalculateTarget().get());
strm.Printf ("Resulting unwind rows for [0x%" PRIx64 " - 0x%" PRIx64 "):", base_addr, base_addr + range.GetByteSize());
unwind_plan.Dump(strm, &thread, base_addr);
log->PutCString (strm.GetData());
}
return unwind_plan.GetRowCount() > 0;
}
return false;
}
int main(int argc, char **argv){
int whichConfig=0;
uint64 tempTime=0;
whichConfig=atoi(argv[1]);
//Select configuration and read it
switch(whichConfig){
case BASE:
printf("Using Base Config\n");
Config::readConfigFile("./configs/parametersBase.conf");
break;
case L12WAY:
printf("Using L1 2-Way Config\n");
Config::readConfigFile("./configs/parametersL12.conf");
break;
case L22WAY:
printf("Using L2 2-Way Config\n");
Config::readConfigFile("./configs/parametersL22.conf");
break;
case ALL2WAY:
printf("Using All 2-way Config\n");
Config::readConfigFile("./configs/parametersAll2.conf");
break;
case L12WAYL24WAY:
printf("Using L12WAYL24WAY Config\n");
Config::readConfigFile("./configs/parametersL12L24.conf");
break;
case L2BIG:
printf("Using L2BIG Config\n");
Config::readConfigFile("./configs/parametersL2Big.conf");
break;
case ALLFA:
printf("Using ALL FA Config\n");
Config::readConfigFile("./configs/parametersAllFA.conf");
break;
default:
printf("Invalid Configuration File Number:%d\n",whichConfig);
break;
}
//Create caches based on configuration
Cache* L1I = Cache::CreateCache(Cache::CL_L1I, L1_cache_size, L1_block_size, L1_assoc);
Cache* L1D = Cache::CreateCache(Cache::CL_L1D, L1_cache_size, L1_block_size, L1_assoc);
Cache* L2 = Cache::CreateCache(Cache::CL_L2, L2_cache_size, L2_block_size, L2_assoc);
//Open trace file & instantiate instruction and result vectors
Trace::OpenTraceFile(INPUTTRACE);
Instruction* instr = new Instruction();
Results* results = new Results();
//Deal with command line arguments
if (argc < 2) printBool=false;
else if(argv[2] != NULL){
if (atoi(argv[2]) == 1) printBool=true;
}
printf("Status of printing: %s\n",BoolToString(printBool));
//Start simulation and keep running until end of trace file
while (Trace::GetInstruction(instr, results) == 0){
tempTime=results->GetExecTime();
if (printBool == true) Trace::PrintInstruction(instr);
Simulator::HandleInstruction(instr, L1I, L1D, L2, results);
tempTime=results->GetExecTime()-tempTime;
results->AddCycleCount(instr->GetOpcode(),tempTime);
if (printBool == true) printf("Simulated Time = %llu\n",results->GetExecTime());
}
//Save results vector to output file & exit
results->PrintResults();
return 0;
}
