BOOLEAN MemNInitMCTNb ( IN OUT MEM_NB_BLOCK *NBPtr ) { MEM_TECH_BLOCK *TechPtr; UINT8 Dct; BOOLEAN Flag; ID_INFO CallOutIdInfo; TechPtr = NBPtr->TechPtr; // Switch Tech functions for Nb NBPtr->TechBlockSwitch (NBPtr); // Start Memory controller initialization sequence Flag = FALSE; if (TechPtr->DimmPresence (TechPtr)) { AGESA_TESTPOINT (TpProcMemPlatformSpecificInit, &(NBPtr->MemPtr->StdHeader)); if (NBPtr->MemNPlatformSpecificFormFactorInitNb (NBPtr)) { AGESA_TESTPOINT (TpProcMemSpdTiming, &(NBPtr->MemPtr->StdHeader)); if (TechPtr->SpdCalcWidth (TechPtr)) { AGESA_TESTPOINT (TpProcMemSpeedTclConfig, &(NBPtr->MemPtr->StdHeader)); if (TechPtr->SpdGetTargetSpeed (TechPtr)) { for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { NBPtr->SwitchDCT (NBPtr, Dct); Flag |= MemNInitDCTNb (NBPtr); } if (Flag && !NBPtr->IsSupported[TwoStageDramInit] && (NBPtr->MCTPtr->ErrCode != AGESA_FATAL)) { MemFInitTableDrive (NBPtr, MTBeforeDInit); AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader)); IDS_PERF_TIMESTAMP (TP_BEGINAGESAHOOKBEFOREDRAMINIT, &(NBPtr->MemPtr->StdHeader)); CallOutIdInfo.IdField.SocketId = NBPtr->MCTPtr->SocketId; CallOutIdInfo.IdField.ModuleId = NBPtr->MCTPtr->DieId; IDS_HDT_CONSOLE (MEM_FLOW, "\nCalling out to Platform BIOS on Socket %d Module %d...\n", CallOutIdInfo.IdField.SocketId, CallOutIdInfo.IdField.ModuleId); AgesaHookBeforeDramInit ((UINTN) CallOutIdInfo.IdInformation, NBPtr->MemPtr); IDS_HDT_CONSOLE (MEM_FLOW, "\nVDDIO = 1.%dV\n", (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) ? 5 : (NBPtr->RefPtr->DDR3Voltage == VOLT1_35) ? 35 : (NBPtr->RefPtr->DDR3Voltage == VOLT1_25) ? 25 : 999); AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader)); IDS_PERF_TIMESTAMP (TP_ENDAGESAHOOKBEFOREDRAMINIT, &(NBPtr->MemPtr->StdHeader)); IDS_OPTION_HOOK (IDS_BEFORE_DRAM_INIT, NBPtr, &(NBPtr->MemPtr->StdHeader)); NBPtr->StartupDCT (NBPtr); } } } } } return (BOOLEAN) (NBPtr->MCTPtr->ErrCode != AGESA_FATAL); }
BOOLEAN MemNInitMCTNb ( IN OUT MEM_NB_BLOCK *NBPtr ) { MEM_TECH_BLOCK *TechPtr; UINT8 Dct; BOOLEAN Flag; TechPtr = NBPtr->TechPtr; // Switch Tech functions for Nb NBPtr->TechBlockSwitch (NBPtr); // Start Memory controller initialization sequence Flag = FALSE; if (TechPtr->DimmPresence (TechPtr)) { AGESA_TESTPOINT (TpProcMemPlatformSpecificInit, &(NBPtr->MemPtr->StdHeader)); if (NBPtr->MemNPlatformSpecificFormFactorInitNb (NBPtr)) { AGESA_TESTPOINT (TpProcMemSpdTiming, &(NBPtr->MemPtr->StdHeader)); if (TechPtr->SpdCalcWidth (TechPtr)) { AGESA_TESTPOINT (TpProcMemSpeedTclConfig, &(NBPtr->MemPtr->StdHeader)); if (TechPtr->SpdGetTargetSpeed (TechPtr)) { for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { NBPtr->SwitchDCT (NBPtr, Dct); Flag |= MemNInitDCTNb (NBPtr); } if (Flag && (NBPtr->MCTPtr->ErrCode != AGESA_FATAL)) { MemFInitTableDrive (NBPtr, MTBeforeDInit); AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader)); AgesaHookBeforeDramInit (0, NBPtr->MemPtr); AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader)); IDS_OPTION_HOOK (IDS_BEFORE_DRAM_INIT, NBPtr, &(NBPtr->MemPtr->StdHeader)); NBPtr->StartupDCT (NBPtr); } } } } } return (BOOLEAN) (NBPtr->MCTPtr->ErrCode != AGESA_FATAL); }