void HexagonEarlyIfConversion::simplifyFlowGraph(const FlowPattern &FP) { if (FP.TrueB) removeBlock(FP.TrueB); if (FP.FalseB) removeBlock(FP.FalseB); FP.SplitB->updateTerminator(); if (FP.SplitB->succ_size() != 1) return; MachineBasicBlock *SB = *FP.SplitB->succ_begin(); if (SB->pred_size() != 1) return; // By now, the split block has only one successor (SB), and SB has only // one predecessor. We can try to merge them. We will need to update ter- // minators in FP.Split+SB, and that requires working AnalyzeBranch, which // fails on Hexagon for blocks that have EH_LABELs. However, if SB ends // with an unconditional branch, we won't need to touch the terminators. if (!hasEHLabel(SB) || hasUncondBranch(SB)) mergeBlocks(FP.SplitB, SB); }
/// SinkInstruction - Determine whether it is safe to sink the specified machine /// instruction out of its current block into a successor. bool MachineSinking::SinkInstruction(MachineInstr *MI, bool &SawStore) { // Don't sink insert_subreg, subreg_to_reg, reg_sequence. These are meant to // be close to the source to make it easier to coalesce. if (AvoidsSinking(MI, MRI)) return false; // Check if it's safe to move the instruction. if (!MI->isSafeToMove(AA, SawStore)) return false; // FIXME: This should include support for sinking instructions within the // block they are currently in to shorten the live ranges. We often get // instructions sunk into the top of a large block, but it would be better to // also sink them down before their first use in the block. This xform has to // be careful not to *increase* register pressure though, e.g. sinking // "x = y + z" down if it kills y and z would increase the live ranges of y // and z and only shrink the live range of x. bool BreakPHIEdge = false; MachineBasicBlock *ParentBlock = MI->getParent(); MachineBasicBlock *SuccToSinkTo = FindSuccToSinkTo(MI, ParentBlock, BreakPHIEdge); // If there are no outputs, it must have side-effects. if (!SuccToSinkTo) return false; // If the instruction to move defines a dead physical register which is live // when leaving the basic block, don't move it because it could turn into a // "zombie" define of that preg. E.g., EFLAGS. (<rdar://problem/8030636>) for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) { const MachineOperand &MO = MI->getOperand(I); if (!MO.isReg()) continue; unsigned Reg = MO.getReg(); if (Reg == 0 || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue; if (SuccToSinkTo->isLiveIn(Reg)) return false; } DEBUG(dbgs() << "Sink instr " << *MI << "\tinto block " << *SuccToSinkTo); // If the block has multiple predecessors, this is a critical edge. // Decide if we can sink along it or need to break the edge. if (SuccToSinkTo->pred_size() > 1) { // We cannot sink a load across a critical edge - there may be stores in // other code paths. bool TryBreak = false; bool store = true; if (!MI->isSafeToMove(AA, store)) { DEBUG(dbgs() << " *** NOTE: Won't sink load along critical edge.\n"); TryBreak = true; } // We don't want to sink across a critical edge if we don't dominate the // successor. We could be introducing calculations to new code paths. if (!TryBreak && !DT->dominates(ParentBlock, SuccToSinkTo)) { DEBUG(dbgs() << " *** NOTE: Critical edge found\n"); TryBreak = true; } // Don't sink instructions into a loop. if (!TryBreak && LI->isLoopHeader(SuccToSinkTo)) { DEBUG(dbgs() << " *** NOTE: Loop header found\n"); TryBreak = true; } // Otherwise we are OK with sinking along a critical edge. if (!TryBreak) DEBUG(dbgs() << "Sinking along critical edge.\n"); else { // Mark this edge as to be split. // If the edge can actually be split, the next iteration of the main loop // will sink MI in the newly created block. bool Status = PostponeSplitCriticalEdge(MI, ParentBlock, SuccToSinkTo, BreakPHIEdge); if (!Status) DEBUG(dbgs() << " *** PUNTING: Not legal or profitable to " "break critical edge\n"); // The instruction will not be sunk this time. return false; } } if (BreakPHIEdge) { // BreakPHIEdge is true if all the uses are in the successor MBB being // sunken into and they are all PHI nodes. In this case, machine-sink must // break the critical edge first. bool Status = PostponeSplitCriticalEdge(MI, ParentBlock, SuccToSinkTo, BreakPHIEdge); if (!Status) DEBUG(dbgs() << " *** PUNTING: Not legal or profitable to " "break critical edge\n"); // The instruction will not be sunk this time. return false; } // Determine where to insert into. Skip phi nodes. MachineBasicBlock::iterator InsertPos = SuccToSinkTo->begin(); while (InsertPos != SuccToSinkTo->end() && InsertPos->isPHI()) ++InsertPos; // collect matching debug values. SmallVector<MachineInstr *, 2> DbgValuesToSink; collectDebugValues(MI, DbgValuesToSink); // Move the instruction. SuccToSinkTo->splice(InsertPos, ParentBlock, MI, ++MachineBasicBlock::iterator(MI)); // Move debug values. for (SmallVectorImpl<MachineInstr *>::iterator DBI = DbgValuesToSink.begin(), DBE = DbgValuesToSink.end(); DBI != DBE; ++DBI) { MachineInstr *DbgMI = *DBI; SuccToSinkTo->splice(InsertPos, ParentBlock, DbgMI, ++MachineBasicBlock::iterator(DbgMI)); } // Conservatively, clear any kill flags, since it's possible that they are no // longer correct. // Note that we have to clear the kill flags for any register this instruction // uses as we may sink over another instruction which currently kills the // used registers. for (MachineOperand &MO : MI->operands()) { if (MO.isReg() && MO.isUse()) RegsToClearKillFlags.set(MO.getReg()); // Remember to clear kill flags. } return true; }
bool PostRAMachineSinking::tryToSinkCopy(MachineBasicBlock &CurBB, MachineFunction &MF, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII) { SmallPtrSet<MachineBasicBlock *, 2> SinkableBBs; // FIXME: For now, we sink only to a successor which has a single predecessor // so that we can directly sink COPY instructions to the successor without // adding any new block or branch instruction. for (MachineBasicBlock *SI : CurBB.successors()) if (!SI->livein_empty() && SI->pred_size() == 1) SinkableBBs.insert(SI); if (SinkableBBs.empty()) return false; bool Changed = false; // Track which registers have been modified and used between the end of the // block and the current instruction. ModifiedRegUnits.clear(); UsedRegUnits.clear(); for (auto I = CurBB.rbegin(), E = CurBB.rend(); I != E;) { MachineInstr *MI = &*I; ++I; if (MI->isDebugInstr()) continue; // Do not move any instruction across function call. if (MI->isCall()) return false; if (!MI->isCopy() || !MI->getOperand(0).isRenamable()) { LiveRegUnits::accumulateUsedDefed(*MI, ModifiedRegUnits, UsedRegUnits, TRI); continue; } // Track the operand index for use in Copy. SmallVector<unsigned, 2> UsedOpsInCopy; // Track the register number defed in Copy. SmallVector<unsigned, 2> DefedRegsInCopy; // Don't sink the COPY if it would violate a register dependency. if (hasRegisterDependency(MI, UsedOpsInCopy, DefedRegsInCopy, ModifiedRegUnits, UsedRegUnits)) { LiveRegUnits::accumulateUsedDefed(*MI, ModifiedRegUnits, UsedRegUnits, TRI); continue; } assert((!UsedOpsInCopy.empty() && !DefedRegsInCopy.empty()) && "Unexpect SrcReg or DefReg"); MachineBasicBlock *SuccBB = getSingleLiveInSuccBB(CurBB, SinkableBBs, DefedRegsInCopy, TRI); // Don't sink if we cannot find a single sinkable successor in which Reg // is live-in. if (!SuccBB) { LiveRegUnits::accumulateUsedDefed(*MI, ModifiedRegUnits, UsedRegUnits, TRI); continue; } assert((SuccBB->pred_size() == 1 && *SuccBB->pred_begin() == &CurBB) && "Unexpected predecessor"); // Clear the kill flag if SrcReg is killed between MI and the end of the // block. clearKillFlags(MI, CurBB, UsedOpsInCopy, UsedRegUnits, TRI); MachineBasicBlock::iterator InsertPos = SuccBB->getFirstNonPHI(); performSink(*MI, *SuccBB, InsertPos); updateLiveIn(MI, SuccBB, UsedOpsInCopy, DefedRegsInCopy); Changed = true; ++NumPostRACopySink; } return Changed; }
/// IfConvertDiamond - If convert a diamond sub-CFG. /// bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind, unsigned NumDups1, unsigned NumDups2) { BBInfo &TrueBBI = BBAnalysis[BBI.TrueBB->getNumber()]; BBInfo &FalseBBI = BBAnalysis[BBI.FalseBB->getNumber()]; MachineBasicBlock *TailBB = TrueBBI.TrueBB; // True block must fall through or end with an unanalyzable terminator. if (!TailBB) { if (blockAlwaysFallThrough(TrueBBI)) TailBB = FalseBBI.TrueBB; assert((TailBB || !TrueBBI.IsBrAnalyzable) && "Unexpected!"); } if (TrueBBI.IsDone || FalseBBI.IsDone || TrueBBI.BB->pred_size() > 1 || FalseBBI.BB->pred_size() > 1) { // Something has changed. It's no longer safe to predicate these blocks. BBI.IsAnalyzed = false; TrueBBI.IsAnalyzed = false; FalseBBI.IsAnalyzed = false; return false; } // Merge the 'true' and 'false' blocks by copying the instructions // from the 'false' block to the 'true' block. That is, unless the true // block would clobber the predicate, in that case, do the opposite. BBInfo *BBI1 = &TrueBBI; BBInfo *BBI2 = &FalseBBI; SmallVector<MachineOperand, 4> RevCond(BBI.BrCond.begin(), BBI.BrCond.end()); if (TII->ReverseBranchCondition(RevCond)) assert(false && "Unable to reverse branch condition!"); SmallVector<MachineOperand, 4> *Cond1 = &BBI.BrCond; SmallVector<MachineOperand, 4> *Cond2 = &RevCond; // Figure out the more profitable ordering. bool DoSwap = false; if (TrueBBI.ClobbersPred && !FalseBBI.ClobbersPred) DoSwap = true; else if (TrueBBI.ClobbersPred == FalseBBI.ClobbersPred) { if (TrueBBI.NonPredSize > FalseBBI.NonPredSize) DoSwap = true; } if (DoSwap) { std::swap(BBI1, BBI2); std::swap(Cond1, Cond2); } // Remove the conditional branch from entry to the blocks. BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB); // Remove the duplicated instructions at the beginnings of both paths. MachineBasicBlock::iterator DI1 = BBI1->BB->begin(); MachineBasicBlock::iterator DI2 = BBI2->BB->begin(); BBI1->NonPredSize -= NumDups1; BBI2->NonPredSize -= NumDups1; while (NumDups1 != 0) { ++DI1; ++DI2; --NumDups1; } BBI.BB->splice(BBI.BB->end(), BBI1->BB, BBI1->BB->begin(), DI1); BBI2->BB->erase(BBI2->BB->begin(), DI2); // Predicate the 'true' block after removing its branch. BBI1->NonPredSize -= TII->RemoveBranch(*BBI1->BB); DI1 = BBI1->BB->end(); for (unsigned i = 0; i != NumDups2; ++i) --DI1; BBI1->BB->erase(DI1, BBI1->BB->end()); PredicateBlock(*BBI1, BBI1->BB->end(), *Cond1); // Predicate the 'false' block. BBI2->NonPredSize -= TII->RemoveBranch(*BBI2->BB); DI2 = BBI2->BB->end(); while (NumDups2 != 0) { --DI2; --NumDups2; } PredicateBlock(*BBI2, DI2, *Cond2); // Merge the true block into the entry of the diamond. MergeBlocks(BBI, *BBI1); MergeBlocks(BBI, *BBI2); // If the if-converted block falls through or unconditionally branches into // the tail block, and the tail block does not have other predecessors, then // fold the tail block in as well. Otherwise, unless it falls through to the // tail, add a unconditional branch to it. if (TailBB) { BBInfo TailBBI = BBAnalysis[TailBB->getNumber()]; if (TailBB->pred_size() == 1 && !TailBBI.HasFallThrough) { BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB); MergeBlocks(BBI, TailBBI); TailBBI.IsDone = true; } else { InsertUncondBranch(BBI.BB, TailBB, TII); BBI.HasFallThrough = false; } } RemoveExtraEdges(BBI); // Update block info. BBI.IsDone = TrueBBI.IsDone = FalseBBI.IsDone = true; InvalidatePreds(BBI.BB); // FIXME: Must maintain LiveIns. return true; }
bool HexagonEarlyIfConversion::isProfitable(const FlowPattern &FP) const { if (FP.TrueB && FP.FalseB) { // Do not IfCovert if the branch is one sided. if (MBPI) { BranchProbability Prob(9, 10); if (MBPI->getEdgeProbability(FP.SplitB, FP.TrueB) > Prob) return false; if (MBPI->getEdgeProbability(FP.SplitB, FP.FalseB) > Prob) return false; } // If both sides are predicable, convert them if they join, and the // join block has no other predecessors. MachineBasicBlock *TSB = *FP.TrueB->succ_begin(); MachineBasicBlock *FSB = *FP.FalseB->succ_begin(); if (TSB != FSB) return false; if (TSB->pred_size() != 2) return false; } // Calculate the total size of the predicated blocks. // Assume instruction counts without branches to be the approximation of // the code size. If the predicated blocks are smaller than a packet size, // approximate the spare room in the packet that could be filled with the // predicated/speculated instructions. unsigned TS = 0, FS = 0, Spare = 0; if (FP.TrueB) { TS = std::distance(FP.TrueB->begin(), FP.TrueB->getFirstTerminator()); if (TS < HEXAGON_PACKET_SIZE) Spare += HEXAGON_PACKET_SIZE-TS; } if (FP.FalseB) { FS = std::distance(FP.FalseB->begin(), FP.FalseB->getFirstTerminator()); if (FS < HEXAGON_PACKET_SIZE) Spare += HEXAGON_PACKET_SIZE-TS; } unsigned TotalIn = TS+FS; DEBUG(dbgs() << "Total number of instructions to be predicated/speculated: " << TotalIn << ", spare room: " << Spare << "\n"); if (TotalIn >= SizeLimit+Spare) return false; // Count the number of PHI nodes that will need to be updated (converted // to MUX). Those can be later converted to predicated instructions, so // they aren't always adding extra cost. // KLUDGE: Also, count the number of predicate register definitions in // each block. The scheduler may increase the pressure of these and cause // expensive spills (e.g. bitmnp01). unsigned TotalPh = 0; unsigned PredDefs = countPredicateDefs(FP.SplitB); if (FP.JoinB) { TotalPh = computePhiCost(FP.JoinB); PredDefs += countPredicateDefs(FP.JoinB); } else { if (FP.TrueB && FP.TrueB->succ_size() > 0) { MachineBasicBlock *SB = *FP.TrueB->succ_begin(); TotalPh += computePhiCost(SB); PredDefs += countPredicateDefs(SB); } if (FP.FalseB && FP.FalseB->succ_size() > 0) { MachineBasicBlock *SB = *FP.FalseB->succ_begin(); TotalPh += computePhiCost(SB); PredDefs += countPredicateDefs(SB); } } DEBUG(dbgs() << "Total number of extra muxes from converted phis: " << TotalPh << "\n"); if (TotalIn+TotalPh >= SizeLimit+Spare) return false; DEBUG(dbgs() << "Total number of predicate registers: " << PredDefs << "\n"); if (PredDefs > 4) return false; return true; }
bool HexagonEarlyIfConversion::matchFlowPattern(MachineBasicBlock *B, MachineLoop *L, FlowPattern &FP) { DEBUG(dbgs() << "Checking flow pattern at BB#" << B->getNumber() << "\n"); // Interested only in conditional branches, no .new, no new-value, etc. // Check the terminators directly, it's easier than handling all responses // from AnalyzeBranch. MachineBasicBlock *TB = 0, *FB = 0; MachineBasicBlock::const_iterator T1I = B->getFirstTerminator(); if (T1I == B->end()) return false; unsigned Opc = T1I->getOpcode(); if (Opc != Hexagon::J2_jumpt && Opc != Hexagon::J2_jumpf) return false; unsigned PredR = T1I->getOperand(0).getReg(); // Get the layout successor, or 0 if B does not have one. MachineFunction::iterator NextBI = std::next(MachineFunction::iterator(B)); MachineBasicBlock *NextB = (NextBI != MFN->end()) ? &*NextBI : 0; MachineBasicBlock *T1B = T1I->getOperand(1).getMBB(); MachineBasicBlock::const_iterator T2I = std::next(T1I); // The second terminator should be an unconditional branch. assert(T2I == B->end() || T2I->getOpcode() == Hexagon::J2_jump); MachineBasicBlock *T2B = (T2I == B->end()) ? NextB : T2I->getOperand(0).getMBB(); if (T1B == T2B) { // XXX merge if T1B == NextB, or convert branch to unconditional. // mark as diamond with both sides equal? return false; } // Loop could be null for both. if (MLI->getLoopFor(T1B) != L || MLI->getLoopFor(T2B) != L) return false; // Record the true/false blocks in such a way that "true" means "if (PredR)", // and "false" means "if (!PredR)". if (Opc == Hexagon::J2_jumpt) TB = T1B, FB = T2B; else TB = T2B, FB = T1B; if (!MDT->properlyDominates(B, TB) || !MDT->properlyDominates(B, FB)) return false; // Detect triangle first. In case of a triangle, one of the blocks TB/FB // can fall through into the other, in other words, it will be executed // in both cases. We only want to predicate the block that is executed // conditionally. unsigned TNP = TB->pred_size(), FNP = FB->pred_size(); unsigned TNS = TB->succ_size(), FNS = FB->succ_size(); // A block is predicable if it has one predecessor (it must be B), and // it has a single successor. In fact, the block has to end either with // an unconditional branch (which can be predicated), or with a fall- // through. bool TOk = (TNP == 1) && (TNS == 1); bool FOk = (FNP == 1) && (FNS == 1); // If neither is predicable, there is nothing interesting. if (!TOk && !FOk) return false; MachineBasicBlock *TSB = (TNS > 0) ? *TB->succ_begin() : 0; MachineBasicBlock *FSB = (FNS > 0) ? *FB->succ_begin() : 0; MachineBasicBlock *JB = 0; if (TOk) { if (FOk) { if (TSB == FSB) JB = TSB; // Diamond: "if (P) then TB; else FB;". } else { // TOk && !FOk if (TSB == FB) { JB = FB; FB = 0; } } } else { // !TOk && FOk (at least one must be true by now). if (FSB == TB) { JB = TB; TB = 0; } } // Don't try to predicate loop preheaders. if ((TB && isPreheader(TB)) || (FB && isPreheader(FB))) { DEBUG(dbgs() << "One of blocks " << PrintMB(TB) << ", " << PrintMB(FB) << " is a loop preheader. Skipping.\n"); return false; } FP = FlowPattern(B, PredR, TB, FB, JB); DEBUG(dbgs() << "Detected " << PrintFP(FP, *TRI) << "\n"); return true; }
/// SinkInstruction - Determine whether it is safe to sink the specified machine /// instruction out of its current block into a successor. bool MachineSinking::SinkInstruction(MachineInstr *MI, bool &SawStore) { // Check if it's safe to move the instruction. if (!MI->isSafeToMove(TII, AA, SawStore)) return false; // FIXME: This should include support for sinking instructions within the // block they are currently in to shorten the live ranges. We often get // instructions sunk into the top of a large block, but it would be better to // also sink them down before their first use in the block. This xform has to // be careful not to *increase* register pressure though, e.g. sinking // "x = y + z" down if it kills y and z would increase the live ranges of y // and z and only shrink the live range of x. // Loop over all the operands of the specified instruction. If there is // anything we can't handle, bail out. MachineBasicBlock *ParentBlock = MI->getParent(); // SuccToSinkTo - This is the successor to sink this instruction to, once we // decide. MachineBasicBlock *SuccToSinkTo = 0; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); if (!MO.isReg()) continue; // Ignore non-register operands. unsigned Reg = MO.getReg(); if (Reg == 0) continue; if (TargetRegisterInfo::isPhysicalRegister(Reg)) { if (MO.isUse()) { // If the physreg has no defs anywhere, it's just an ambient register // and we can freely move its uses. Alternatively, if it's allocatable, // it could get allocated to something with a def during allocation. if (!RegInfo->def_empty(Reg)) return false; if (AllocatableSet.test(Reg)) return false; // Check for a def among the register's aliases too. for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { unsigned AliasReg = *Alias; if (!RegInfo->def_empty(AliasReg)) return false; if (AllocatableSet.test(AliasReg)) return false; } } else if (!MO.isDead()) { // A def that isn't dead. We can't move it. return false; } } else { // Virtual register uses are always safe to sink. if (MO.isUse()) continue; // If it's not safe to move defs of the register class, then abort. if (!TII->isSafeToMoveRegClassDefs(RegInfo->getRegClass(Reg))) return false; // FIXME: This picks a successor to sink into based on having one // successor that dominates all the uses. However, there are cases where // sinking can happen but where the sink point isn't a successor. For // example: // x = computation // if () {} else {} // use x // the instruction could be sunk over the whole diamond for the // if/then/else (or loop, etc), allowing it to be sunk into other blocks // after that. // Virtual register defs can only be sunk if all their uses are in blocks // dominated by one of the successors. if (SuccToSinkTo) { // If a previous operand picked a block to sink to, then this operand // must be sinkable to the same block. if (!AllUsesDominatedByBlock(Reg, SuccToSinkTo)) return false; continue; } // Otherwise, we should look at all the successors and decide which one // we should sink to. for (MachineBasicBlock::succ_iterator SI = ParentBlock->succ_begin(), E = ParentBlock->succ_end(); SI != E; ++SI) { if (AllUsesDominatedByBlock(Reg, *SI)) { SuccToSinkTo = *SI; break; } } // If we couldn't find a block to sink to, ignore this instruction. if (SuccToSinkTo == 0) return false; } } // If there are no outputs, it must have side-effects. if (SuccToSinkTo == 0) return false; // It's not safe to sink instructions to EH landing pad. Control flow into // landing pad is implicitly defined. if (SuccToSinkTo->isLandingPad()) return false; // It is not possible to sink an instruction into its own block. This can // happen with loops. if (MI->getParent() == SuccToSinkTo) return false; DEBUG(dbgs() << "Sink instr " << *MI); DEBUG(dbgs() << "to block " << *SuccToSinkTo); // If the block has multiple predecessors, this would introduce computation on // a path that it doesn't already exist. We could split the critical edge, // but for now we just punt. // FIXME: Split critical edges if not backedges. if (SuccToSinkTo->pred_size() > 1) { DEBUG(dbgs() << " *** PUNTING: Critical edge found\n"); return false; } // Determine where to insert into. Skip phi nodes. MachineBasicBlock::iterator InsertPos = SuccToSinkTo->begin(); while (InsertPos != SuccToSinkTo->end() && InsertPos->isPHI()) ++InsertPos; // Move the instruction. SuccToSinkTo->splice(InsertPos, ParentBlock, MI, ++MachineBasicBlock::iterator(MI)); return true; }
/// SinkInstruction - Determine whether it is safe to sink the specified machine /// instruction out of its current block into a successor. bool MachineSinking::SinkInstruction(MachineInstr *MI, bool &SawStore) { // Don't sink insert_subreg, subreg_to_reg, reg_sequence. These are meant to // be close to the source to make it easier to coalesce. if (AvoidsSinking(MI, MRI)) return false; // Check if it's safe to move the instruction. if (!MI->isSafeToMove(TII, AA, SawStore)) return false; // FIXME: This should include support for sinking instructions within the // block they are currently in to shorten the live ranges. We often get // instructions sunk into the top of a large block, but it would be better to // also sink them down before their first use in the block. This xform has to // be careful not to *increase* register pressure though, e.g. sinking // "x = y + z" down if it kills y and z would increase the live ranges of y // and z and only shrink the live range of x. // Loop over all the operands of the specified instruction. If there is // anything we can't handle, bail out. MachineBasicBlock *ParentBlock = MI->getParent(); // SuccToSinkTo - This is the successor to sink this instruction to, once we // decide. MachineBasicBlock *SuccToSinkTo = 0; bool BreakPHIEdge = false; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); if (!MO.isReg()) continue; // Ignore non-register operands. unsigned Reg = MO.getReg(); if (Reg == 0) continue; if (TargetRegisterInfo::isPhysicalRegister(Reg)) { if (MO.isUse()) { // If the physreg has no defs anywhere, it's just an ambient register // and we can freely move its uses. Alternatively, if it's allocatable, // it could get allocated to something with a def during allocation. if (!MRI->def_empty(Reg)) return false; if (AllocatableSet.test(Reg)) return false; // Check for a def among the register's aliases too. for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { unsigned AliasReg = *Alias; if (!MRI->def_empty(AliasReg)) return false; if (AllocatableSet.test(AliasReg)) return false; } } else if (!MO.isDead()) { // A def that isn't dead. We can't move it. return false; } } else { // Virtual register uses are always safe to sink. if (MO.isUse()) continue; // If it's not safe to move defs of the register class, then abort. if (!TII->isSafeToMoveRegClassDefs(MRI->getRegClass(Reg))) return false; // FIXME: This picks a successor to sink into based on having one // successor that dominates all the uses. However, there are cases where // sinking can happen but where the sink point isn't a successor. For // example: // // x = computation // if () {} else {} // use x // // the instruction could be sunk over the whole diamond for the // if/then/else (or loop, etc), allowing it to be sunk into other blocks // after that. // Virtual register defs can only be sunk if all their uses are in blocks // dominated by one of the successors. if (SuccToSinkTo) { // If a previous operand picked a block to sink to, then this operand // must be sinkable to the same block. bool LocalUse = false; if (!AllUsesDominatedByBlock(Reg, SuccToSinkTo, ParentBlock, BreakPHIEdge, LocalUse)) return false; continue; } // Otherwise, we should look at all the successors and decide which one // we should sink to. for (MachineBasicBlock::succ_iterator SI = ParentBlock->succ_begin(), E = ParentBlock->succ_end(); SI != E; ++SI) { bool LocalUse = false; if (AllUsesDominatedByBlock(Reg, *SI, ParentBlock, BreakPHIEdge, LocalUse)) { SuccToSinkTo = *SI; break; } if (LocalUse) // Def is used locally, it's never safe to move this def. return false; } // If we couldn't find a block to sink to, ignore this instruction. if (SuccToSinkTo == 0) return false; } } // If there are no outputs, it must have side-effects. if (SuccToSinkTo == 0) return false; // It's not safe to sink instructions to EH landing pad. Control flow into // landing pad is implicitly defined. if (SuccToSinkTo->isLandingPad()) return false; // It is not possible to sink an instruction into its own block. This can // happen with loops. if (MI->getParent() == SuccToSinkTo) return false; // If the instruction to move defines a dead physical register which is live // when leaving the basic block, don't move it because it could turn into a // "zombie" define of that preg. E.g., EFLAGS. (<rdar://problem/8030636>) for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) { const MachineOperand &MO = MI->getOperand(I); if (!MO.isReg()) continue; unsigned Reg = MO.getReg(); if (Reg == 0 || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue; if (SuccToSinkTo->isLiveIn(Reg)) return false; } DEBUG(dbgs() << "Sink instr " << *MI << "\tinto block " << *SuccToSinkTo); // If the block has multiple predecessors, this would introduce computation on // a path that it doesn't already exist. We could split the critical edge, // but for now we just punt. if (SuccToSinkTo->pred_size() > 1) { // We cannot sink a load across a critical edge - there may be stores in // other code paths. bool TryBreak = false; bool store = true; if (!MI->isSafeToMove(TII, AA, store)) { DEBUG(dbgs() << " *** NOTE: Won't sink load along critical edge.\n"); TryBreak = true; } // We don't want to sink across a critical edge if we don't dominate the // successor. We could be introducing calculations to new code paths. if (!TryBreak && !DT->dominates(ParentBlock, SuccToSinkTo)) { DEBUG(dbgs() << " *** NOTE: Critical edge found\n"); TryBreak = true; } // Don't sink instructions into a loop. if (!TryBreak && LI->isLoopHeader(SuccToSinkTo)) { DEBUG(dbgs() << " *** NOTE: Loop header found\n"); TryBreak = true; } // Otherwise we are OK with sinking along a critical edge. if (!TryBreak) DEBUG(dbgs() << "Sinking along critical edge.\n"); else { MachineBasicBlock *NewSucc = SplitCriticalEdge(MI, ParentBlock, SuccToSinkTo, BreakPHIEdge); if (!NewSucc) { DEBUG(dbgs() << " *** PUNTING: Not legal or profitable to " "break critical edge\n"); return false; } else { DEBUG(dbgs() << " *** Splitting critical edge:" " BB#" << ParentBlock->getNumber() << " -- BB#" << NewSucc->getNumber() << " -- BB#" << SuccToSinkTo->getNumber() << '\n'); SuccToSinkTo = NewSucc; ++NumSplit; BreakPHIEdge = false; } } } if (BreakPHIEdge) { // BreakPHIEdge is true if all the uses are in the successor MBB being // sunken into and they are all PHI nodes. In this case, machine-sink must // break the critical edge first. MachineBasicBlock *NewSucc = SplitCriticalEdge(MI, ParentBlock, SuccToSinkTo, BreakPHIEdge); if (!NewSucc) { DEBUG(dbgs() << " *** PUNTING: Not legal or profitable to " "break critical edge\n"); return false; } DEBUG(dbgs() << " *** Splitting critical edge:" " BB#" << ParentBlock->getNumber() << " -- BB#" << NewSucc->getNumber() << " -- BB#" << SuccToSinkTo->getNumber() << '\n'); SuccToSinkTo = NewSucc; ++NumSplit; } // Determine where to insert into. Skip phi nodes. MachineBasicBlock::iterator InsertPos = SuccToSinkTo->begin(); while (InsertPos != SuccToSinkTo->end() && InsertPos->isPHI()) ++InsertPos; // collect matching debug values. SmallVector<MachineInstr *, 2> DbgValuesToSink; collectDebugValues(MI, DbgValuesToSink); // Move the instruction. SuccToSinkTo->splice(InsertPos, ParentBlock, MI, ++MachineBasicBlock::iterator(MI)); // Move debug values. for (SmallVector<MachineInstr *, 2>::iterator DBI = DbgValuesToSink.begin(), DBE = DbgValuesToSink.end(); DBI != DBE; ++DBI) { MachineInstr *DbgMI = *DBI; SuccToSinkTo->splice(InsertPos, ParentBlock, DbgMI, ++MachineBasicBlock::iterator(DbgMI)); } // Conservatively, clear any kill flags, since it's possible that they are no // longer correct. MI->clearKillInfo(); return true; }