int ZONE_CONTAINER::GetClearance( BOARD_CONNECTED_ITEM* aItem ) const
{
int myClearance = m_ZoneClearance;
#if 0 // Maybe the netclass clearance should not come into play for a zone?
// At least the policy decision can be controlled by the zone
// itself, i.e. here. On reasons of insufficient documentation,
// the user will be less bewildered if we simply respect the
// "zone clearance" setting in the zone properties dialog. (At least
// until there is a UI boolean for this.)
NETCLASSPTR myClass = GetNetClass();
if( myClass )
myClearance = std::max( myClearance, myClass->GetClearance() );
#endif
if( aItem )
{
int hisClearance = aItem->GetClearance( NULL );
myClearance = std::max( hisClearance, myClearance );
}
return myClearance;
}
PNS_PCBNEW_CLEARANCE_RESOLVER::PNS_PCBNEW_CLEARANCE_RESOLVER( PNS_ROUTER* aRouter ) :
m_router( aRouter )
{
BOARD* brd = m_router->GetBoard();
m_clearanceCache.resize( brd->GetNetCount() );
m_useDpGap = false;
for( unsigned int i = 0; i < brd->GetNetCount(); i++ )
{
NETINFO_ITEM* ni = brd->FindNet( i );
if( ni == NULL )
continue;
CLEARANCE_ENT ent;
ent.coupledNet = m_router->GetWorld()->PairedNet( i );
wxString netClassName = ni->GetClassName();
NETCLASSPTR nc = brd->GetDesignSettings().m_NetClasses.Find( netClassName );
int clearance = nc->GetClearance();
ent.clearance = clearance;
m_clearanceCache[i] = ent;
TRACE( 1, "Add net %d netclass %s clearance %d", i % netClassName.mb_str() %
clearance );
}
m_overrideEnabled = false;
m_defaultClearance = Millimeter2iu( 0.254 ); // aBoard->m_NetClasses.Find ("Default clearance")->GetClearance();
m_overrideNetA = 0;
m_overrideNetB = 0;
m_overrideClearance = 0;
}
PNS_PCBNEW_RULE_RESOLVER::PNS_PCBNEW_RULE_RESOLVER( BOARD* aBoard, PNS::ROUTER* aRouter ) :
m_router( aRouter ),
m_board( aBoard )
{
PNS::NODE* world = m_router->GetWorld();
PNS::TOPOLOGY topo( world );
m_netClearanceCache.resize( m_board->GetNetCount() );
// Build clearance cache for net classes
for( unsigned int i = 0; i < m_board->GetNetCount(); i++ )
{
NETINFO_ITEM* ni = m_board->FindNet( i );
if( ni == NULL )
continue;
CLEARANCE_ENT ent;
ent.coupledNet = DpCoupledNet( i );
wxString netClassName = ni->GetClassName();
NETCLASSPTR nc = m_board->GetDesignSettings().m_NetClasses.Find( netClassName );
int clearance = nc->GetClearance();
ent.clearance = clearance;
m_netClearanceCache[i] = ent;
wxLogTrace( "PNS", "Add net %u netclass %s clearance %d", i, netClassName.mb_str(), clearance );
}
// Build clearance cache for pads
for( MODULE* mod = m_board->m_Modules; mod ; mod = mod->Next() )
{
auto moduleClearance = mod->GetLocalClearance();
for( D_PAD* pad = mod->PadsList(); pad; pad = pad->Next() )
{
int padClearance = pad->GetLocalClearance();
if( padClearance > 0 )
m_localClearanceCache[ pad ] = padClearance;
else if( moduleClearance > 0 )
m_localClearanceCache[ pad ] = moduleClearance;
}
}
//printf("DefaultCL : %d\n", m_board->GetDesignSettings().m_NetClasses.Find ("Default clearance")->GetClearance());
m_overrideEnabled = false;
m_defaultClearance = Millimeter2iu( 0.254 ); // m_board->m_NetClasses.Find ("Default clearance")->GetClearance();
m_overrideNetA = 0;
m_overrideNetB = 0;
m_overrideClearance = 0;
m_useDpGap = false;
}
bool PNS_DIFF_PAIR_PLACER::Start( const VECTOR2I& aP, PNS_ITEM* aStartItem )
{
VECTOR2I p( aP );
if( !aStartItem )
{
Router()->SetFailureReason( _( "Can't start a differential pair "
" in the middle of nowhere." ) );
return false;
}
setWorld( Router()->GetWorld() );
m_currentNode = m_world;
if( !findDpPrimitivePair( aP, aStartItem, m_start ) )
{
Router()->SetFailureReason( _( "Unable to find complementary differential pair "
"net. Make sure the names of the nets belonging "
"to a differential pair end with either _N/_P or +/-." ) );
return false;
}
m_netP = m_start.PrimP()->Net();
m_netN = m_start.PrimN()->Net();
#if 0
// FIXME: this also needs to be factored out but not so important right now
// Check if the current track/via gap & track width settings are violated
BOARD* brd = NULL; // FIXME Router()->GetBoard();
NETCLASSPTR netclassP = brd->FindNet( m_netP )->GetNetClass();
NETCLASSPTR netclassN = brd->FindNet( m_netN )->GetNetClass();
int clearance = std::min( m_sizes.DiffPairGap(), m_sizes.DiffPairViaGap() );
if( clearance < netclassP->GetClearance() || clearance < netclassN->GetClearance() )
{
Router()->SetFailureReason( _( "Current track/via gap setting violates "
"design rules for this net." ) );
return false;
}
if( m_sizes.DiffPairWidth() < brd->GetDesignSettings().m_TrackMinWidth )
{
Router()->SetFailureReason( _( "Current track width setting violates design rules." ) );
return false;
}
#endif
m_currentStart = p;
m_currentEnd = p;
m_placingVia = false;
m_chainedPlacement = false;
initPlacement();
return true;
}
int BOARD_DESIGN_SETTINGS::GetSmallestClearanceValue()
{
int clearance = m_NetClasses.GetDefault()->GetClearance();
//Read list of Net Classes
for( NETCLASSES::const_iterator nc = m_NetClasses.begin(); nc != m_NetClasses.end(); ++nc )
{
NETCLASSPTR netclass = nc->second;
clearance = std::min( clearance, netclass->GetClearance() );
}
return clearance;
}
int VIA::GetDrillValue() const
{
if( m_Drill > 0 ) // Use the specific value.
return m_Drill;
// Use the default value from the Netclass
NETCLASSPTR netclass = GetNetClass();
if( GetViaType() == VIA_MICROVIA )
return netclass->GetuViaDrill();
return netclass->GetViaDrill();
}
bool NETCLASSES::Add( NETCLASSPTR aNetClass )
{
const wxString& name = aNetClass->GetName();
if( name == NETCLASS::Default )
{
// invoke operator=(), which is currently generated by compiler.
m_Default = aNetClass;
return true;
}
// Test for an existing netclass:
if( !Find( name ) )
{
// name not found, take ownership
m_NetClasses[name] = aNetClass;
return true;
}
else
{
// name already exists
// do not "take ownership" and return false telling caller such.
return false;
}
}
static void class2gridRow( wxGrid* grid, int row, NETCLASSPTR nc )
{
wxString msg;
// label is netclass name
grid->SetRowLabelValue( row, nc->GetName() );
msg = StringFromValue( g_UserUnit, nc->GetClearance() );
grid->SetCellValue( row, GRID_CLEARANCE, msg );
msg = StringFromValue( g_UserUnit, nc->GetTrackWidth() );
grid->SetCellValue( row, GRID_TRACKSIZE, msg );
msg = StringFromValue( g_UserUnit, nc->GetViaDiameter() );
grid->SetCellValue( row, GRID_VIASIZE, msg );
msg = StringFromValue( g_UserUnit, nc->GetViaDrill() );
grid->SetCellValue( row, GRID_VIADRILL, msg );
msg = StringFromValue( g_UserUnit, nc->GetuViaDiameter() );
grid->SetCellValue( row, GRID_uVIASIZE, msg );
msg = StringFromValue( g_UserUnit, nc->GetuViaDrill() );
grid->SetCellValue( row, GRID_uVIADRILL, msg );
}
bool BOARD_DESIGN_SETTINGS::SetCurrentNetClass( const wxString& aNetClassName )
{
NETCLASSPTR netClass = m_NetClasses.Find( aNetClassName );
bool lists_sizes_modified = false;
// if not found (should not happen) use the default
if( netClass == NULL )
netClass = m_NetClasses.GetDefault();
m_currentNetClassName = netClass->GetName();
// Initialize others values:
if( m_ViasDimensionsList.size() == 0 )
{
VIA_DIMENSION viadim;
lists_sizes_modified = true;
m_ViasDimensionsList.push_back( viadim );
}
if( m_TrackWidthList.size() == 0 )
{
lists_sizes_modified = true;
m_TrackWidthList.push_back( 0 );
}
/* note the m_ViasDimensionsList[0] and m_TrackWidthList[0] values
* are always the Netclass values
*/
if( m_ViasDimensionsList[0].m_Diameter != netClass->GetViaDiameter() )
{
lists_sizes_modified = true;
m_ViasDimensionsList[0].m_Diameter = netClass->GetViaDiameter();
}
if( m_ViasDimensionsList[0].m_Drill != netClass->GetViaDrill() )
{
lists_sizes_modified = true;
m_ViasDimensionsList[0].m_Drill = netClass->GetViaDrill();
}
if( m_TrackWidthList[0] != netClass->GetTrackWidth() )
{
lists_sizes_modified = true;
m_TrackWidthList[0] = netClass->GetTrackWidth();
}
if( GetViaSizeIndex() >= m_ViasDimensionsList.size() )
SetViaSizeIndex( m_ViasDimensionsList.size() );
if( GetTrackWidthIndex() >= m_TrackWidthList.size() )
SetTrackWidthIndex( m_TrackWidthList.size() );
return lists_sizes_modified;
}
void ROUTER_TOOL::getNetclassDimensions( int aNetCode, int& aWidth,
int& aViaDiameter, int& aViaDrill )
{
BOARD_DESIGN_SETTINGS &bds = m_board->GetDesignSettings();
NETCLASSPTR netClass;
NETINFO_ITEM* ni = m_board->FindNet( aNetCode );
if( ni )
{
wxString netClassName = ni->GetClassName();
netClass = bds.m_NetClasses.Find( netClassName );
}
if( !netClass )
netClass = bds.GetDefault();
aWidth = netClass->GetTrackWidth();
aViaDiameter = netClass->GetViaDiameter();
aViaDrill = netClass->GetViaDrill();
}
void DIALOG_DESIGN_RULES::CopyRulesListToBoard()
{
NETCLASSES& netclasses = m_BrdSettings->m_NetClasses;
// Remove all netclasses from board. We'll copy new list after
netclasses.Clear();
// Copy the default NetClass:
gridRow2class( m_grid, 0, netclasses.GetDefault() );
// Copy other NetClasses :
for( int row = 1; row < m_grid->GetNumberRows(); ++row )
{
NETCLASSPTR nc = boost::make_shared<NETCLASS>( m_grid->GetRowLabelValue( row ) );
if( !m_BrdSettings->m_NetClasses.Add( nc ) )
{
// this netclass cannot be added because an other netclass with the same name exists
// Should not occur because OnAddNetclassClick() tests for existing NetClass names
wxString msg;
msg.Printf( wxT( "CopyRulesListToBoard(): The NetClass \"%s\" already exists. Skip" ),
GetChars( m_grid->GetRowLabelValue( row ) ) );
wxMessageBox( msg );
continue;
}
gridRow2class( m_grid, row, nc );
}
// Now read all nets and push them in the corresponding netclass net buffer
for( NETCUPS::const_iterator netcup = m_AllNets.begin(); netcup != m_AllNets.end(); ++netcup )
{
NETCLASSPTR nc = netclasses.Find( netcup->clazz );
wxASSERT( nc );
nc->Add( netcup->net );
}
m_Pcb->SynchronizeNetsAndNetClasses();
}
static void gridRow2class( wxGrid* grid, int row, NETCLASSPTR nc )
{
#define MYCELL( col ) \
ValueFromString( g_UserUnit, grid->GetCellValue( row, col ) )
nc->SetClearance( MYCELL( GRID_CLEARANCE ) );
nc->SetTrackWidth( MYCELL( GRID_TRACKSIZE ) );
nc->SetViaDiameter( MYCELL( GRID_VIASIZE ) );
nc->SetViaDrill( MYCELL( GRID_VIADRILL ) );
nc->SetuViaDiameter( MYCELL( GRID_uVIASIZE ) );
nc->SetuViaDrill( MYCELL( GRID_uVIADRILL ) );
}
// see class_track.h
void TRACK::GetMsgPanelInfo( std::vector< MSG_PANEL_ITEM >& aList )
{
wxString msg;
BOARD* board = GetBoard();
// Display basic infos
GetMsgPanelInfoBase( aList );
// Display full track length (in Pcbnew)
if( board )
{
double trackLen = 0;
double lenPadToDie = 0;
board->MarkTrace( this, NULL, &trackLen, &lenPadToDie, false );
msg = ::CoordinateToString( trackLen );
aList.push_back( MSG_PANEL_ITEM( _( "Track Len" ), msg, DARKCYAN ) );
if( lenPadToDie != 0 )
{
msg = ::LengthDoubleToString( trackLen + lenPadToDie );
aList.push_back( MSG_PANEL_ITEM( _( "Full Len" ), msg, DARKCYAN ) );
msg = ::LengthDoubleToString( lenPadToDie );
aList.push_back( MSG_PANEL_ITEM( _( "In Package" ), msg, DARKCYAN ) );
}
}
NETCLASSPTR netclass = GetNetClass();
if( netclass )
{
aList.push_back( MSG_PANEL_ITEM( _( "NC Name" ), netclass->GetName(), DARKMAGENTA ) );
aList.push_back( MSG_PANEL_ITEM( _( "NC Clearance" ),
::CoordinateToString( netclass->GetClearance(), true ),
DARKMAGENTA ) );
aList.push_back( MSG_PANEL_ITEM( _( "NC Width" ),
::CoordinateToString( netclass->GetTrackWidth(), true ),
DARKMAGENTA ) );
aList.push_back( MSG_PANEL_ITEM( _( "NC Via Size" ),
::CoordinateToString( netclass->GetViaDiameter(), true ),
DARKMAGENTA ) );
aList.push_back( MSG_PANEL_ITEM( _( "NC Via Drill"),
::CoordinateToString( netclass->GetViaDrill(), true ),
DARKMAGENTA ) );
}
}
void DIALOG_DESIGN_RULES::InitDialogRules()
{
// @todo: Move the initialization code into TransferDataToWindow() to follow wxWidgets
// dialog data transfer convention.
SetFocus();
SetReturnCode( 0 );
m_Pcb = m_Parent->GetBoard();
m_BrdSettings = &m_Pcb->GetDesignSettings();
// Initialize the Rules List
InitRulesList();
// copy all NETs into m_AllNets by adding them as NETCUPs.
// @todo go fix m_Pcb->SynchronizeNetsAndNetClasses() so that the netcode==0 is not
// present in the BOARD::m_NetClasses
NETCLASSES& netclasses = m_BrdSettings->m_NetClasses;
NETCLASSPTR netclass = netclasses.GetDefault();
// Initialize list of nets for Default Net Class
for( NETCLASS::iterator name = netclass->begin(); name != netclass->end(); ++name )
{
m_AllNets.push_back( NETCUP( *name, netclass->GetName() ) );
}
// Initialize list of nets for others (custom) Net Classes
for( NETCLASSES::const_iterator nc = netclasses.begin(); nc != netclasses.end(); ++nc )
{
netclass = nc->second;
for( NETCLASS::const_iterator name = netclass->begin(); name != netclass->end(); ++name )
{
m_AllNets.push_back( NETCUP( *name, netclass->GetName() ) );
}
}
InitializeRulesSelectionBoxes();
InitGlobalRules();
}
void BOARD::SynchronizeNetsAndNetClasses()
{
NETCLASSES& netClasses = m_designSettings.m_NetClasses;
// set all NETs to the default NETCLASS, then later override some
// as we go through the NETCLASSes.
for( NETINFO_LIST::iterator net( m_NetInfo.begin() ), netEnd( m_NetInfo.end() );
net != netEnd; ++net )
{
net->SetClass( netClasses.GetDefault() );
}
// Add netclass name and pointer to nets. If a net is in more than one netclass,
// set the net's name and pointer to only the first netclass. Subsequent
// and therefore bogus netclass memberships will be deleted in logic below this loop.
for( NETCLASSES::iterator clazz = netClasses.begin(); clazz != netClasses.end(); ++clazz )
{
NETCLASSPTR netclass = clazz->second;
for( NETCLASS::const_iterator member = netclass->begin(); member != netclass->end(); ++member )
{
const wxString& netname = *member;
// although this overall function seems to be adequately fast,
// FindNet( wxString ) uses now a fast binary search and is fast
// event for large net lists
NETINFO_ITEM* net = FindNet( netname );
if( net && net->GetClassName() == NETCLASS::Default )
{
net->SetClass( netclass );
}
}
}
// Finally, make sure that every NET is in a NETCLASS, even if that
// means the Default NETCLASS. And make sure that all NETCLASSes do not
// contain netnames that do not exist, by deleting all netnames from
// every netclass and re-adding them.
for( NETCLASSES::iterator clazz = netClasses.begin(); clazz != netClasses.end(); ++clazz )
{
NETCLASSPTR netclass = clazz->second;
netclass->Clear();
}
netClasses.GetDefault()->Clear();
for( NETINFO_LIST::iterator net( m_NetInfo.begin() ), netEnd( m_NetInfo.end() );
net != netEnd; ++net )
{
const wxString& classname = net->GetClassName();
// because of the std:map<> this should be fast, and because of
// prior logic, netclass should not be NULL.
NETCLASSPTR netclass = netClasses.Find( classname );
wxASSERT( netclass );
netclass->Add( net->GetNetname() );
}
}
int BOARD_DESIGN_SETTINGS::GetCurrentMicroViaDrill()
{
NETCLASSPTR netclass = m_NetClasses.Find( m_currentNetClassName );
return netclass->GetuViaDrill();
}
bool DRC::doNetClass( NETCLASSPTR nc, wxString& msg )
{
bool ret = true;
const BOARD_DESIGN_SETTINGS& g = m_pcb->GetDesignSettings();
#define FmtVal( x ) GetChars( StringFromValue( g_UserUnit, x ) )
#if 0 // set to 1 when (if...) BOARD_DESIGN_SETTINGS has a m_MinClearance value
if( nc->GetClearance() < g.m_MinClearance )
{
msg.Printf( _( "NETCLASS: '%s' has Clearance:%s which is less than global:%s" ),
GetChars( nc->GetName() ),
FmtVal( nc->GetClearance() ),
FmtVal( g.m_TrackClearance )
);
addMarkerToPcb( fillMarker( DRCE_NETCLASS_CLEARANCE, msg, m_currentMarker ) );
m_currentMarker = nullptr;
ret = false;
}
#endif
if( nc->GetTrackWidth() < g.m_TrackMinWidth )
{
msg.Printf( _( "NETCLASS: '%s' has TrackWidth:%s which is less than global:%s" ),
GetChars( nc->GetName() ),
FmtVal( nc->GetTrackWidth() ),
FmtVal( g.m_TrackMinWidth )
);
addMarkerToPcb( fillMarker( DRCE_NETCLASS_TRACKWIDTH, msg, m_currentMarker ) );
m_currentMarker = nullptr;
ret = false;
}
if( nc->GetViaDiameter() < g.m_ViasMinSize )
{
msg.Printf( _( "NETCLASS: '%s' has Via Dia:%s which is less than global:%s" ),
GetChars( nc->GetName() ),
FmtVal( nc->GetViaDiameter() ),
FmtVal( g.m_ViasMinSize )
);
addMarkerToPcb( fillMarker( DRCE_NETCLASS_VIASIZE, msg, m_currentMarker ) );
m_currentMarker = nullptr;
ret = false;
}
if( nc->GetViaDrill() < g.m_ViasMinDrill )
{
msg.Printf( _( "NETCLASS: '%s' has Via Drill:%s which is less than global:%s" ),
GetChars( nc->GetName() ),
FmtVal( nc->GetViaDrill() ),
FmtVal( g.m_ViasMinDrill )
);
addMarkerToPcb( fillMarker( DRCE_NETCLASS_VIADRILLSIZE, msg, m_currentMarker ) );
m_currentMarker = nullptr;
ret = false;
}
if( nc->GetuViaDiameter() < g.m_MicroViasMinSize )
{
msg.Printf( _( "NETCLASS: '%s' has uVia Dia:%s which is less than global:%s" ),
GetChars( nc->GetName() ),
FmtVal( nc->GetuViaDiameter() ),
FmtVal( g.m_MicroViasMinSize )
);
addMarkerToPcb( fillMarker( DRCE_NETCLASS_uVIASIZE, msg, m_currentMarker ) );
m_currentMarker = nullptr;
ret = false;
}
if( nc->GetuViaDrill() < g.m_MicroViasMinDrill )
{
msg.Printf( _( "NETCLASS: '%s' has uVia Drill:%s which is less than global:%s" ),
GetChars( nc->GetName() ),
FmtVal( nc->GetuViaDrill() ),
FmtVal( g.m_MicroViasMinDrill )
);
addMarkerToPcb( fillMarker( DRCE_NETCLASS_uVIADRILLSIZE, msg, m_currentMarker ) );
m_currentMarker = nullptr;
ret = false;
}
return ret;
}
void SPECCTRA_DB::FromSESSION( BOARD* aBoard ) throw( IO_ERROR )
{
sessionBoard = aBoard; // not owned here
if( !session )
THROW_IO_ERROR( _("Session file is missing the \"session\" section") );
/* Dick 16-Jan-2012: session need not have a placement section.
if( !session->placement )
THROW_IO_ERROR( _("Session file is missing the \"placement\" section") );
*/
if( !session->route )
THROW_IO_ERROR( _("Session file is missing the \"routes\" section") );
if( !session->route->library )
THROW_IO_ERROR( _("Session file is missing the \"library_out\" section") );
// delete all the old tracks and vias
aBoard->m_Track.DeleteAll();
aBoard->DeleteMARKERs();
buildLayerMaps( aBoard );
if( session->placement )
{
// Walk the PLACEMENT object's COMPONENTs list, and for each PLACE within
// each COMPONENT, reposition and re-orient each component and put on
// correct side of the board.
COMPONENTS& components = session->placement->components;
for( COMPONENTS::iterator comp=components.begin(); comp!=components.end(); ++comp )
{
PLACES& places = comp->places;
for( unsigned i=0; i<places.size(); ++i )
{
PLACE* place = &places[i]; // '&' even though places[] holds a pointer!
wxString reference = FROM_UTF8( place->component_id.c_str() );
MODULE* module = aBoard->FindModuleByReference( reference );
if( !module )
{
THROW_IO_ERROR( wxString::Format( _("Session file has 'reference' to non-existent component \"%s\""),
GetChars( reference ) ) );
}
if( !place->hasVertex )
continue;
UNIT_RES* resolution = place->GetUnits();
wxASSERT( resolution );
wxPoint newPos = mapPt( place->vertex, resolution );
module->SetPosition( newPos );
if( place->side == T_front )
{
// convert from degrees to tenths of degrees used in KiCad.
int orientation = KiROUND( place->rotation * 10.0 );
if( module->GetLayer() != F_Cu )
{
// module is on copper layer (back)
module->Flip( module->GetPosition() );
}
module->SetOrientation( orientation );
}
else if( place->side == T_back )
{
int orientation = KiROUND( (place->rotation + 180.0) * 10.0 );
if( module->GetLayer() != B_Cu )
{
// module is on component layer (front)
module->Flip( module->GetPosition() );
}
module->SetOrientation( orientation );
}
else
{
// as I write this, the PARSER *is* catching this, so we should never see below:
wxFAIL_MSG( wxT("DSN::PARSER did not catch an illegal side := 'back|front'") );
}
}
}
}
routeResolution = session->route->GetUnits();
// Walk the NET_OUTs and create tracks and vias anew.
NET_OUTS& net_outs = session->route->net_outs;
for( NET_OUTS::iterator net = net_outs.begin(); net!=net_outs.end(); ++net )
{
int netCode = 0;
// page 143 of spec says wire's net_id is optional
if( net->net_id.size() )
{
wxString netName = FROM_UTF8( net->net_id.c_str() );
NETINFO_ITEM* netinfo = aBoard->FindNet( netName );
if( netinfo )
netCode = netinfo->GetNet();
else // else netCode remains 0
{
// int breakhere = 1;
}
}
WIRES& wires = net->wires;
for( unsigned i = 0; i<wires.size(); ++i )
{
WIRE* wire = &wires[i];
DSN_T shape = wire->shape->Type();
if( shape != T_path )
{
/* shape == T_polygon is expected from freerouter if you have
a zone on a non "power" type layer, i.e. a T_signal layer
and the design does a round trip back in as session here.
We kept our own zones in the BOARD, so ignore this so called
'wire'.
wxString netId = FROM_UTF8( wire->net_id.c_str() );
THROW_IO_ERROR( wxString::Format( _("Unsupported wire shape: \"%s\" for net: \"%s\""),
DLEX::GetTokenString(shape).GetData(),
netId.GetData()
) );
*/
}
else
{
PATH* path = (PATH*) wire->shape;
for( unsigned pt=0; pt<path->points.size()-1; ++pt )
{
/* a debugging aid, may come in handy
if( path->points[pt].x == 547800
&& path->points[pt].y == -380250 )
{
int breakhere = 1;
}
*/
TRACK* track = makeTRACK( path, pt, netCode );
aBoard->Add( track );
}
}
}
WIRE_VIAS& wire_vias = net->wire_vias;
LIBRARY& library = *session->route->library;
for( unsigned i=0; i<wire_vias.size(); ++i )
{
int netCode = 0;
// page 144 of spec says wire_via's net_id is optional
if( net->net_id.size() )
{
wxString netName = FROM_UTF8( net->net_id.c_str() );
NETINFO_ITEM* net = aBoard->FindNet( netName );
if( net )
netCode = net->GetNet();
// else netCode remains 0
}
WIRE_VIA* wire_via = &wire_vias[i];
// example: (via Via_15:8_mil 149000 -71000 )
PADSTACK* padstack = library.FindPADSTACK( wire_via->GetPadstackId() );
if( !padstack )
{
// Dick Feb 29, 2008:
// Freerouter has a bug where it will not round trip all vias.
// Vias which have a (use_via) element will be round tripped.
// Vias which do not, don't come back in in the session library,
// even though they may be actually used in the pre-routed,
// protected wire_vias. So until that is fixed, create the
// padstack from its name as a work around.
// Could use a STRING_FORMATTER here and convert the entire
// wire_via to text and put that text into the exception.
wxString psid( FROM_UTF8( wire_via->GetPadstackId().c_str() ) );
THROW_IO_ERROR( wxString::Format( _("A wire_via references a missing padstack \"%s\""),
GetChars( psid ) ) );
}
NETCLASSPTR netclass = aBoard->GetDesignSettings().m_NetClasses.GetDefault();
int via_drill_default = netclass->GetViaDrill();
for( unsigned v=0; v<wire_via->vertexes.size(); ++v )
{
::VIA* via = makeVIA( padstack, wire_via->vertexes[v], netCode, via_drill_default );
aBoard->Add( via );
}
}
}
}
void SaveParam( wxConfigBase* aConfig ) const override
{
if( !m_Pt_param || !aConfig )
return;
wxString oldPath = aConfig->GetPath();
NETCLASSES::const_iterator nc = m_Pt_param->begin();
for( unsigned index = 0; index <= m_Pt_param->GetCount(); ++index )
{
wxString path = "";
NETCLASSPTR netclass;
if( index == 0 )
path = "Default";
else
path << index;
aConfig->SetPath( oldPath );
aConfig->SetPath( m_Ident );
aConfig->SetPath( path );
if( index == 0 )
{
netclass = m_Pt_param->GetDefault();
}
else
{
netclass = nc->second;
++nc;
}
aConfig->Write( NetclassNameKey, netclass->GetName() );
#define WRITE_MM( aKey, aValue ) aConfig->Write( aKey, Iu2Millimeter( aValue ) )
WRITE_MM( ClearanceKey, netclass->GetClearance() );
WRITE_MM( TrackWidthKey, netclass->GetTrackWidth() );
WRITE_MM( ViaDiameterKey, netclass->GetViaDiameter() );
WRITE_MM( ViaDrillKey, netclass->GetViaDrill() );
WRITE_MM( uViaDiameterKey, netclass->GetuViaDiameter() );
WRITE_MM( uViaDrillKey, netclass->GetuViaDrill() );
WRITE_MM( dPairWidthKey, netclass->GetDiffPairWidth() );
WRITE_MM( dPairGapKey, netclass->GetDiffPairGap() );
WRITE_MM( dPairViaGapKey, netclass->GetDiffPairViaGap() );
}
aConfig->SetPath( oldPath );
}
void ReadParam( wxConfigBase* aConfig ) const override
{
if( !m_Pt_param || !aConfig )
return;
wxString oldPath = aConfig->GetPath();
m_Pt_param->Clear();
for( int index = 0; ; ++index )
{
wxString path = "";
NETCLASSPTR netclass;
wxString netclassName;
if( index == 0 )
path = "Default";
else
path << index;
aConfig->SetPath( oldPath );
aConfig->SetPath( m_Ident );
aConfig->SetPath( path );
if( !aConfig->Read( NetclassNameKey, &netclassName ) )
break;
if( index == 0 )
netclass = m_Pt_param->GetDefault();
else
netclass = std::make_shared<NETCLASS>( netclassName );
#define READ_MM( aKey, aDefault ) Millimeter2iu( aConfig->ReadDouble( aKey, aDefault ) )
netclass->SetClearance( READ_MM( ClearanceKey, netclass->GetClearance() ) );
netclass->SetTrackWidth( READ_MM( TrackWidthKey, netclass->GetTrackWidth() ) );
netclass->SetViaDiameter( READ_MM( ViaDiameterKey, netclass->GetViaDiameter() ) );
netclass->SetViaDrill( READ_MM( ViaDrillKey, netclass->GetViaDrill() ) );
netclass->SetuViaDiameter( READ_MM( uViaDiameterKey, netclass->GetuViaDiameter() ) );
netclass->SetuViaDrill( READ_MM( uViaDrillKey, netclass->GetuViaDrill() ) );
netclass->SetDiffPairWidth( READ_MM( dPairWidthKey, netclass->GetDiffPairWidth() ) );
netclass->SetDiffPairGap( READ_MM( dPairGapKey, netclass->GetDiffPairGap() ) );
netclass->SetDiffPairViaGap( READ_MM( dPairViaGapKey, netclass->GetDiffPairViaGap() ) );
if( index > 0 )
m_Pt_param->Add( netclass );
}
aConfig->SetPath( oldPath );
}
bool DRC::doTrackDrc( TRACK* aRefSeg, TRACK* aStart, bool testPads )
{
TRACK* track;
wxPoint delta; // length on X and Y axis of segments
LSET layerMask;
int net_code_ref;
wxPoint shape_pos;
NETCLASSPTR netclass = aRefSeg->GetNetClass();
BOARD_DESIGN_SETTINGS& dsnSettings = m_pcb->GetDesignSettings();
/* In order to make some calculations more easier or faster,
* pads and tracks coordinates will be made relative to the reference segment origin
*/
wxPoint origin = aRefSeg->GetStart(); // origin will be the origin of other coordinates
m_segmEnd = delta = aRefSeg->GetEnd() - origin;
m_segmAngle = 0;
layerMask = aRefSeg->GetLayerSet();
net_code_ref = aRefSeg->GetNetCode();
// Phase 0 : Test vias
if( aRefSeg->Type() == PCB_VIA_T )
{
const VIA *refvia = static_cast<const VIA*>( aRefSeg );
// test if the via size is smaller than minimum
if( refvia->GetViaType() == VIA_MICROVIA )
{
if( refvia->GetWidth() < dsnSettings.m_MicroViasMinSize )
{
m_currentMarker = fillMarker( refvia, NULL,
DRCE_TOO_SMALL_MICROVIA, m_currentMarker );
return false;
}
if( refvia->GetDrillValue() < dsnSettings.m_MicroViasMinDrill )
{
m_currentMarker = fillMarker( refvia, NULL,
DRCE_TOO_SMALL_MICROVIA_DRILL, m_currentMarker );
return false;
}
}
else
{
if( refvia->GetWidth() < dsnSettings.m_ViasMinSize )
{
m_currentMarker = fillMarker( refvia, NULL,
DRCE_TOO_SMALL_VIA, m_currentMarker );
return false;
}
if( refvia->GetDrillValue() < dsnSettings.m_ViasMinDrill )
{
m_currentMarker = fillMarker( refvia, NULL,
DRCE_TOO_SMALL_VIA_DRILL, m_currentMarker );
return false;
}
}
// test if via's hole is bigger than its diameter
// This test is necessary since the via hole size and width can be modified
// and a default via hole can be bigger than some vias sizes
if( refvia->GetDrillValue() > refvia->GetWidth() )
{
m_currentMarker = fillMarker( refvia, NULL,
DRCE_VIA_HOLE_BIGGER, m_currentMarker );
return false;
}
// For microvias: test if they are blind vias and only between 2 layers
// because they are used for very small drill size and are drill by laser
// and **only one layer** can be drilled
if( refvia->GetViaType() == VIA_MICROVIA )
{
LAYER_ID layer1, layer2;
bool err = true;
refvia->LayerPair( &layer1, &layer2 );
if( layer1 > layer2 )
std::swap( layer1, layer2 );
if( layer2 == B_Cu && layer1 == m_pcb->GetDesignSettings().GetCopperLayerCount() - 2 )
err = false;
else if( layer1 == F_Cu && layer2 == In1_Cu )
err = false;
if( err )
{
m_currentMarker = fillMarker( refvia, NULL,
DRCE_MICRO_VIA_INCORRECT_LAYER_PAIR, m_currentMarker );
return false;
}
}
}
else // This is a track segment
{
if( aRefSeg->GetWidth() < dsnSettings.m_TrackMinWidth )
{
m_currentMarker = fillMarker( aRefSeg, NULL,
DRCE_TOO_SMALL_TRACK_WIDTH, m_currentMarker );
return false;
}
}
// for a non horizontal or vertical segment Compute the segment angle
// in tenths of degrees and its length
if( delta.x || delta.y )
{
// Compute the segment angle in 0,1 degrees
m_segmAngle = ArcTangente( delta.y, delta.x );
// Compute the segment length: we build an equivalent rotated segment,
// this segment is horizontal, therefore dx = length
RotatePoint( &delta, m_segmAngle ); // delta.x = length, delta.y = 0
}
m_segmLength = delta.x;
/******************************************/
/* Phase 1 : test DRC track to pads : */
/******************************************/
/* Use a dummy pad to test DRC tracks versus holes, for pads not on all copper layers
* but having a hole
* This dummy pad has the size and shape of the hole
* to test tracks to pad hole DRC, using checkClearanceSegmToPad test function.
* Therefore, this dummy pad is a circle or an oval.
* A pad must have a parent because some functions expect a non null parent
* to find the parent board, and some other data
*/
MODULE dummymodule( m_pcb ); // Creates a dummy parent
D_PAD dummypad( &dummymodule );
dummypad.SetLayerSet( LSET::AllCuMask() ); // Ensure the hole is on all layers
// Compute the min distance to pads
if( testPads )
{
unsigned pad_count = m_pcb->GetPadCount();
for( unsigned ii = 0; ii<pad_count; ++ii )
{
D_PAD* pad = m_pcb->GetPad( ii );
/* No problem if pads are on an other layer,
* But if a drill hole exists (a pad on a single layer can have a hole!)
* we must test the hole
*/
if( !( pad->GetLayerSet() & layerMask ).any() )
{
/* We must test the pad hole. In order to use the function
* checkClearanceSegmToPad(),a pseudo pad is used, with a shape and a
* size like the hole
*/
if( pad->GetDrillSize().x == 0 )
continue;
dummypad.SetSize( pad->GetDrillSize() );
dummypad.SetPosition( pad->GetPosition() );
dummypad.SetShape( pad->GetDrillShape() == PAD_DRILL_SHAPE_OBLONG ?
PAD_SHAPE_OVAL : PAD_SHAPE_CIRCLE );
dummypad.SetOrientation( pad->GetOrientation() );
m_padToTestPos = dummypad.GetPosition() - origin;
if( !checkClearanceSegmToPad( &dummypad, aRefSeg->GetWidth(),
netclass->GetClearance() ) )
{
m_currentMarker = fillMarker( aRefSeg, pad,
DRCE_TRACK_NEAR_THROUGH_HOLE, m_currentMarker );
return false;
}
continue;
}
// The pad must be in a net (i.e pt_pad->GetNet() != 0 )
// but no problem if the pad netcode is the current netcode (same net)
if( pad->GetNetCode() // the pad must be connected
&& net_code_ref == pad->GetNetCode() ) // the pad net is the same as current net -> Ok
continue;
// DRC for the pad
shape_pos = pad->ShapePos();
m_padToTestPos = shape_pos - origin;
if( !checkClearanceSegmToPad( pad, aRefSeg->GetWidth(), aRefSeg->GetClearance( pad ) ) )
{
m_currentMarker = fillMarker( aRefSeg, pad,
DRCE_TRACK_NEAR_PAD, m_currentMarker );
return false;
}
}
}
/***********************************************/
/* Phase 2: test DRC with other track segments */
/***********************************************/
// At this point the reference segment is the X axis
// Test the reference segment with other track segments
wxPoint segStartPoint;
wxPoint segEndPoint;
for( track = aStart; track; track = track->Next() )
{
// No problem if segments have the same net code:
if( net_code_ref == track->GetNetCode() )
continue;
// No problem if segment are on different layers :
if( !( layerMask & track->GetLayerSet() ).any() )
continue;
// the minimum distance = clearance plus half the reference track
// width plus half the other track's width
int w_dist = aRefSeg->GetClearance( track );
w_dist += (aRefSeg->GetWidth() + track->GetWidth()) / 2;
// Due to many double to int conversions during calculations, which
// create rounding issues,
// the exact clearance margin cannot be really known.
// To avoid false bad DRC detection due to these rounding issues,
// slightly decrease the w_dist (remove one nanometer is enough !)
w_dist -= 1;
// If the reference segment is a via, we test it here
if( aRefSeg->Type() == PCB_VIA_T )
{
delta = track->GetEnd() - track->GetStart();
segStartPoint = aRefSeg->GetStart() - track->GetStart();
if( track->Type() == PCB_VIA_T )
{
// Test distance between two vias, i.e. two circles, trivial case
if( EuclideanNorm( segStartPoint ) < w_dist )
{
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_VIA_NEAR_VIA, m_currentMarker );
return false;
}
}
else // test via to segment
{
// Compute l'angle du segment a tester;
double angle = ArcTangente( delta.y, delta.x );
// Compute new coordinates ( the segment become horizontal)
RotatePoint( &delta, angle );
RotatePoint( &segStartPoint, angle );
if( !checkMarginToCircle( segStartPoint, w_dist, delta.x ) )
{
m_currentMarker = fillMarker( track, aRefSeg,
DRCE_VIA_NEAR_TRACK, m_currentMarker );
return false;
}
}
continue;
}
/* We compute segStartPoint, segEndPoint = starting and ending point coordinates for
* the segment to test in the new axis : the new X axis is the
* reference segment. We must translate and rotate the segment to test
*/
segStartPoint = track->GetStart() - origin;
segEndPoint = track->GetEnd() - origin;
RotatePoint( &segStartPoint, m_segmAngle );
RotatePoint( &segEndPoint, m_segmAngle );
if( track->Type() == PCB_VIA_T )
{
if( checkMarginToCircle( segStartPoint, w_dist, m_segmLength ) )
continue;
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_TRACK_NEAR_VIA, m_currentMarker );
return false;
}
/* We have changed axis:
* the reference segment is Horizontal.
* 3 cases : the segment to test can be parallel, perpendicular or have an other direction
*/
if( segStartPoint.y == segEndPoint.y ) // parallel segments
{
if( abs( segStartPoint.y ) >= w_dist )
continue;
// Ensure segStartPoint.x <= segEndPoint.x
if( segStartPoint.x > segEndPoint.x )
std::swap( segStartPoint.x, segEndPoint.x );
if( segStartPoint.x > (-w_dist) && segStartPoint.x < (m_segmLength + w_dist) ) /* possible error drc */
{
// the start point is inside the reference range
// X........
// O--REF--+
// Fine test : we consider the rounded shape of each end of the track segment:
if( segStartPoint.x >= 0 && segStartPoint.x <= m_segmLength )
{
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_TRACK_ENDS1, m_currentMarker );
return false;
}
if( !checkMarginToCircle( segStartPoint, w_dist, m_segmLength ) )
{
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_TRACK_ENDS2, m_currentMarker );
return false;
}
}
if( segEndPoint.x > (-w_dist) && segEndPoint.x < (m_segmLength + w_dist) )
{
// the end point is inside the reference range
// .....X
// O--REF--+
// Fine test : we consider the rounded shape of the ends
if( segEndPoint.x >= 0 && segEndPoint.x <= m_segmLength )
{
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_TRACK_ENDS3, m_currentMarker );
return false;
}
if( !checkMarginToCircle( segEndPoint, w_dist, m_segmLength ) )
{
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_TRACK_ENDS4, m_currentMarker );
return false;
}
}
if( segStartPoint.x <=0 && segEndPoint.x >= 0 )
{
// the segment straddles the reference range (this actually only
// checks if it straddles the origin, because the other cases where already
// handled)
// X.............X
// O--REF--+
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_TRACK_SEGMENTS_TOO_CLOSE, m_currentMarker );
return false;
}
}
else if( segStartPoint.x == segEndPoint.x ) // perpendicular segments
{
if( ( segStartPoint.x <= (-w_dist) ) || ( segStartPoint.x >= (m_segmLength + w_dist) ) )
continue;
// Test if segments are crossing
if( segStartPoint.y > segEndPoint.y )
std::swap( segStartPoint.y, segEndPoint.y );
if( (segStartPoint.y < 0) && (segEndPoint.y > 0) )
{
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_TRACKS_CROSSING, m_currentMarker );
return false;
}
// At this point the drc error is due to an end near a reference segm end
if( !checkMarginToCircle( segStartPoint, w_dist, m_segmLength ) )
{
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_ENDS_PROBLEM1, m_currentMarker );
return false;
}
if( !checkMarginToCircle( segEndPoint, w_dist, m_segmLength ) )
{
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_ENDS_PROBLEM2, m_currentMarker );
return false;
}
}
else // segments quelconques entre eux
{
// calcul de la "surface de securite du segment de reference
// First rought 'and fast) test : the track segment is like a rectangle
m_xcliplo = m_ycliplo = -w_dist;
m_xcliphi = m_segmLength + w_dist;
m_ycliphi = w_dist;
// A fine test is needed because a serment is not exactly a
// rectangle, it has rounded ends
if( !checkLine( segStartPoint, segEndPoint ) )
{
/* 2eme passe : the track has rounded ends.
* we must a fine test for each rounded end and the
* rectangular zone
*/
m_xcliplo = 0;
m_xcliphi = m_segmLength;
if( !checkLine( segStartPoint, segEndPoint ) )
{
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_ENDS_PROBLEM3, m_currentMarker );
return false;
}
else // The drc error is due to the starting or the ending point of the reference segment
{
// Test the starting and the ending point
segStartPoint = track->GetStart();
segEndPoint = track->GetEnd();
delta = segEndPoint - segStartPoint;
// Compute the segment orientation (angle) en 0,1 degre
double angle = ArcTangente( delta.y, delta.x );
// Compute the segment length: delta.x = length after rotation
RotatePoint( &delta, angle );
/* Comute the reference segment coordinates relatives to a
* X axis = current tested segment
*/
wxPoint relStartPos = aRefSeg->GetStart() - segStartPoint;
wxPoint relEndPos = aRefSeg->GetEnd() - segStartPoint;
RotatePoint( &relStartPos, angle );
RotatePoint( &relEndPos, angle );
if( !checkMarginToCircle( relStartPos, w_dist, delta.x ) )
{
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_ENDS_PROBLEM4, m_currentMarker );
return false;
}
if( !checkMarginToCircle( relEndPos, w_dist, delta.x ) )
{
m_currentMarker = fillMarker( aRefSeg, track,
DRCE_ENDS_PROBLEM5, m_currentMarker );
return false;
}
}
}
}
}
return true;
}
