// This function expands mips intrinsic nodes which have 64-bit input operands // or output values. // // out64 = intrinsic-node in64 // => // lo = copy (extract-element (in64, 0)) // hi = copy (extract-element (in64, 1)) // mips-specific-node // v0 = copy lo // v1 = copy hi // out64 = merge-values (v0, v1) // static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) { DebugLoc DL = Op.getDebugLoc(); bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other; SmallVector<SDValue, 3> Ops; unsigned OpNo = 0; // See if Op has a chain input. if (HasChainIn) Ops.push_back(Op->getOperand(OpNo++)); // The next operand is the intrinsic opcode. assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant); // See if the next operand has type i64. SDValue Opnd = Op->getOperand(++OpNo), In64; if (Opnd.getValueType() == MVT::i64) In64 = initAccumulator(Opnd, DL, DAG); else Ops.push_back(Opnd); // Push the remaining operands. for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo) Ops.push_back(Op->getOperand(OpNo)); // Add In64 to the end of the list. if (In64.getNode()) Ops.push_back(In64); // Scan output. SmallVector<EVT, 2> ResTys; for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end(); I != E; ++I) ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I); // Create node. SDValue Val = DAG.getNode(Opc, DL, ResTys, &Ops[0], Ops.size()); SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val; if (!HasChainIn) return Out; assert(Val->getValueType(1) == MVT::Other); SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) }; return DAG.getMergeValues(Vals, 2, DL); }