Exemple #1
0
int _main(int argc, char *argv[])
{
    using namespace sc_core;
    using namespace soclib::caba;
    using namespace soclib::common;

    typedef VciParams<cell_size,
                      plen_size,
                      addr_size,
                      rerror_size,
                      clen_size,
                      rflag_size,
                      srcid_size,
                      pktid_size,
                      trdid_size,
                      wrplen_size> vci_param;

    ///////////////////////////////////////////////////////////////
    // command line arguments
    ///////////////////////////////////////////////////////////////
    int     ncycles             = 1000000000;       // simulated cycles
    char    sys_path[256]       = "soft_multi/sys.bin";   // pathname for system code
    char    app_path[256]       = "soft_multi/app.bin";   // pathname for application code
    char    ioc_filename[256]   = "to_be_defined";  // pathname for the ioc file
    size_t  fbf_size            = 128;              // number of lines = number of pixels
    bool    debug               = false;            // debug activated
    int     from_cycle          = 0;                // debug start cycle
    int     nprocs              = NPROCS;                // number of processors

    std::cout << std::endl << "********************************************************" << std::endl;
    std::cout << std::endl << "******        tp4_soclib_multi                    ******" << std::endl;
    std::cout << std::endl << "********************************************************" << std::endl;

    if (argc > 1)
    {
        for( int n=1 ; n<argc ; n=n+2 )
        {
            if( (strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc) )
            {
                ncycles = atoi(argv[n+1]);
            }
            else if( (strcmp(argv[n],"-NPROCS") == 0) && (n+1<argc) )
            {
                nprocs = atoi(argv[n+1]);
                assert( (nprocs <= 4 && nprocs > 0) && "NPROCS cannot be greater than 4");
            }
            else if( (strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) )
            {
                debug = true;
                from_cycle = atoi(argv[n+1]);
            }
            else if( (strcmp(argv[n],"-SYS") == 0) && (n+1<argc) )
            {
                strcpy(sys_path, argv[n+1]) ;
            }
            else if( (strcmp(argv[n],"-APP") == 0) && (n+1<argc) )
            {
                strcpy(app_path, argv[n+1]) ;
            }
            else if( (strcmp(argv[n],"-IOCFILE") == 0) && (n+1<argc) )
            {
                strcpy(ioc_filename, argv[n+1]) ;
            }
            else if( (strcmp(argv[n],"-FBFSIZE") == 0) && (n+1<argc) )
            {
                fbf_size = atoi(argv[n+1]) ;
            }
            else
            {
                std::cout << "   Arguments on the command line are (key,value) couples." << std::endl;
                std::cout << "   The order is not important." << std::endl;
                std::cout << "   Accepted arguments are :" << std::endl << std::endl;
                std::cout << "   -NCYCLES number_of_simulated_cycles" << std::endl;
                std::cout << "   -NPROCS number_of_processors" << std::endl;
                std::cout << "   -IOCFILE file_name" << std::endl;
                std::cout << "   -FBFSIZE number_of_pixels" << std::endl;
                std::cout << "   -SYS sys_elf_pathname" << std::endl;
                std::cout << "   -APP app_elf_pathname" << std::endl;
                std::cout << "   -DEBUG debug_start_cycle" << std::endl;
                exit(0);
            }
        }
    }
    std::cout << std::endl;
    std::cout << "    NPROCS       = " << nprocs << std::endl;
    std::cout << "    ncycles      = " << ncycles << std::endl;
    std::cout << "    sys_pathname = " << sys_path << std::endl;
    std::cout << "    app_pathname = " << app_path << std::endl;
    std::cout << "    ioc_filename = " << ioc_filename << std::endl;
    std::cout << "    icache_sets  = " << icache_sets << std::endl;
    std::cout << "    icache_words = " << icache_words << std::endl;
    std::cout << "    icache_ways  = " << icache_ways << std::endl;
    std::cout << "    dcache_sets  = " << dcache_sets << std::endl;
    std::cout << "    dcache_words = " << dcache_words << std::endl;
    std::cout << "    dcache_ways  = " << dcache_ways << std::endl;

    //////////////////////////////////////////////////////////////////////////
    // Mapping Table
    //////////////////////////////////////////////////////////////////////////
    MappingTable maptab(32, IntTab(8), IntTab(2), 0xFF000000);

    maptab.add(Segment("seg_reset" , SEG_RESET_BASE , SEG_RESET_SIZE , IntTab(TGTID_ROM), true));

    maptab.add(Segment("seg_kernel", SEG_KERNEL_BASE, SEG_KERNEL_SIZE, IntTab(TGTID_RAM), true));
    maptab.add(Segment("seg_kdata" , SEG_KDATA_BASE , SEG_KDATA_SIZE , IntTab(TGTID_RAM), true));
    maptab.add(Segment("seg_kunc"  , SEG_KUNC_BASE  , SEG_KUNC_SIZE  , IntTab(TGTID_RAM), false));
    maptab.add(Segment("seg_code"  , SEG_CODE_BASE  , SEG_CODE_SIZE  , IntTab(TGTID_RAM), true));
    maptab.add(Segment("seg_data"  , SEG_DATA_BASE  , SEG_DATA_SIZE  , IntTab(TGTID_RAM), true));
    maptab.add(Segment("seg_stack" , SEG_STACK_BASE , SEG_STACK_SIZE , IntTab(TGTID_RAM), true));

    maptab.add(Segment("seg_tty"   ,  SEG_TTY_BASE ,  SEG_TTY_SIZE ,  IntTab(TGTID_TTY), false));
    maptab.add(Segment("seg_timer" ,  SEG_TIM_BASE ,  SEG_TIM_SIZE ,  IntTab(TGTID_TIM), false));
    maptab.add(Segment("seg_icu"   ,  SEG_ICU_BASE ,  SEG_ICU_SIZE ,  IntTab(TGTID_ICU), false));
    maptab.add(Segment("seg_dma"   ,  SEG_DMA_BASE ,  SEG_DMA_SIZE ,  IntTab(TGTID_DMA), false));
    maptab.add(Segment("seg_fbf"   ,  SEG_FBF_BASE ,  SEG_FBF_SIZE ,  IntTab(TGTID_FBF), false));
    maptab.add(Segment("seg_ioc"   ,  SEG_IOC_BASE ,  SEG_IOC_SIZE ,  IntTab(TGTID_IOC), false));
    maptab.add(Segment("seg_gcd"   ,  SEG_GCD_BASE ,  SEG_GCD_SIZE ,  IntTab(TGTID_GCD), false));

    std::cout << std::endl << maptab << std::endl;

    //////////////////////////////////////////////////////////////////////////
    // Signals
    //////////////////////////////////////////////////////////////////////////
    sc_clock        signal_clk("signal_clk", sc_time( 1, SC_NS ), 0.5 );
    sc_signal<bool> signal_resetn("signal_resetn");

    VciSignals<vci_param> * signal_vci_init_proc = alloc_elems<VciSignals<vci_param> >("signal_vci_init_proc", nprocs);

    VciSignals<vci_param>   signal_vci_init_dma("signal_vci_init_dma");
    VciSignals<vci_param>   signal_vci_init_ioc("signal_vci_init_ioc");

    VciSignals<vci_param>   signal_vci_tgt_rom("signal_vci_tgt_rom");
    VciSignals<vci_param>   signal_vci_tgt_ram("signal_vci_tgt_ram");
    VciSignals<vci_param>   signal_vci_tgt_tty("signal_vci_tgt_tty");
    VciSignals<vci_param>   signal_vci_tgt_gcd("signal_vci_tgt_gcd");
    VciSignals<vci_param>   signal_vci_tgt_tim("signal_vci_tgt_tim");
    VciSignals<vci_param>   signal_vci_tgt_icu("signal_vci_tgt_icu");
    VciSignals<vci_param>   signal_vci_tgt_fbf("signal_vci_tgt_fbf");
    VciSignals<vci_param>   signal_vci_tgt_ioc("signal_vci_tgt_ioc");
    VciSignals<vci_param>   signal_vci_tgt_dma("signal_vci_tgt_dma");

    sc_signal<bool> signal_false("signal_false");
    sc_signal<bool> * signal_irq_ttys = alloc_elems<sc_signal<bool> >("signal_irq_ttys", nprocs);
    sc_signal<bool> * signal_irq_tims = alloc_elems<sc_signal<bool> >("signal_irq_tims", nprocs);
    sc_signal<bool> * signal_irq_dmas = alloc_elems<sc_signal<bool> >("signal_irq_dmas", nprocs);
    sc_signal<bool> * signal_irq_procs = alloc_elems<sc_signal<bool> >("signal_irq_procs", nprocs);
    sc_signal<bool> signal_irq_ioc("signal_irq_ioc");

    ///////////////////////////////////////////////////////////////
    // VCI Components : 3 initiators / 9 targets
    // The IOC & DMA components are both initiator & target.
    ///////////////////////////////////////////////////////////////
    // The ICU controls 4 input IRQs :
    // - IRQ[0] : timer
    // - IRQ[1] : tty
    // - IRQ[2] : ioc
    // - IRQ[3] : dma
    //////////////////////////////////////////////////////////////

    Loader loader(sys_path, app_path);

    VciXcacheWrapper<vci_param, Mips32ElIss >* proc[nprocs];
    char*                                      name[nprocs];
    for (int i = 0; i< nprocs; i++){
    name[i] = new char[16];
    sprintf(name[i], "proc_%d", i);
    proc[i] = new VciXcacheWrapper<vci_param,Mips32ElIss>(name[i], i,maptab,IntTab(i),
                                                    icache_ways, icache_sets, icache_words,
                                                    dcache_ways, dcache_sets, dcache_words);
    }
    VciSimpleRam<vci_param>* rom;
    rom = new VciSimpleRam<vci_param>("rom", IntTab(TGTID_ROM), maptab, loader);

    VciSimpleRam<vci_param>* ram;
    ram = new VciSimpleRam<vci_param>("ram", IntTab(TGTID_RAM), maptab, loader);
   
    std::vector<std::string> vect_names;
    for( int i = 0 ; i < nprocs ; i++ )
    {
        std::ostringstream tty_name;
          tty_name <<  "tty" << i;

         vect_names.push_back(tty_name.str().c_str());
      }

 
    VciMultiTty<vci_param>* tty;
    tty = new VciMultiTty<vci_param>("tty", IntTab(TGTID_TTY), maptab, vect_names);

    VciGcdCoprocessor<vci_param>* gcd;
    gcd = new VciGcdCoprocessor<vci_param>("gcd", IntTab(TGTID_GCD), maptab);

    VciTimer<vci_param>* timer;
    timer = new VciTimer<vci_param>("timer", IntTab(TGTID_TIM), maptab, nprocs);

    VciMultiIcu<vci_param>* icu;
    icu = new VciMultiIcu<vci_param>("icu", IntTab(TGTID_ICU), maptab, 32, nprocs);

    VciMultiDma<vci_param>* dma;
    dma = new VciMultiDma<vci_param>("dma", maptab, IntTab(nprocs+1), IntTab(TGTID_DMA), 64, nprocs);

    VciFrameBuffer<vci_param>* fbf;
    fbf = new VciFrameBuffer<vci_param>("fbf", IntTab(TGTID_FBF), maptab, fbf_size, fbf_size, 420);

    VciBlockDevice<vci_param>* ioc;
//    ioc = new VciBlockDevice<vci_param>("ioc", maptab, IntTab(2 +nprocs), IntTab(TGTID_IOC), ioc_filename ,512, 0); 
    ioc = new VciBlockDevice<vci_param>("ioc", maptab, IntTab(2 +nprocs), IntTab(TGTID_IOC), ioc_filename ); 

    VciVgsb<vci_param>* bus;
    bus = new VciVgsb<vci_param>("vgsb", maptab, 2+nprocs, 9);

    //////////////////////////////////////////////////////////////////////////
    // Net-List
    //////////////////////////////////////////////////////////////////////////
    for (int i=0; i< nprocs; i++){
    proc[i]->p_clk                     (signal_clk);
    proc[i]->p_resetn                  (signal_resetn);
    proc[i]->p_vci                     (signal_vci_init_proc[i]);
    proc[i]->p_irq[0]                  (signal_irq_procs[i]);
    proc[i]->p_irq[1]                  (signal_false);
    proc[i]->p_irq[2]                  (signal_false);
    proc[i]->p_irq[3]                  (signal_false);
    proc[i]->p_irq[4]                  (signal_false);
    proc[i]->p_irq[5]                  (signal_false);
}
    rom->p_clk                      (signal_clk);
    rom->p_resetn                   (signal_resetn);
    rom->p_vci                      (signal_vci_tgt_rom);

    ram->p_clk                      (signal_clk);
    ram->p_resetn                   (signal_resetn);
    ram->p_vci                      (signal_vci_tgt_ram);

    gcd->p_clk                      (signal_clk);
    gcd->p_resetn                   (signal_resetn);
    gcd->p_vci                      (signal_vci_tgt_gcd);

    tty->p_clk                      (signal_clk);
    tty->p_resetn                   (signal_resetn);
    tty->p_vci                      (signal_vci_tgt_tty);
    for (int i=0; i< nprocs; i++)
    tty->p_irq[i]                   (signal_irq_ttys[i]);

    timer->p_clk                    (signal_clk);
    timer->p_resetn                 (signal_resetn);
    timer->p_vci                    (signal_vci_tgt_tim);
    for (int i=0; i< nprocs; i++)
    timer->p_irq[i]                 (signal_irq_tims[i]);

    icu->p_clk                      (signal_clk);
    icu->p_resetn                   (signal_resetn);
    icu->p_vci                      (signal_vci_tgt_icu);
    for (int i = 0; i < nprocs; i++)
        icu->p_irq_out[i]          (signal_irq_procs[i]);
    for (int i = 16; i < 32; i++)
        icu->p_irq_in[i]            (signal_false);

    icu->p_irq_in[0]            (signal_irq_ioc);
    icu->p_irq_in[1]            (signal_false);
    icu->p_irq_in[2]            (signal_false);
    icu->p_irq_in[3]            (signal_false);

    for (int i = 0; i < nprocs; i++)
    {
        icu->p_irq_in[i + 4](signal_irq_dmas[i]);
        icu->p_irq_in[i + 8](signal_irq_tims[i]);
        icu->p_irq_in[i + 12](signal_irq_ttys[i]);
    }
    for (int i = nprocs; i < 4; i++) //4 is the Max processor we can use 
    {
        icu->p_irq_in[i + 4](signal_false);
        icu->p_irq_in[i + 8](signal_false);
        icu->p_irq_in[i + 12](signal_false);
    }

    fbf->p_clk                      (signal_clk);
    fbf->p_resetn                   (signal_resetn);
    fbf->p_vci                      (signal_vci_tgt_fbf);

    ioc->p_clk                      (signal_clk);
    ioc->p_resetn                   (signal_resetn);
    ioc->p_vci_initiator            (signal_vci_init_ioc);
    ioc->p_vci_target               (signal_vci_tgt_ioc);
    ioc->p_irq                      (signal_irq_ioc);

    dma->p_clk                      (signal_clk);
    dma->p_resetn                   (signal_resetn);
    dma->p_vci_initiator            (signal_vci_init_dma);
    dma->p_vci_target               (signal_vci_tgt_dma);
    for (int i=0; i< nprocs; i++)
    dma->p_irq[i]                   (signal_irq_dmas[i]);

    bus->p_clk                      (signal_clk);
    bus->p_resetn                   (signal_resetn);
    for (int i =0; i< nprocs; i++){
    bus->p_to_initiator[i]          (signal_vci_init_proc[i]);
    }
    bus->p_to_initiator[1 + nprocs -1]     (signal_vci_init_dma);
    bus->p_to_initiator[2 + nprocs -1]     (signal_vci_init_ioc);
    bus->p_to_target[TGTID_ROM]     (signal_vci_tgt_rom);
    bus->p_to_target[TGTID_RAM]     (signal_vci_tgt_ram);
    bus->p_to_target[TGTID_TTY]     (signal_vci_tgt_tty);
    bus->p_to_target[TGTID_GCD]     (signal_vci_tgt_gcd);
    bus->p_to_target[TGTID_TIM]     (signal_vci_tgt_tim);
    bus->p_to_target[TGTID_ICU]     (signal_vci_tgt_icu);
    bus->p_to_target[TGTID_DMA]     (signal_vci_tgt_dma);
    bus->p_to_target[TGTID_FBF]     (signal_vci_tgt_fbf);
    bus->p_to_target[TGTID_IOC]     (signal_vci_tgt_ioc);

    //////////////////////////////////////////////////////////////////////////
    // simulation
    //////////////////////////////////////////////////////////////////////////

    sc_start( sc_time( 1, SC_NS ) ) ;
    signal_false = false;
    signal_resetn = false;
    sc_start( sc_time( 1, SC_NS ) ) ;

    signal_resetn = true;
    for ( int n=1 ; n<ncycles ; n++ )
    {
        if( debug && (n > from_cycle) )
        {
            std::cout << "***************** cycle " << std::dec << n << std::endl;
            for(int i=0; i< nprocs; i++)
            proc[i]->print_trace(1);
            bus->print_trace();
            timer->print_trace();
            rom->print_trace();
            ram->print_trace();
   //         if( signal_irq_procs.read() ) std::cout << "IRQ_PROC" << std::endl;
   //         if( signal_irq_tims.read() )  std::cout << "IRQ_TIM"  << std::endl;
   //         if( signal_irq_ttys.read() )  std::cout << "IRQ_TTY"  << std::endl;
   //         if( signal_irq_ioc.read() )  std::cout << "IRQ_IOC"  << std::endl;
   //         if( signal_irq_dmas.read() )  std::cout << "IRQ_DMA"  << std::endl;
        }
        sc_start( sc_time( 1 , SC_NS ) ) ;
    }

    sc_stop();

    return(0);

} // end _main
Exemple #2
0
int _main(int argc, char *argv[])
{
#ifdef _OPENMP
    omp_set_dynamic(false);
    omp_set_num_threads(5);
    std::cerr << "Built with openmp version " << _OPENMP << std::endl;
#endif

    struct param_s param = PARAM_INITIALIZER;

    /* parse arguments */
    args_parse(argc, argv, param);

    /*
     * mapping tables
     */

    /* data mapping table */
    MappingTable maptabp(32, IntTab(0, 16), IntTab(0, srcid_width), 0xF0000000);

    /* ram */
    maptabp.add(Segment("mc_m", MEMC_BASE, MEMC_SIZE, IntTab(0, 0), true));
    maptabp.add(Segment("boot", BOOT_BASE, BOOT_SIZE, IntTab(0, 1), true));

    /* uncached peripherals */
    maptabp.add(Segment("xicu", XICU_BASE, XICU_SIZE, IntTab(0, 2), false));
    maptabp.add(Segment("tty",  MTTY_BASE, MTTY_SIZE, IntTab(0, 3), false));
    maptabp.add(Segment("bd",   BD_BASE,   BD_SIZE,   IntTab(0, 4), false));
    maptabp.add(Segment("fb",   FB_BASE,   FB_SIZE,   IntTab(0, 5), false));

    std::cout << maptabp << std::endl;

    /* xram mapping table */
    MappingTable maptabx(32, IntTab(8), IntTab(8), 0x30000000);
    maptabx.add(Segment("xram", MEMC_BASE, MEMC_SIZE, IntTab(0), false));

    std::cout << maptabx << std::endl;

    /*
     * components
     */

    Loader loader;
    loader.load_file(param.rom_path);
    loader.memory_default(0x5c);

#ifdef CONFIG_GDB_SERVER
    typedef GdbServer<Mips32ElIss> proc_iss;
    proc_iss::set_loader(loader);
#else
    typedef Mips32ElIss proc_iss;
#endif

    if (param.dummy_boot == true)
    {
        /* boot linux image directly */
        uint64_t entry_addr = loader.get_entry_point_address();
        std::cout << "setResetAdress: " << std::hex << entry_addr << std::endl << std::endl;
        proc_iss::setResetAddress(entry_addr);
    }

    VciCcVCacheWrapper<vci_param, dspin_cmd_width, dspin_rsp_width, proc_iss > **proc;
    proc = new VciCcVCacheWrapper<vci_param, dspin_cmd_width, dspin_rsp_width,
         proc_iss >*[param.nr_cpus];
    for (size_t i = 0; i < param.nr_cpus; i++)
    {
        std::ostringstream o;
        o << "ccvache" << "[" << i << "]";
        proc[i] = new VciCcVCacheWrapper<vci_param, dspin_cmd_width,
            dspin_rsp_width, proc_iss >(
                o.str().c_str(),    // name
                i,                  // proc_id
                maptabp,            // direct space
                IntTab(0, i),       // srcid_d
                i,                  // cc_global_id
                8, 8,               // itlb size
                8, 8,               // dtlb size
                4, 64, 16,          // icache size
                4, 64, 16,          // dcache size
                4, 4,               // wbuf size
                0, 0,               // x, y Width
                MAX_FROZEN_CYCLES,  // max frozen cycles
                param.trace_start_cycle,
                param.trace_enabled);
    }

    VciSimpleRam<vci_param_ext> xram("xram", IntTab(0), maptabx, loader);

    VciSimpleRam<vci_param> rom("rom", IntTab(0, 1), maptabp, loader);

    VciMemCache<vci_param, vci_param_ext, dspin_rsp_width, dspin_cmd_width>
        memc("memc",
                maptabp,        // direct space
                maptabx,        // xram space
                IntTab(0),      // xram srcid
                IntTab(0, 0),   // direct tgtid
                0, 0,           // x, y width
                16, 256, 16,    // cache size
                3,              // max copies
                4096, 8, 8, 8,  // HEAP size, TRT size, UPT size, IVT size
                param.trace_start_cycle, param.trace_enabled);

    VciXicu<vci_param> xicu("xicu", maptabp, IntTab(0, 2),
            param.nr_cpus,  // #timers
            3,              // #input hw irqs
            param.nr_cpus,  // #ipis
            param.nr_cpus * NB_IRQS_PER_CPU); // #output irqs

    VciMultiTty<vci_param> mtty("mtty", IntTab(0, 3), maptabp, "vcitty0", NULL);

    VciBlockDeviceTsar<vci_param> *bd = NULL;
    if (param.dsk == true)
        bd = new VciBlockDeviceTsar<vci_param>("bd", maptabp,
                IntTab(0, param.nr_cpus),   // srcid
                IntTab(0, 4),               // tgtid
                param.dsk_path);            // filename

    VciFrameBuffer<vci_param> *fb = NULL;
    if (param.framebuffer == true)
        fb = new VciFrameBuffer<vci_param>("fb", IntTab(0, 5), maptabp,
                FB_XSIZE, FB_YSIZE,     // window size
                FbController::RGB_16);  // color type

    /*
     * Interconnects
     */

    /* data network */
    VciLocalCrossbar<vci_param> xbar_d("xbar_d",
            maptabp,        // mapping table
            0,              // cluster coordinates
            param.nr_cpus + 1, // #src
            6,              // #dst
            1);             // default target

    /* coherence */
    DspinLocalCrossbar<dspin_cmd_width> xbar_m2p_c("xbar_m2p_c",
            maptabp,
            0, 0,
            0, 0,
            srcid_width,
            1, param.nr_cpus,
            2, 2,
            true,
            false,
            true);
    DspinLocalCrossbar<dspin_rsp_width> xbar_p2m_c("xbar_p2m_c",
            maptabp,
            0, 0,
            0, 0,
            0,
            param.nr_cpus, 1,
            2, 2,
            false,
            false,
            false);
    DspinLocalCrossbar<dspin_cmd_width> xbar_clack_c("xbar_clack_c",
            maptabp,
            0, 0,
            0, 0,
            srcid_width,
            1, param.nr_cpus,
            1, 1,
            true,
            false,
            false);

    /*
     * signals
     */

    /* clk and resetn */
    sc_clock signal_clk ("clk");
    sc_signal<bool> signal_resetn("resetn");

    /* irq lines */
    sc_signal<bool> **signal_proc_irq =
        alloc_elems<sc_signal<bool> >("proc_irq", param.nr_cpus, proc_iss::n_irq);
    sc_signal<bool> signal_mtty_irq("mtty_irq");
    sc_signal<bool> signal_bd_irq("bd_irq");
    sc_signal<bool> signal_memc_irq("memc_irq");

    /* vci */
    VciSignals<vci_param> *signal_vci_proc =
        alloc_elems<VciSignals<vci_param> >("vci_proc", param.nr_cpus);
    VciSignals<vci_param> signal_vci_ini_bd ("vci_ini_bd");

    VciSignals<vci_param> signal_vci_memc ("vci_memc");
    VciSignals<vci_param> signal_vci_rom ("vci_rom");
    VciSignals<vci_param> signal_vci_xicu ("vci_xicu");
    VciSignals<vci_param> signal_vci_tty ("vci_tty");
    VciSignals<vci_param> signal_vci_tgt_bd ("vci_tgt_bd");
    VciSignals<vci_param> signal_vci_fb ("vci_fb");

    VciSignals<vci_param_ext> signal_vci_xram ("vci_xram");

    /* fake signals for in/out of cluster */
    VciSignals<vci_param> signal_vci_from_out("vci_from_out");
    VciSignals<vci_param> signal_vci_to_out("vci_to_out");

    /* Coherence DSPIN signals to local crossbar */
    DspinSignals<dspin_cmd_width> signal_dspin_m2p_l2g;
    DspinSignals<dspin_cmd_width> signal_dspin_m2p_g2l;
    DspinSignals<dspin_rsp_width> signal_dspin_p2m_l2g;
    DspinSignals<dspin_rsp_width> signal_dspin_p2m_g2l;
    DspinSignals<dspin_cmd_width> signal_dspin_clack_l2g;
    DspinSignals<dspin_cmd_width> signal_dspin_clack_g2l;

    DspinSignals<dspin_cmd_width> signal_dspin_m2p_memc;
    DspinSignals<dspin_cmd_width> signal_dspin_clack_memc;
    DspinSignals<dspin_rsp_width> signal_dspin_p2m_memc;
    DspinSignals<dspin_cmd_width> *signal_dspin_m2p_proc =
        alloc_elems<DspinSignals<dspin_cmd_width> >("dspin_m2p_proc", param.nr_cpus);
    DspinSignals<dspin_cmd_width> *signal_dspin_clack_proc =
        alloc_elems<DspinSignals<dspin_cmd_width> >("dspin_clack_proc", param.nr_cpus);
    DspinSignals<dspin_rsp_width> *signal_dspin_p2m_proc =
        alloc_elems<DspinSignals<dspin_rsp_width> >("dspin_p2m_proc", param.nr_cpus);

    /*
     * netlist
     */

    /* components */
    for (size_t i = 0; i < param.nr_cpus; i++)
    {
        proc[i]->p_clk(signal_clk);
        proc[i]->p_resetn(signal_resetn);
        for (size_t j = 0; j < proc_iss::n_irq; j++)
            proc[i]->p_irq[j](signal_proc_irq[i][j]);
        proc[i]->p_vci(signal_vci_proc[i]);
        proc[i]->p_dspin_m2p(signal_dspin_m2p_proc[i]);
        proc[i]->p_dspin_p2m(signal_dspin_p2m_proc[i]);
        proc[i]->p_dspin_clack(signal_dspin_clack_proc[i]);
    }

    memc.p_clk(signal_clk);
    memc.p_resetn(signal_resetn);
    memc.p_irq(signal_memc_irq);
    memc.p_vci_tgt(signal_vci_memc);
    memc.p_dspin_p2m(signal_dspin_p2m_memc);
    memc.p_dspin_m2p(signal_dspin_m2p_memc);
    memc.p_dspin_clack(signal_dspin_clack_memc);
    memc.p_vci_ixr(signal_vci_xram);

    rom.p_clk(signal_clk);
    rom.p_resetn(signal_resetn);
    rom.p_vci(signal_vci_rom);

    xicu.p_resetn(signal_resetn);
    xicu.p_clk(signal_clk);
    xicu.p_vci(signal_vci_xicu);
    xicu.p_hwi[0](signal_mtty_irq);
    xicu.p_hwi[1](signal_bd_irq);
    xicu.p_hwi[2](signal_memc_irq);
    for (size_t i = 0; i < param.nr_cpus; i++) {
        xicu.p_irq[i * NB_IRQS_PER_CPU + 0](signal_proc_irq[i][0]);
        xicu.p_irq[i * NB_IRQS_PER_CPU + 1](signal_proc_irq[i][1]);
        xicu.p_irq[i * NB_IRQS_PER_CPU + 2](signal_proc_irq[i][2]);
        xicu.p_irq[i * NB_IRQS_PER_CPU + 3](signal_proc_irq[i][3]);
    }

    mtty.p_clk(signal_clk);
    mtty.p_resetn(signal_resetn);
    mtty.p_vci(signal_vci_tty);
    mtty.p_irq[0](signal_mtty_irq);

    if (param.dsk == true)
    {
        bd->p_clk(signal_clk);
        bd->p_resetn(signal_resetn);
        bd->p_vci_target(signal_vci_tgt_bd);
        bd->p_vci_initiator(signal_vci_ini_bd);
        bd->p_irq(signal_bd_irq);
    }

    if (param.framebuffer == true)
    {
        fb->p_clk(signal_clk);
        fb->p_resetn(signal_resetn);
        fb->p_vci(signal_vci_fb);
    }

    xram.p_clk(signal_clk);
    xram.p_resetn(signal_resetn);
    xram.p_vci(signal_vci_xram);

    /* interconnects */
    xbar_d.p_clk(signal_clk);
    xbar_d.p_resetn(signal_resetn);
    xbar_d.p_target_to_up(signal_vci_from_out);
    xbar_d.p_initiator_to_up(signal_vci_to_out);
    for (size_t i = 0; i < param.nr_cpus; i++)
        xbar_d.p_to_initiator[i](signal_vci_proc[i]);
    xbar_d.p_to_initiator[param.nr_cpus](signal_vci_ini_bd);
    xbar_d.p_to_target[0](signal_vci_memc);
    xbar_d.p_to_target[1](signal_vci_rom);
    xbar_d.p_to_target[2](signal_vci_xicu);
    xbar_d.p_to_target[3](signal_vci_tty);
    xbar_d.p_to_target[4](signal_vci_tgt_bd);
    xbar_d.p_to_target[5](signal_vci_fb);

    xbar_m2p_c.p_clk(signal_clk);
    xbar_m2p_c.p_resetn(signal_resetn);
    xbar_m2p_c.p_global_out(signal_dspin_m2p_l2g);
    xbar_m2p_c.p_global_in(signal_dspin_m2p_g2l);
    xbar_m2p_c.p_local_in[0](signal_dspin_m2p_memc);
    for (size_t i = 0; i < param.nr_cpus; i++)
        xbar_m2p_c.p_local_out[i](signal_dspin_m2p_proc[i]);

    xbar_clack_c.p_clk(signal_clk);
    xbar_clack_c.p_resetn(signal_resetn);
    xbar_clack_c.p_global_out(signal_dspin_clack_l2g);
    xbar_clack_c.p_global_in(signal_dspin_clack_g2l);
    xbar_clack_c.p_local_in[0](signal_dspin_clack_memc);
    for (size_t i = 0; i < param.nr_cpus; i++)
        xbar_clack_c.p_local_out[i](signal_dspin_clack_proc[i]);

    xbar_p2m_c.p_clk(signal_clk);
    xbar_p2m_c.p_resetn(signal_resetn);
    xbar_p2m_c.p_global_out(signal_dspin_p2m_l2g);
    xbar_p2m_c.p_global_in(signal_dspin_p2m_g2l);
    xbar_p2m_c.p_local_out[0](signal_dspin_p2m_memc);
    for (size_t i = 0; i < param.nr_cpus; i++)
        xbar_p2m_c.p_local_in[i](signal_dspin_p2m_proc[i]);

    /*
     * simulation
     */

    for (size_t i = 0; i < param.nr_cpus; i++)
        proc[i]->iss_set_debug_mask(0);

    sc_start(sc_time(0, SC_NS));
    signal_resetn = false;

    sc_start(sc_time(1, SC_NS));
    signal_resetn = true;

    /* network boundaries initialization */
    signal_dspin_m2p_l2g.write = false;
    signal_dspin_m2p_l2g.read = true;
    signal_dspin_m2p_g2l.write = false;
    signal_dspin_m2p_g2l.read = true;

    if (param.ncycles > 0)
    {
        for (size_t n = 1; n < param.ncycles; n++)
        {
            if (param.trace_enabled and (n > param.trace_start_cycle))
            {
                std::cout << "****************** cycle " << std::dec << n
                    << " ************************************************" << std::endl;

                proc[0]->print_trace();
                memc.print_trace();

                signal_vci_proc[0].print_trace("signal_vci_proc[0]");
                signal_vci_memc.print_trace("signal_vci_memc");

                signal_dspin_m2p_memc.print_trace("signal_m2p_memc");
                signal_dspin_clack_memc.print_trace("signal_clack_memc");
                signal_dspin_p2m_memc.print_trace("signal_p2m_memc");
                for (size_t i = 0; i < param.nr_cpus; i++)
                {
                    std::ostringstream o;
                    o << "signal_m2p_proc" << "[" << i << "]";
                    signal_dspin_m2p_proc[i].print_trace(o.str().c_str());
                }
            }
            sc_start(sc_core::sc_time(1, SC_NS));
        }
    } else {
        uint64_t n;
        struct timeval t1, t2;

        gettimeofday(&t1, NULL);

        for (n = 1; ; n++) {
            /* stats display */
            if ((n % 5000000) == 0) {
                gettimeofday(&t2, NULL);

                uint64_t ms1 = (uint64_t)t1.tv_sec * 1000ULL +
                    (uint64_t)t1.tv_usec / 1000;
                uint64_t ms2 = (uint64_t)t2.tv_sec * 1000ULL +
                    (uint64_t)t2.tv_usec / 1000;
                std::cerr << "platform clock frequency "
                    << (double)5000000 / (double)(ms2 - ms1) << "Khz" << std::endl;

                gettimeofday(&t1, NULL);
            }

            sc_start(sc_core::sc_time(1, SC_NS));
        };
    }

    return EXIT_SUCCESS;

}
Exemple #3
0
int _main(int argc, char *argv[])
{
    using namespace sc_core;
    using namespace soclib::caba;
    using namespace soclib::common;

    // VCI fields width definition
    //  cell_size   = 4;
    //  plen_size   = 8;
    //  addr_size   = 32;
    //  rerror_size = 1;
    //  clen_size   = 1;
    //  rflag_size  = 1;
    //  srcid_size  = 12;
    //  pktid_size  = 1;
    //  trdid_size  = 4;
    //  wrplen_size = 1;

    typedef VciParams<4,8,32,1,1,1,12,1,4,1> vci_param;

    char    soft_name[256]     = "soft/boot.elf";
    char    ioc_filename[256]  = "soft/boot.elf";

    size_t  n_cycles        = 1000000000;       // simulated cycles
    size_t  tlb_ways        = 8;                // Itlb & Dtlb parameters
    size_t  tlb_sets        = 8;
    size_t  icache_sets     = 256;              // Icache parameters
    size_t  icache_words    = 16;
    size_t  icache_ways     = 4;
    size_t  dcache_sets     = 256;              // Dcache parameters
    size_t  dcache_words    = 16;
    size_t  dcache_ways     = 4;
    size_t  wbuf_nlines     = 4;                // Write Buffer parameters
    size_t  wbuf_nwords     = 4;
    size_t  ram_latency     = 0;                // Ram latency (L2 MISS emulation)
    size_t  fbf_size        = 128;              // number of lines = number of pixels
    bool    debug_ok        = false;            // debug activated
    size_t  from_cycle      = 0;                // debug start cycle
    bool    trace_ok        = false;            // cache trace activated
    char    trace_filename[256];
    FILE*   trace_file      = NULL;
    bool    stats_ok        = false;            // statistics activated
    char    stats_filename[256];
    FILE*   stats_file      = NULL;

    std::cout << std::endl << "********************************" << std::endl;
    std::cout << std::endl << "*** caba-vgmn-vcache-nic-dma ***" << std::endl;
    std::cout << std::endl << "********************************" << std::endl;

    if (argc > 1)
    {
        for( int n=1 ; n<argc ; n=n+2 )
        {
            if( (strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc) )
            {
                n_cycles = atoi(argv[n+1]);
            }
            else if( (strcmp(argv[n],"-TRACE") == 0) && (n+1<argc) )
            {
                trace_ok = true;
                if(n_cycles > 10000) n_cycles = 10000;
                strcpy(trace_filename, argv[n+1]);
                trace_file = fopen(trace_filename,"w+");
            }
            else if( (strcmp(argv[n],"-STATS") == 0) && (n+1<argc) )
            {
                stats_ok = true;
                strcpy(stats_filename, argv[n+1]);
                stats_file = fopen(stats_filename,"w+");
            }
            else if( (strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) )
            {
                debug_ok = true;
                from_cycle = atoi(argv[n+1]);
            }
            else if( (strcmp(argv[n],"-IOCFILE") == 0) && (n+1<argc) )
            {
                strcpy(ioc_filename, argv[n+1]) ;
            }
            else
            {
                std::cout << "   Arguments on the command line are (key,value)" << std::endl;
                std::cout << "   The order is not important." << std::endl;
                std::cout << "   Accepted arguments are :" << std::endl << std::endl;
                std::cout << "   -NCYCLES number_of_simulated_cycles" << std::endl;
                std::cout << "   -IOCFILE file_name" << std::endl;
                std::cout << "   -TRACE file_name" << std::endl;
                std::cout << "   -STATS file_name" << std::endl;
                std::cout << "   -DEBUG debug_start_cycle" << std::endl;
                exit(0);
            }
        }
    }
    std::cout << std::endl;
    std::cout << "    n_cycles     = " << n_cycles << std::endl;
    std::cout << "    icache_sets  = " << icache_sets << std::endl;
    std::cout << "    icache_words = " << icache_words << std::endl;
    std::cout << "    icache_ways  = " << icache_ways << std::endl;
    std::cout << "    dcache_sets  = " << dcache_sets << std::endl;
    std::cout << "    dcache_words = " << dcache_words << std::endl;
    std::cout << "    dcache_ways  = " << dcache_ways << std::endl;
    std::cout << "    ram_latency  = " << ram_latency << std::endl;
    if(trace_ok) std::cout << "    trace_file   = " << trace_filename << std::endl;
    if(stats_ok) std::cout << "    stats_file   = " << stats_filename << std::endl;

    /*  limitation are related to ICU inputs */
    if ( NB_VMS > 4 )
    {
        std::cout << std::endl;
        std::cout << "The number of VM cannot be larger than 4" << std::endl;
        exit(0);
    }

    //////////////////////////////////////////////////////////////////////////
    // Mapping Table
    //////////////////////////////////////////////////////////////////////////
    MappingTable maptab(32, IntTab(16), IntTab(12), 0xFFF00000);

    maptab.add(Segment("seg_rom", PSEG_ROM_BASE, PSEG_ROM_SIZE, IntTab(ROM_TGTID) , true));
    maptab.add(Segment("seg_ram", PSEG_RAM_BASE, PSEG_RAM_SIZE, IntTab(RAM_TGTID) , true));
    maptab.add(Segment("seg_tim", PSEG_TIM_BASE, PSEG_TIM_SIZE, IntTab(TIM_TGTID) , false));
    maptab.add(Segment("seg_dma", PSEG_DMA_BASE, PSEG_DMA_SIZE, IntTab(DMA_TGTID) , false));
    maptab.add(Segment("seg_nic", PSEG_NIC_BASE, PSEG_NIC_SIZE, IntTab(NIC_TGTID) , false));
    maptab.add(Segment("seg_fbf", PSEG_FBF_BASE, PSEG_FBF_SIZE, IntTab(FBF_TGTID) , false));
    maptab.add(Segment("seg_ioc", PSEG_IOC_BASE, PSEG_IOC_SIZE, IntTab(IOC_TGTID) , false));
    maptab.add(Segment("seg_tty", PSEG_TTY_BASE, PSEG_TTY_SIZE, IntTab(TTY_TGTID) , false));
    maptab.add(Segment("seg_icu", PSEG_ICU_BASE, PSEG_ICU_SIZE, IntTab(ICU_TGTID) , false));

    std::cout << std::endl << maptab << std::endl;

    //////////////////////////////////////////////////////////////////////////
    // Signals
    //////////////////////////////////////////////////////////////////////////
    sc_clock        signal_clk("signal_clk", sc_time( 1, SC_NS ), 0.5 );
    sc_signal<bool> signal_resetn("signal_resetn");

    VciSignals<vci_param> *signal_vci_init_proc =
        alloc_elems<VciSignals<vci_param> >("signal_vci_init_proc", NB_PROCS);

    VciSignals<vci_param> signal_vci_init_dma("signal_vci_init_dma");
    VciSignals<vci_param> signal_vci_init_ioc("signal_vci_init_ioc");

    VciSignals<vci_param> signal_vci_tgt_rom("signal_vci_tgt_rom");
    VciSignals<vci_param> signal_vci_tgt_ram("signal_vci_tgt_ram");
    VciSignals<vci_param> signal_vci_tgt_tim("signal_vci_tgt_tim");
    VciSignals<vci_param> signal_vci_tgt_fbf("signal_vci_tgt_fbf");
    VciSignals<vci_param> signal_vci_tgt_ioc("signal_vci_tgt_ioc");
    VciSignals<vci_param> signal_vci_tgt_dma("signal_vci_tgt_dma");
    VciSignals<vci_param> signal_vci_tgt_nic("signal_vci_tgt_nic");
    VciSignals<vci_param> signal_vci_tgt_icu("signal_vci_tgt_icu");
    VciSignals<vci_param> signal_vci_tgt_tty("signal_vci_tgt_tty");

    sc_signal<bool> signal_false("signal_false");

    sc_signal<bool> *signal_irq_proc =
        alloc_elems<sc_signal<bool> >("signal_irq_proc", NB_PROCS);

    sc_signal<bool> *signal_irq_tim =
        alloc_elems<sc_signal<bool> >("signal_irq_tim", NB_PROCS);

    sc_signal<bool> *signal_irq_tty =
        alloc_elems<sc_signal<bool> >("signal_irq_tty", NB_PROCS);

    sc_signal<bool> *signal_irq_dma =
        alloc_elems<sc_signal<bool> >("signal_irq_dma", 8);

    sc_signal<bool> *signal_irq_nic_rx =
        alloc_elems<sc_signal<bool> >("signal_irq_proc", 4);

    sc_signal<bool> *signal_irq_nic_tx =
        alloc_elems<sc_signal<bool> >("signal_irq_proc", 4);

    sc_signal<bool> signal_irq_ioc("signal_irq_ioc");

    //////////////////////////////////////////////////////////////////////////
    // VCI Components : (NB_PROCS+2) initiators / (9) targets
    // The IOC & DMA components are both initiator & target.
    //////////////////////////////////////////////////////////////////////////

    Loader loader(soft_name);

    GdbServer<Mips32ElIss>::set_loader(&loader);

    std::cout << std::endl;

    ////////////////////////////////////////////////////////////////////////
    VciVcacheWrapper<vci_param, GdbServer<Mips32ElIss> >* proc[NB_PROCS];
    for( size_t p = 0 ; p < NB_PROCS ; p++ )
        {
            std::ostringstream proc_name;
            proc_name << "proc_" << p;
            proc[p] = new VciVcacheWrapper< vci_param, GdbServer<Mips32ElIss> >
                          ( proc_name.str().c_str(),
                            p,
                            maptab,
                            IntTab(p),
                            tlb_ways, tlb_sets,
                            icache_ways, icache_sets, icache_words,
                            dcache_ways, dcache_sets, dcache_words,
                            wbuf_nlines, wbuf_nwords,
                            1000,           // max frozen cycles
                            from_cycle,     // debug_start_cycle
                            debug_ok );     //  detailed debug activation

            std::cout << "proc " << std::dec << p << " constructed" << std::endl;
        }

    /////////////////////////////
    VciSimpleRam<vci_param>* ram;
    ram = new VciSimpleRam<vci_param>("ram",
                                      IntTab(RAM_TGTID),
                                      maptab,
                                      loader,
                                      ram_latency);

    std::cout << "ram constructed" << std::endl;
    
    /////////////////////////////
    VciSimpleRam<vci_param>* rom;
    rom = new VciSimpleRam<vci_param>("rom",
                                      IntTab(ROM_TGTID),
                                      maptab,
                                      loader);

    std::cout << "rom constructed" << std::endl;

    ////////////////////////////
    VciMultiTty<vci_param> *tty;
    std::vector<std::string> vect_names;
    for( size_t p = 0 ; p < (NB_PROCS) ; p++ )
    {
        std::ostringstream term_name;
        term_name <<  "term" << p;
        vect_names.push_back(term_name.str().c_str());
    }
    tty = new VciMultiTty<vci_param>("tty",
                                     IntTab(TTY_TGTID),
                                     maptab,
                                     vect_names);

    std::cout << "tty constructed" << std::endl;

    ////////////////////////////
    VciMultiIcu<vci_param> *icu;
    icu = new VciMultiIcu<vci_param>("icu",
                                     IntTab(ICU_TGTID),
                                     maptab,
                                     32,
                                     NB_PROCS);

    std::cout << "icu constructed" << std::endl;

    ///////////////////////////
    VciTimer<vci_param>* timer;
    timer = new VciTimer<vci_param>("timer",
                                    IntTab(TIM_TGTID),
                                    maptab,
                                    NB_PROCS);

    std::cout << "timer constructed" << std::endl;

    ////////////////////////////
    VciChbufDma<vci_param>* dma;
    dma = new VciChbufDma<vci_param>("dma",
                                     maptab,
                                     IntTab(DMA_SRCID),
                                     IntTab(DMA_TGTID),
                                     64,
                                     8);    // at most 8 DMA channels

    std::cout << "dma constructed" << std::endl;

    ////////////////////////////
    VciMultiNic<vci_param>* nic;
    nic = new VciMultiNic<vci_param>("nic",
                                     IntTab(NIC_TGTID),
                                     maptab,
                                     4,     // at most 4 NIC channels
                                     "./in_two_channels.txt",
                                     "./out_two_channels.txt",
                                     DEFAULT_MAC_4,
                                     DEFAULT_MAC_2);

    std::cout << "nic constructed" << std::endl;

    ///////////////////////////////
    VciFrameBuffer<vci_param>* fbf;
    fbf = new VciFrameBuffer<vci_param>("fbf",
                                        IntTab(FBF_TGTID),
                                        maptab,
                                        fbf_size, fbf_size);

    std::cout << "fbf constructed" << std::endl;

    ///////////////////////////////
    VciBlockDevice<vci_param>* ioc;
    ioc = new VciBlockDevice<vci_param>("ioc",
                                        maptab,
                                        IntTab(IOC_SRCID),
                                        IntTab(IOC_TGTID),
                                        ioc_filename,
                                        512,
                                        200000);

    std::cout << "fbf constructed" << std::endl;

    ////////////////////////
    VciVgmn<vci_param>* noc;
    noc = new VciVgmn<vci_param>("noc",
                                 maptab,
                                 NB_PROCS+2,
                                 9,
                                 2,
                                 8);

    std::cout << "noc constructed" << std::endl << std::endl;

    //////////////////////////////////////////////////////////////////////////
    // Net-List
    //////////////////////////////////////////////////////////////////////////
    for ( size_t p = 0 ; p < NB_PROCS ; p++)
        {
            proc[p]->p_clk      (signal_clk);
            proc[p]->p_resetn   (signal_resetn);
            proc[p]->p_vci      (signal_vci_init_proc[p]);
            proc[p]->p_irq[0]   (signal_irq_proc[p]);
            proc[p]->p_irq[1]   (signal_false);
            proc[p]->p_irq[2]   (signal_false);
            proc[p]->p_irq[3]   (signal_false);
            proc[p]->p_irq[4]   (signal_false);
            proc[p]->p_irq[5]   (signal_false);
        }

    std::cout << "processors connected" << std::endl;

    //////////////////////////////////////////
    ram->p_clk      (signal_clk);
    ram->p_resetn   (signal_resetn);
    ram->p_vci      (signal_vci_tgt_ram);

    std::cout << "ram connected" << std::endl;

    //////////////////////////////////////////
    rom->p_clk      (signal_clk);
    rom->p_resetn   (signal_resetn);
    rom->p_vci      (signal_vci_tgt_rom);

    std::cout << "rom connected" << std::endl;

    //////////////////////////////////////////
    tty->p_clk      (signal_clk);
    tty->p_resetn   (signal_resetn);
    tty->p_vci      (signal_vci_tgt_tty);
    for (size_t t = 0 ; t < NB_PROCS ; t++)
        tty->p_irq[t] (signal_irq_tty[t]);

    std::cout << "tty connected" << std::endl;

    //////////////////////////////////////////
    icu->p_clk      (signal_clk);
    icu->p_resetn   (signal_resetn);
    icu->p_vci      (signal_vci_tgt_icu);

    // irq_out
    for (size_t p = 0 ; p < NB_PROCS ; p++)
        icu->p_irq_out[p]       (signal_irq_proc[p]);

    // irq_in_[0] to irq_in[3] : IOC
    icu->p_irq_in[0] (signal_irq_ioc);
    icu->p_irq_in[1] (signal_false);
    icu->p_irq_in[2] (signal_false);
    icu->p_irq_in[3] (signal_false);

    // irq_in_[4] to irq_in[8] : TTY(s)
    for (size_t x = 0 ; x < 5 ; x++)
    {
        if ( x < NB_PROCS ) icu->p_irq_in[x+4] (signal_irq_tty[x]);
        else                icu->p_irq_in[x+4] (signal_false);
    }

    // irq_in_[9] to irq_in[13] : TIMER(s)
    for (size_t x = 0 ; x < 5 ; x++)
    {
        if ( x < NB_PROCS ) icu->p_irq_in[x+9] (signal_irq_tim[x]);
        else                icu->p_irq_in[x+9] (signal_false);
    }

    // irq_in[14] to irq_in[15] 
    icu->p_irq_in[14] (signal_false);
    icu->p_irq_in[15] (signal_false);


    // irq_in[16] to irq_in[23] : DMA(s)
    for (size_t x = 0 ; x < 8 ; x++)
    {
        icu->p_irq_in[16+x] (signal_irq_dma[x]);
    }

    // irq_in[24] to irq_in[31] 
    for (size_t x = 0 ; x < 8 ; x++)
    {
        icu->p_irq_in[24+x] (signal_false);
    };

    std::cout << "icu connected" << std::endl;

    //////////////////////////////////////////
    timer->p_clk    (signal_clk);
    timer->p_resetn (signal_resetn);
    timer->p_vci    (signal_vci_tgt_tim);
    for (size_t p = 0 ; p < NB_PROCS ; p++)
    {
        timer->p_irq[p] (signal_irq_tim[p]);
    }

    std::cout << "timer connected" << std::endl;

    //////////////////////////////////////////
    dma->p_clk          (signal_clk);
    dma->p_resetn       (signal_resetn);
    dma->p_vci_initiator(signal_vci_init_dma);
    dma->p_vci_target   (signal_vci_tgt_dma);
    for (size_t p = 0 ; p < 8 ; p++)
    {
        dma->p_irq[p] (signal_irq_dma[p]);
    }

    std::cout << "dma connected" << std::endl;

    //////////////////////////////////////////
    nic->p_clk          (signal_clk);
    nic->p_resetn       (signal_resetn);
    nic->p_vci          (signal_vci_tgt_nic);
    for (size_t p = 0 ; p < 4 ; p++)
    {
        nic->p_rx_irq[p]   (signal_irq_nic_rx[p]);
        nic->p_tx_irq[p]   (signal_irq_nic_tx[p]);
    }

    std::cout << "nic connected" << std::endl;

    //////////////////////////////////////////
    fbf->p_clk      (signal_clk);
    fbf->p_resetn   (signal_resetn);
    fbf->p_vci      (signal_vci_tgt_fbf);

    std::cout << "fbf connected" << std::endl;

    //////////////////////////////////////////
    ioc->p_clk          (signal_clk);
    ioc->p_resetn       (signal_resetn);
    ioc->p_vci_initiator(signal_vci_init_ioc);
    ioc->p_vci_target   (signal_vci_tgt_ioc);
    ioc->p_irq          (signal_irq_ioc);

    std::cout << "ioc connected" << std::endl;

    //////////////////////////////////////////
    noc->p_clk      (signal_clk);
    noc->p_resetn   (signal_resetn);
    for ( size_t p = 0 ; p < NB_PROCS ; p++)
    {
        noc->p_to_initiator[p]  (signal_vci_init_proc[p]);
    }
    noc->p_to_initiator[DMA_SRCID]  (signal_vci_init_dma);
    noc->p_to_initiator[IOC_SRCID]  (signal_vci_init_ioc);
    noc->p_to_target[ROM_TGTID]     (signal_vci_tgt_rom);
    noc->p_to_target[RAM_TGTID]     (signal_vci_tgt_ram);
    noc->p_to_target[TIM_TGTID]     (signal_vci_tgt_tim);
    noc->p_to_target[DMA_TGTID]     (signal_vci_tgt_dma);
    noc->p_to_target[NIC_TGTID]     (signal_vci_tgt_nic);
    noc->p_to_target[FBF_TGTID]     (signal_vci_tgt_fbf);
    noc->p_to_target[IOC_TGTID]     (signal_vci_tgt_ioc);
    noc->p_to_target[TTY_TGTID]     (signal_vci_tgt_tty);
    noc->p_to_target[ICU_TGTID]     (signal_vci_tgt_icu);

    std::cout << "noc connected" << std::endl;

    //////////////////////////////////////////////////////////////////////////
    // simulation
    //////////////////////////////////////////////////////////////////////////

    signal_resetn = false;

    sc_start( sc_time( 1, SC_NS ) ) ;

    signal_resetn = true;
    
    for ( size_t n=1 ; n<n_cycles ; n++ )
    {
        sc_start( sc_time( 1 , SC_NS ) ) ;

        if( debug_ok && (n > from_cycle) )
        {
            std::cout << "***************** cycle " << std::dec << n
                      << " ***********************" << std::endl;

            proc[0]->print_trace();
            signal_vci_init_proc[0].print_trace("signal_proc_0");
#if 0
            proc[1]->print_trace();
            signal_vci_init_proc[1].print_trace("signal_proc_1");
            proc[2]->print_trace();
            signal_vci_init_proc[2].print_trace("signal_proc_2");
            proc[3]->print_trace();
            signal_vci_init_proc[3].print_trace("signal_proc_3");
            noc->print_trace(); // function not implemented
            rom->print_trace();
            signal_vci_tgt_rom.print_trace("signal_rom");
            ram->print_trace();
            signal_vci_tgt_ram.print_trace("signal_ram");
#endif
            nic->print_trace(0x3FF1);
            signal_vci_tgt_nic.print_trace("signal_nic");
            dma->print_trace();
            signal_vci_tgt_dma.print_trace("signal_tgt_dma");
            signal_vci_init_dma.print_trace("signal_init_dma");
#if 0
            if ( signal_irq_tim[0].read() ) 
            {
                std::cout << "!!! IRQ_TIMER [0] ACTIVATED !!!" << std::endl; 
                std::cout << "    PROC_IRQ [0] = " << signal_irq_proc[0] << std::endl;
            }
            if ( signal_irq_tim[1].read() ) 
            {
                std::cout << "!!! IRQ_TIMER [1] ACTIVATED !!!" << std::endl; 
                std::cout << "    PROC_IRQ [1] = " << signal_irq_proc[1] << std::endl;
            }
            if ( signal_irq_tim[2].read() ) 
            {
                std::cout << "!!! IRQ_TIMER [2] ACTIVATED !!!" << std::endl; 
                std::cout << "    PROC_IRQ [2] = " << signal_irq_proc[2] << std::endl;
            }
#endif
        }
    }

    kill(0, SIGINT);

    return 0;
} // end main