void act() {
while (true) {
cout << "MemAdaptor: waiting for requests..." << endl;
// wait for a request to come
while (req.read() != true) wait();
// request now accepted
address_t memaddr = addr.read(); // read recipient address
// SIZE request?
if (memsize.read() == true) {
// SIZE request!
cout << "MemAdaptor: SIZE request income, processing...";
addr.write(memory->size());
cout << " done." << endl;
goto act_oper_ok;
}
// READ request?
if (r_w.read() == true) {
// READ request!
cout << "MemAdaptor: READ request income, processing...";
char val;
try {
memory->read(val, memaddr);
} catch (std::runtime_error &e) {
// an error occurred, reporting on the bus
goto act_oper_err;
}
data.write(val);
cout << " done." << endl;
goto act_oper_ok;
}
// in any other case..
// WRITE request!
cout << "MemAdaptor: WRITE request income, processing...";
try { memory->write(data.read(), memaddr); } catch (std::runtime_error &e) {
// an error occurred, reporting on the bus
goto act_oper_err;
}
cout << " done." << endl;
goto act_oper_ok;
act_oper_err: // an error happened operating the service
err.write(true);
while (req.read() != false) wait();
err.write(false);
continue;
act_oper_ok: // service went ok
ack.write(true); // request served
// wait for peer assertion
while (req.read() != false) wait();
ack.write(false); // terminate the operation
}
}
void write(const char data, address_t address) {
// wait for the receiver to become available
waitendptfree();
// prepare info on bus to issue a write request
addr.write(address);
this->data.write(data);
r_w.write(false);
req.write(true);
// wait for receiver to acknowledge de request
if (waitresultready() == false) {
// an error occurred, propagate to CPU
throw std::runtime_error("Error while writing");
}
req.write(false);
}
void sc_reset::reset_signal_is(
bool async, const sc_out<bool>& port, bool level )
{
const sc_signal_in_if<bool>* iface_p;
sc_process_b* process_p;
process_p = (sc_process_b*)sc_get_current_process_handle();
assert( process_p );
process_p->m_has_reset_signal = true;
switch ( process_p->proc_kind() )
{
case SC_THREAD_PROC_:
case SC_METHOD_PROC_:
case SC_CTHREAD_PROC_:
iface_p = DCAST<const sc_signal_in_if<bool>*>(port.get_interface());
if ( iface_p )
reset_signal_is( async, *iface_p, level );
else
new sc_reset_finder( async, &port, level, process_p );
break;
default:
SC_REPORT_ERROR(SC_ID_UNKNOWN_PROCESS_TYPE_, process_p->name());
break;
}
}
void read(char &data, address_t address) {
// wait for the receiver to become available
waitendptfree();
addr.write(address);
r_w.write(true);
req.write(true);
// wait for the receiver to acknowledge the request
if (waitresultready() == false) {
// an error occurred, propagate to CPU
throw std::runtime_error("Error while reading.");
}
// service accomplished, data available on bus
data = this->data.read();
// recognizing the service
req.write(false);
}
// asking memory for what's its capacity
size_t size() {
// memory size is not necessarily sizeof(address_t),
// so this value must be provided directly to the memory
waitendptfree();
size_t sz;
// raise request for size
memsize.write(true);
req.write(true);
// wait for receiver to acknowledge
waitresultready();
sz = addr.read();
// bring back bus to ready state
memsize.write(false);
req.write(false);
return sz;
}
void prc_driver()
{
sc_uint<2> pattern;
d.write(0);
clk.write(0);
pattern = 0;
do
{
wait(5, SC_NS);
pattern++;
d.write(pattern[1]);
clk.write(pattern[0]);
}
while(0x3 != pattern);
wait(5, SC_NS);
sc_stop();
}
void produce() {
while (true) { // do forever:
wait(); // wait the beginning of a clock cycle
// possibly update the counter
if (++cnt == 1000)
cnt = 0;
// write data
value.write(cnt);
}
}
void run(){
unsigned int i=0;
cout << "x out: " << x << " AT time=" << sc_time_stamp() << endl;
for(i=0; i<=11; i++){
// wait();
cout << "x out: " << i*10 << " AT time=" << sc_time_stamp() << endl;
x.write(i*10);
wait();
}
}
void process() {
if (isHead == false) {
while (in.read() == false) {
#ifdef KASCPAR
wait(5, SC_NS);
#else
//sc_core::wait(5, SC_NS);
#endif
}
}
notified = true;
out.write(true);
}
void top::process3(){
while(true) {
if (z_count<y_count && z_count<x_count) {
z=y1+y3+1;
cout << " z=" << z << " AT time=" << sc_time_stamp() << endl;
output.write(z);
z_count++;
}
wait();
}
}
/** function declaration **/
void process()
{
wait(2500, SC_NS); // Wait to prevent use of garbage reg values
sc_time delay = sc_time(2500, SC_NS);
sc_bit b;
/** wait for start flag **/
transmissionstart: // Goto label in case of arbitration loss
do {
if (!(boolmem_write_ctl1)) wait(eventmem_write_ctl1); // Wait for start flag write to register
boolmem_write_ctl1=0; // Reset write flag
UCB0CTL1=read_register(UCB0CTL1_); // Start flag written, read register
if (STT_flag==1 ) { // Other master transmitting
wait_other_master();
}
} while ((!(UCB0CTL1 & UCTXSTT))| ( !((read_register(UCB0CTL0_)) & UCMST) )); // No start flag or not in master mode
STT_flag=1;
/** see if transmitting or receiving **/
UCB0CTL1=read_register(UCB0CTL1_);
if (UCB0CTL1 & UCTR){ // transmitting
UCTR_flag=1;
} else UCTR_flag=0; // receiving
/** generate transmit interrupt if transmitting **/
if(UCTR_flag) transmit_interrupt();
/** TLM-2 generic payload transaction **/
tlm::tlm_generic_payload* trans = new tlm::tlm_generic_payload;
trans->set_address( 0);
trans->set_data_ptr(reinterpret_cast<unsigned char *>(&sda));
trans->set_data_length( 4 );
trans->set_streaming_width( 4 ); // data_length, no streaming
trans->set_byte_enable_ptr( 0 ); // not used
trans->set_dmi_allowed( false ); // no dmi
trans->set_response_status( tlm::TLM_INCOMPLETE_RESPONSE ); // initial value
trans->set_command(TLM_IGNORE_COMMAND);
/** write start condition to bus **/
b = 0;
sda.write(b);
wait(6*250, SC_NS); // start condition: sdl change on high scl
socket->b_transport(*trans, delay);
trans->set_command(TLM_WRITE_COMMAND);
/** writing slave address to bus **/
UCB0I2CSA=(sc_bv<7>)(read_register(UCB0I2CSA_)); // Read register with slave address
while (bitnr < 7) { // 7 bit address
b = UCB0I2CSA[bitnr];
sda.write(b);
wait();
socket->b_transport(*trans, delay);
/** if b is high, check if other master is writing b low on bus, if yes wait (slave remains) **/
if ((b==1)&(sda.read() == 0)) { // arbitration lost
write_register(UCB0CTL1_, ( (read_register(UCB0CTL1_))& (!(UCTXSTT)) ) ); // clear start flag
wait_other_master(); // wait until bus free
goto transmissionstart; // bus free, start over
}
bitnr++;
/** writing read/!write bit to bus **/
if (bitnr == 7) {
b = !(UCTR_flag);
sda.write(b);
wait();
socket->b_transport(*trans, delay);
}
}
/** if transmitting **/
if (UCTR_flag)
{
/** read transmit buffer **/
if (!(boolmem_write_txbuf)) { // no data written yet
wait(eventmem_write_txbuf); // wait until data written to buffer
}
boolmem_write_txbuf=0; // reset write flag
UCB0TXBUF=(sc_bv<8>)(read_register(UCB0TXBUF_ )); // read buffer
}
/** wait for address acknowledgement **/
trans->set_command(TLM_READ_COMMAND);
socket->b_transport(*trans, delay);
wait();
if (sda.read() == 1) {} //no acknowledgement
/** clear start flag **/
UCB0CTL1=read_register(UCB0CTL1_ );
write_register(UCB0CTL1_ , (UCB0CTL1 & (~(UCTXSTT))) );
STT_flag=0;
while (!(UCB0CTL1 & UCTXSTP)) // no stop flag
{
/** if transmitting **/
if (UCTR_flag)
{
/** buffer to shift register **/
shift_reg=UCB0TXBUF;
/** transmit interrupt **/
transmit_interrupt();
/** data transfer **/
cout << sc_time_stamp()<< ": I2C: Master "<<sc_core::sc_get_current_process_b()->get_parent()->basename()<<"--- Transmitting data : " << UCB0TXBUF << endl;
trans->set_command(TLM_WRITE_COMMAND);
bitnr = 7;
while (bitnr >= 0) { // transmit data bitwise
b = shift_reg[bitnr--];
sda.write(b);
wait();
socket->b_transport(*trans, delay);
}
/** read transmit buffer **/
while ((!(read_register(UCB0CTL1_) & UCTXSTP))&(!(boolmem_write_txbuf))){ // no stop flag and no data written
wait(eventmem_write_txbuf | eventmem_write_ctl1); // wait for transmit buffer write
}
boolmem_write_txbuf=0; // reset write flag
UCB0TXBUF=(sc_bv<8>)(read_register(UCB0TXBUF_ )); // read transmit buffer
/** wait for acknowledgement **/
trans->set_command(TLM_READ_COMMAND);
socket->b_transport(*trans, delay);
do {wait();} while (bus_stall & (!(read_register(UCB0CTL1_) & UCTXSTP))) ;
if (sda.read() == 1) {} //no acknowledgement
}
/** if receiving **/
else {
trans->set_command(TLM_READ_COMMAND);
bitnr=7;
/* receive data bitwise */
while (bitnr >= 0) {
socket->b_transport(*trans, delay);
do {wait();} while (bus_stall & (!(read_register(UCB0CTL1_) & UCTXSTP)));
shift_reg[bitnr--] = sda.read(); // receive data bitwise
}
cout << sc_time_stamp()<< ": I2C: Master "<<sc_core::sc_get_current_process_b()->get_parent()->basename()<<"--- Received data : " << shift_reg << endl;
/* transfer shift register to buffer */
write_register(UCB0RXBUF_, (sc_uint<8>) shift_reg);
/* receive interrupt */
receive_interrupt();
/* wait until receive buffer read */
while ((!(read_register(UCB0CTL1_) & UCTXSTP))&(!(boolmem_read_rxbuf))){ // no stop flag and buffer not read
wait(eventmem_read_rxbuf | eventmem_write_ctl1); // wait until buffer read
}
boolmem_read_rxbuf=0;
/** acknowledgement **/
trans->set_command(TLM_WRITE_COMMAND);
b=0;
sda.write(b);
wait();
socket->b_transport(*trans, delay);
};
UCB0CTL1=read_register(UCB0CTL1_ );
}
/** write stop condition on bus **/
STP_flag = 1; //stop flag
wait(7*250, SC_NS);
trans->set_command(TLM_IGNORE_COMMAND);
b = 1;
sda.write(b);
wait();
socket->b_transport(*trans, delay);
/** clear stop flag **/
write_register(UCB0CTL1_ , (UCB0CTL1 & (~(UCTXSTP)))); //clear stop flag
STP_flag=0;
wait();
bitnr = 0;
goto transmissionstart;
}
void f() {
int t = (int) (sc_time_stamp ().to_double());
o.write(t);
}
