static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address,
const void *Decoder) {
unsigned Rd = fieldFromInstruction(Insn, 0, 5);
unsigned Rn = fieldFromInstruction(Insn, 5, 5);
unsigned ImmS = fieldFromInstruction(Insn, 10, 6);
unsigned ImmR = fieldFromInstruction(Insn, 16, 6);
unsigned SF = fieldFromInstruction(Insn, 31, 1);
// Undef for 0b11 just in case it occurs. Don't want the compiler to optimise
// out assertions that it thinks should never be hit.
enum OpcTypes { SBFM = 0, BFM, UBFM, Undef } Opc;
Opc = (OpcTypes)fieldFromInstruction(Insn, 29, 2);
if (!SF) {
// ImmR and ImmS must be between 0 and 31 for 32-bit instructions.
if (ImmR > 31 || ImmS > 31)
return MCDisassembler::Fail;
}
if (SF) {
DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
// BFM MCInsts use Rd as a source too.
if (Opc == BFM) DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
} else {
DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
// BFM MCInsts use Rd as a source too.
if (Opc == BFM) DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
DecodeGPR32RegisterClass(Inst, Rn, Address, Decoder);
}
// ASR and LSR have more specific patterns so they won't get here:
assert(!(ImmS == 31 && !SF && Opc != BFM)
&& "shift should have used auto decode");
assert(!(ImmS == 63 && SF && Opc != BFM)
&& "shift should have used auto decode");
// Extension instructions similarly:
if (Opc == SBFM && ImmR == 0) {
assert((ImmS != 7 && ImmS != 15) && "extension got here");
assert((ImmS != 31 || SF == 0) && "extension got here");
} else if (Opc == UBFM && ImmR == 0) {
assert((SF != 0 || (ImmS != 7 && ImmS != 15)) && "extension got here");
}
if (Opc == UBFM) {
// It might be a LSL instruction, which actually takes the shift amount
// itself as an MCInst operand.
if (SF && (ImmS + 1) % 64 == ImmR) {
Inst.setOpcode(AArch64::LSLxxi);
Inst.addOperand(MCOperand::CreateImm(63 - ImmS));
return MCDisassembler::Success;
} else if (!SF && (ImmS + 1) % 32 == ImmR) {
Inst.setOpcode(AArch64::LSLwwi);
Inst.addOperand(MCOperand::CreateImm(31 - ImmS));
return MCDisassembler::Success;
}
}
// Otherwise it's definitely either an extract or an insert depending on which
// of ImmR or ImmS is larger.
unsigned ExtractOp, InsertOp;
switch (Opc) {
default: llvm_unreachable("unexpected instruction trying to decode bitfield");
case SBFM:
ExtractOp = SF ? AArch64::SBFXxxii : AArch64::SBFXwwii;
InsertOp = SF ? AArch64::SBFIZxxii : AArch64::SBFIZwwii;
break;
case BFM:
ExtractOp = SF ? AArch64::BFXILxxii : AArch64::BFXILwwii;
InsertOp = SF ? AArch64::BFIxxii : AArch64::BFIwwii;
break;
case UBFM:
ExtractOp = SF ? AArch64::UBFXxxii : AArch64::UBFXwwii;
InsertOp = SF ? AArch64::UBFIZxxii : AArch64::UBFIZwwii;
break;
}
// Otherwise it's a boring insert or extract
Inst.addOperand(MCOperand::CreateImm(ImmR));
Inst.addOperand(MCOperand::CreateImm(ImmS));
if (ImmS < ImmR)
Inst.setOpcode(InsertOp);
else
Inst.setOpcode(ExtractOp);
return MCDisassembler::Success;
}
