/***********************************************************************
* Structors
**********************************************************************/
wbx_xcvr::wbx_xcvr(ctor_args_t args) : xcvr_dboard_base(args){
//enable the clocks that we need
this->get_iface()->set_clock_enabled(dboard_iface::UNIT_TX, true);
this->get_iface()->set_clock_enabled(dboard_iface::UNIT_RX, true);
//set the gpio directions and atr controls (identically)
this->get_iface()->set_pin_ctrl(dboard_iface::UNIT_TX, TXIO_MASK);
this->get_iface()->set_pin_ctrl(dboard_iface::UNIT_RX, RXIO_MASK);
this->get_iface()->set_gpio_ddr(dboard_iface::UNIT_TX, TXIO_MASK);
this->get_iface()->set_gpio_ddr(dboard_iface::UNIT_RX, RXIO_MASK);
if (wbx_debug) std::cerr << boost::format(
"WBX GPIO Direction: RX: 0x%08x, TX: 0x%08x"
) % RXIO_MASK % TXIO_MASK << std::endl;
//set some default values
set_rx_lo_freq((wbx_freq_range.start() + wbx_freq_range.stop())/2.0);
set_tx_lo_freq((wbx_freq_range.start() + wbx_freq_range.stop())/2.0);
set_rx_ant("RX2");
BOOST_FOREACH(const std::string &name, wbx_tx_gain_ranges.keys()){
set_tx_gain(wbx_tx_gain_ranges[name].start(), name);
}
BOOST_FOREACH(const std::string &name, wbx_rx_gain_ranges.keys()){
set_rx_gain(wbx_rx_gain_ranges[name].start(), name);
}
}
/***********************************************************************
* Structors
**********************************************************************/
sbx_xcvr::sbx_xcvr(ctor_args_t args) : xcvr_dboard_base(args){
//enable the clocks that we need
this->get_iface()->set_clock_enabled(dboard_iface::UNIT_TX, true);
this->get_iface()->set_clock_enabled(dboard_iface::UNIT_RX, true);
//set the gpio directions and atr controls (identically)
this->get_iface()->set_pin_ctrl(dboard_iface::UNIT_TX, (TXIO_MASK|TX_LED_IO));
this->get_iface()->set_pin_ctrl(dboard_iface::UNIT_RX, (RXIO_MASK|RX_LED_IO));
this->get_iface()->set_gpio_ddr(dboard_iface::UNIT_TX, (TXIO_MASK|TX_LED_IO));
this->get_iface()->set_gpio_ddr(dboard_iface::UNIT_RX, (RXIO_MASK|RX_LED_IO));
//flash LEDs
flash_leds();
UHD_LOGV(often) << boost::format(
"SBX GPIO Direction: RX: 0x%08x, TX: 0x%08x"
) % RXIO_MASK % TXIO_MASK << std::endl;
//set some default values
set_rx_lo_freq((sbx_freq_range.start() + sbx_freq_range.stop())/2.0);
set_tx_lo_freq((sbx_freq_range.start() + sbx_freq_range.stop())/2.0);
set_rx_ant("RX2");
BOOST_FOREACH(const std::string &name, sbx_tx_gain_ranges.keys()){
set_tx_gain(sbx_tx_gain_ranges[name].start(), name);
}
BOOST_FOREACH(const std::string &name, sbx_rx_gain_ranges.keys()){
set_rx_gain(sbx_rx_gain_ranges[name].start(), name);
}
}
libusb::device_handle::sptr libusb::device_handle::get_cached_handle(device::sptr dev){
static uhd::dict<libusb_device *, boost::weak_ptr<device_handle> > handles;
//lock for atomic access to static table above
static boost::mutex mutex;
boost::mutex::scoped_lock lock(mutex);
//not expired -> get existing handle
if (handles.has_key(dev->get()) and not handles[dev->get()].expired()){
return handles[dev->get()].lock();
}
//create a new cached handle
try{
sptr new_handle(new libusb_device_handle_impl(dev));
handles[dev->get()] = new_handle;
return new_handle;
}
catch(const uhd::exception &){
#ifdef UHD_PLATFORM_LINUX
UHD_MSG(error) <<
"USB open failed: insufficient permissions.\n"
"See the application notes for your device.\n"
<< std::endl;
#else
UHD_LOG << "USB open failed: device already claimed." << std::endl;
#endif
throw;
}
}
/***********************************************************************
* RX Codec Properties
**********************************************************************/
void usrp2_mboard_impl::rx_codec_get(const wax::obj &key_, wax::obj &val){
named_prop_t key = named_prop_t::extract(key_);
//handle the get request conditioned on the key
switch(key.as<codec_prop_t>()){
case CODEC_PROP_NAME:
switch(_iface->get_rev()){
case usrp2_iface::USRP_N200:
case usrp2_iface::USRP_N210:
val = _iface->get_cname() + " adc - ads62p44";
break;
case usrp2_iface::USRP2_REV3:
case usrp2_iface::USRP2_REV4:
val = _iface->get_cname() + " adc - ltc2284";
break;
case usrp2_iface::USRP_NXXX:
val = _iface->get_cname() + " adc - ??????";
break;
}
return;
case CODEC_PROP_OTHERS:
val = prop_names_t();
return;
case CODEC_PROP_GAIN_NAMES:
switch(_iface->get_rev()){
case usrp2_iface::USRP_N200:
case usrp2_iface::USRP_N210:
val = prop_names_t(codec_rx_gain_ranges.keys());
return;
default: val = prop_names_t();
}
return;
case CODEC_PROP_GAIN_I:
case CODEC_PROP_GAIN_Q:
assert_has(_codec_rx_gains.keys(), key.name, "codec rx gain name");
val = _codec_rx_gains[key.name];
return;
case CODEC_PROP_GAIN_RANGE:
assert_has(codec_rx_gain_ranges.keys(), key.name, "codec rx gain range name");
val = codec_rx_gain_ranges[key.name];
return;
default: UHD_THROW_PROP_GET_ERROR();
}
}
/***********************************************************************
* Structors
**********************************************************************/
xcvr2450::xcvr2450(ctor_args_t args) : xcvr_dboard_base(args) {
//enable only the clocks we need
this->get_iface()->set_clock_enabled(dboard_iface::UNIT_TX, true);
//set the gpio directions and atr controls (identically)
this->get_iface()->set_pin_ctrl(dboard_iface::UNIT_TX, TXIO_MASK);
this->get_iface()->set_pin_ctrl(dboard_iface::UNIT_RX, RXIO_MASK);
this->get_iface()->set_gpio_ddr(dboard_iface::UNIT_TX, TXIO_MASK);
this->get_iface()->set_gpio_ddr(dboard_iface::UNIT_RX, RXIO_MASK);
spi_reset(); //prepare the spi
_rx_bandwidth = 9.5e6;
_tx_bandwidth = 12.0e6;
//setup the misc max2829 registers
_max2829_regs.mimo_select = max2829_regs_t::MIMO_SELECT_MIMO;
_max2829_regs.band_sel_mimo = max2829_regs_t::BAND_SEL_MIMO_MIMO;
_max2829_regs.pll_cp_select = max2829_regs_t::PLL_CP_SELECT_4MA;
_max2829_regs.rssi_high_bw = max2829_regs_t::RSSI_HIGH_BW_6MHZ;
_max2829_regs.tx_lpf_coarse_adj = max2829_regs_t::TX_LPF_COARSE_ADJ_12MHZ;
_max2829_regs.rx_lpf_coarse_adj = max2829_regs_t::RX_LPF_COARSE_ADJ_9_5MHZ;
_max2829_regs.rx_lpf_fine_adj = max2829_regs_t::RX_LPF_FINE_ADJ_100;
_max2829_regs.rx_vga_gain_spi = max2829_regs_t::RX_VGA_GAIN_SPI_SPI;
_max2829_regs.rssi_output_range = max2829_regs_t::RSSI_OUTPUT_RANGE_HIGH;
_max2829_regs.rssi_op_mode = max2829_regs_t::RSSI_OP_MODE_ENABLED;
_max2829_regs.rssi_pin_fcn = max2829_regs_t::RSSI_PIN_FCN_RSSI;
_max2829_regs.rx_highpass = max2829_regs_t::RX_HIGHPASS_100HZ;
_max2829_regs.tx_vga_gain_spi = max2829_regs_t::TX_VGA_GAIN_SPI_SPI;
_max2829_regs.pa_driver_linearity = max2829_regs_t::PA_DRIVER_LINEARITY_78;
_max2829_regs.tx_vga_linearity = max2829_regs_t::TX_VGA_LINEARITY_78;
_max2829_regs.tx_upconv_linearity = max2829_regs_t::TX_UPCONV_LINEARITY_78;
//send initial register settings
for(boost::uint8_t reg = 0x2; reg <= 0xC; reg++) {
this->send_reg(reg);
}
//set defaults for LO, gains, antennas
set_lo_freq(2.45e9);
set_rx_ant(xcvr_antennas.at(0));
set_tx_ant(xcvr_antennas.at(1));
BOOST_FOREACH(const std::string &name, xcvr_tx_gain_ranges.keys()) {
set_tx_gain(xcvr_tx_gain_ranges[name].start(), name);
}
BOOST_FOREACH(const std::string &name, xcvr_rx_gain_ranges.keys()) {
set_rx_gain(xcvr_rx_gain_ranges[name].start(), name);
}
}
void enable_tx(bool enb){
_tx_enabled = enb;
_fx2_ctrl->usrp_tx_enable(enb);
BOOST_FOREACH(const std::string &key, _dbc.keys())
{
_dbc[key].codec->enable_tx_digital(enb);
}
}
static std::string get_band(double freq) {
BOOST_FOREACH(const std::string &band, tvrx_freq_ranges.keys()) {
if(freq >= tvrx_freq_ranges[band].start() && freq <= tvrx_freq_ranges[band].stop()){
UHD_LOGV(often) << "Band: " << band << std::endl;
return band;
}
}
UHD_THROW_INVALID_CODE_PATH();
}
static std::string get_band(double freq) {
for(const std::string &band: tvrx_freq_ranges.keys()) {
if(freq >= tvrx_freq_ranges[band].start() && freq <= tvrx_freq_ranges[band].stop()){
UHD_LOGGER_TRACE("TVRX") << "Band: " << band ;
return band;
}
}
UHD_THROW_INVALID_CODE_PATH();
}
/***********************************************************************
* WBX Common Implementation
**********************************************************************/
wbx_base::wbx_version4::wbx_version4(wbx_base *_self_wbx_base) {
//register our handle on the primary wbx_base instance
self_base = _self_wbx_base;
////////////////////////////////////////////////////////////////////
// Register RX properties
////////////////////////////////////////////////////////////////////
this->get_rx_subtree()->create<std::string>("name").set("WBXv4 RX");
this->get_rx_subtree()->create<double>("freq/value")
.coerce(boost::bind(&wbx_base::wbx_version4::set_lo_freq, this, dboard_iface::UNIT_RX, _1))
.set((wbx_v4_freq_range.start() + wbx_v4_freq_range.stop())/2.0);
this->get_rx_subtree()->create<meta_range_t>("freq/range").set(wbx_v4_freq_range);
////////////////////////////////////////////////////////////////////
// Register TX properties
////////////////////////////////////////////////////////////////////
this->get_tx_subtree()->create<std::string>("name").set("WBXv4 TX");
BOOST_FOREACH(const std::string &name, wbx_v4_tx_gain_ranges.keys()){
self_base->get_tx_subtree()->create<double>("gains/"+name+"/value")
.coerce(boost::bind(&wbx_base::wbx_version4::set_tx_gain, this, _1, name))
.set(wbx_v4_tx_gain_ranges[name].start());
self_base->get_tx_subtree()->create<meta_range_t>("gains/"+name+"/range")
.set(wbx_v4_tx_gain_ranges[name]);
}
this->get_tx_subtree()->create<double>("freq/value")
.coerce(boost::bind(&wbx_base::wbx_version4::set_lo_freq, this, dboard_iface::UNIT_TX, _1))
.set((wbx_v4_freq_range.start() + wbx_v4_freq_range.stop())/2.0);
this->get_tx_subtree()->create<meta_range_t>("freq/range").set(wbx_v4_freq_range);
this->get_tx_subtree()->create<bool>("enabled")
.subscribe(boost::bind(&wbx_base::wbx_version4::set_tx_enabled, this, _1))
.set(true); //start enabled
//set attenuator control bits
int v4_iobits = TX_ATTN_MASK;
int v4_tx_mod = ADF4351_PDBRF;
//set the gpio directions and atr controls
self_base->get_iface()->set_pin_ctrl(dboard_iface::UNIT_TX, v4_tx_mod|v4_iobits);
self_base->get_iface()->set_pin_ctrl(dboard_iface::UNIT_RX, RXBB_PDB|ADF4351_PDBRF);
self_base->get_iface()->set_gpio_ddr(dboard_iface::UNIT_TX, TX_PUP_5V|TX_PUP_3V|v4_tx_mod|v4_iobits);
self_base->get_iface()->set_gpio_ddr(dboard_iface::UNIT_RX, RX_PUP_5V|RX_PUP_3V|ADF4351_CE|RXBB_PDB|ADF4351_PDBRF|RX_ATTN_MASK);
//setup ATR for the mixer enables (always enabled to prevent phase slip between bursts)
//set TX gain iobits to min gain (max attenuation) when RX_ONLY or IDLE to suppress LO leakage
self_base->get_iface()->set_atr_reg(dboard_iface::UNIT_TX, dboard_iface::ATR_REG_IDLE, v4_tx_mod, TX_ATTN_MASK | TX_MIXER_DIS | v4_tx_mod);
self_base->get_iface()->set_atr_reg(dboard_iface::UNIT_TX, dboard_iface::ATR_REG_RX_ONLY, v4_tx_mod, TX_ATTN_MASK | TX_MIXER_DIS | v4_tx_mod);
self_base->get_iface()->set_atr_reg(dboard_iface::UNIT_TX, dboard_iface::ATR_REG_TX_ONLY, v4_tx_mod, TX_ATTN_MASK | TX_MIXER_DIS | v4_tx_mod);
self_base->get_iface()->set_atr_reg(dboard_iface::UNIT_TX, dboard_iface::ATR_REG_FULL_DUPLEX, v4_tx_mod, TX_ATTN_MASK | TX_MIXER_DIS | v4_tx_mod);
self_base->get_iface()->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_IDLE, RX_MIXER_ENB, RX_MIXER_DIS | RX_MIXER_ENB);
self_base->get_iface()->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_TX_ONLY, RX_MIXER_ENB, RX_MIXER_DIS | RX_MIXER_ENB);
self_base->get_iface()->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_RX_ONLY, RX_MIXER_ENB, RX_MIXER_DIS | RX_MIXER_ENB);
self_base->get_iface()->set_atr_reg(dboard_iface::UNIT_RX, dboard_iface::ATR_REG_FULL_DUPLEX, RX_MIXER_ENB, RX_MIXER_DIS | RX_MIXER_ENB);
}
void wbx_xcvr::set_rx_gain(double gain, const std::string &name){
assert_has(wbx_rx_gain_ranges.keys(), name, "wbx rx gain name");
if(name == "PGA0"){
rx_pga0_gain_to_iobits(gain);
_rx_gains[name] = gain;
//write the new gain to atr regs
update_atr();
}
else UHD_THROW_INVALID_CODE_PATH();
}
void wbx_xcvr::set_tx_gain(double gain, const std::string &name){
assert_has(wbx_tx_gain_ranges.keys(), name, "wbx tx gain name");
if(name == "PGA0"){
double dac_volts = tx_pga0_gain_to_dac_volts(gain);
_tx_gains[name] = gain;
//write the new voltage to the aux dac
this->get_iface()->write_aux_dac(dboard_iface::UNIT_TX, dboard_iface::AUX_DAC_A, dac_volts);
}
else UHD_THROW_INVALID_CODE_PATH();
}
/***********************************************************************
* Gain Handling
**********************************************************************/
double wbx_base::wbx_version2::set_tx_gain(double gain, const std::string &name){
assert_has(wbx_v2_tx_gain_ranges.keys(), name, "wbx tx gain name");
if(name == "PGA0"){
double dac_volts = tx_pga0_gain_to_dac_volts(gain);
self_base->_tx_gains[name] = gain;
//write the new voltage to the aux dac
self_base->get_iface()->write_aux_dac(dboard_iface::UNIT_TX, dboard_iface::AUX_DAC_A, dac_volts);
}
else UHD_THROW_INVALID_CODE_PATH();
return self_base->_tx_gains[name]; //shadowed
}
void xcvr2450::set_tx_gain(double gain, const std::string &name) {
assert_has(xcvr_tx_gain_ranges.keys(), name, "xcvr tx gain name");
if (name == "VGA") {
_max2829_regs.tx_vga_gain = gain_to_tx_vga_reg(gain);
send_reg(0xC);
}
else if(name == "BB") {
_max2829_regs.tx_baseband_gain = gain_to_tx_bb_reg(gain);
send_reg(0x9);
}
else UHD_THROW_INVALID_CODE_PATH();
_tx_gains[name] = gain;
}
void xcvr2450::set_rx_gain(double gain, const std::string &name) {
assert_has(xcvr_rx_gain_ranges.keys(), name, "xcvr rx gain name");
if (name == "VGA") {
_max2829_regs.rx_vga_gain = gain_to_rx_vga_reg(gain);
send_reg(0xB);
}
else if(name == "LNA") {
_max2829_regs.rx_lna_gain = gain_to_rx_lna_reg(gain);
send_reg(0xB);
}
else UHD_THROW_INVALID_CODE_PATH();
_rx_gains[name] = gain;
}
void dbsrx::set_gain(double gain, const std::string &name){
assert_has(dbsrx_gain_ranges.keys(), name, "dbsrx gain name");
if (name == "GC2"){
_max2118_write_regs.gc2 = gain_to_gc2_vga_reg(gain);
send_reg(0x5, 0x5);
}
else if(name == "GC1"){
//write the new voltage to the aux dac
this->get_iface()->write_aux_dac(dboard_iface::UNIT_RX, dboard_iface::AUX_DAC_A, gain_to_gc1_rfvga_dac(gain));
}
else UHD_THROW_INVALID_CODE_PATH();
_gains[name] = gain;
}
double rfx_xcvr::set_rx_gain(double gain, const std::string &name){
assert_has(_rx_gain_ranges.keys(), name, "rfx rx gain name");
if(name == "PGA0"){
double dac_volts = rx_pga0_gain_to_dac_volts(gain,
(_rx_gain_ranges["PGA0"].stop() - _rx_gain_ranges["PGA0"].start()));
//write the new voltage to the aux dac
this->get_iface()->write_aux_dac(dboard_iface::UNIT_RX, dboard_iface::AUX_DAC_A, dac_volts);
return gain;
}
else UHD_THROW_INVALID_CODE_PATH();
}
/***********************************************************************
* Gain Handling
**********************************************************************/
double wbx_base::wbx_version3::set_tx_gain(double gain, const std::string &name){
assert_has(wbx_v3_tx_gain_ranges.keys(), name, "wbx tx gain name");
if(name == "PGA0"){
uint16_t io_bits = tx_pga0_gain_to_iobits(gain);
self_base->_tx_gains[name] = gain;
//write the new gain to tx gpio outputs
//Update ATR with gain io_bits, only update for TX_ONLY and FULL_DUPLEX ATR states
self_base->get_iface()->set_atr_reg(dboard_iface::UNIT_TX, gpio_atr::ATR_REG_TX_ONLY, io_bits, TX_ATTN_MASK);
self_base->get_iface()->set_atr_reg(dboard_iface::UNIT_TX, gpio_atr::ATR_REG_FULL_DUPLEX, io_bits, TX_ATTN_MASK);
}
else UHD_THROW_INVALID_CODE_PATH();
return self_base->_tx_gains[name]; //shadow
}
static void apply_fe_corrections(
uhd::property_tree::sptr sub_tree,
const uhd::fs_path &db_path,
const uhd::fs_path &fe_path,
const std::string &file_prefix,
const double lo_freq
){
//extract eeprom serial
const uhd::usrp::dboard_eeprom_t db_eeprom = sub_tree->access<uhd::usrp::dboard_eeprom_t>(db_path).get();
//make the calibration file path
const fs::path cal_data_path = fs::path(uhd::get_app_path()) / ".uhd" / "cal" / (file_prefix + db_eeprom.serial + ".csv");
UHD_MSG(status) << "Looking for FE correction at: " << cal_data_path.c_str() << "... ";
if (not fs::exists(cal_data_path)) {
UHD_MSG(status) << "Not found" << std::endl;
return;
}
UHD_MSG(status) << "Found, loading... ";
//parse csv file or get from cache
if (not fe_cal_cache.has_key(cal_data_path.string())){
std::ifstream cal_data(cal_data_path.string().c_str());
const uhd::csv::rows_type rows = uhd::csv::to_rows(cal_data);
bool read_data = false, skip_next = false;;
std::vector<fe_cal_t> datas;
BOOST_FOREACH(const uhd::csv::row_type &row, rows){
if (not read_data and not row.empty() and row[0] == "DATA STARTS HERE"){
read_data = true;
skip_next = true;
continue;
}
if (not read_data) continue;
if (skip_next){
skip_next = false;
continue;
}
fe_cal_t data;
std::sscanf(row[0].c_str(), "%lf" , &data.lo_freq);
std::sscanf(row[1].c_str(), "%lf" , &data.iq_corr_real);
std::sscanf(row[2].c_str(), "%lf" , &data.iq_corr_imag);
datas.push_back(data);
}
std::sort(datas.begin(), datas.end(), fe_cal_comp);
fe_cal_cache[cal_data_path.string()] = datas;
UHD_MSG(status) << "Loaded" << std::endl;
} else {
/***********************************************************************
* Structors
**********************************************************************/
dbsrx::dbsrx(ctor_args_t args) : rx_dboard_base(args){
//warn user about incorrect DBID on USRP1, requires R193 populated
if (this->get_iface()->get_special_props().soft_clock_divider and this->get_rx_id() == 0x000D)
uhd::warning::post(
str(boost::format(
"DBSRX: incorrect dbid\n"
"Expected dbid 0x0002 and R193\n"
"found dbid == %d\n"
"Please see the daughterboard app notes"
) % this->get_rx_id().to_pp_string())
);
//warn user about incorrect DBID on non-USRP1, requires R194 populated
if (not this->get_iface()->get_special_props().soft_clock_divider and this->get_rx_id() == 0x0002)
uhd::warning::post(
str(boost::format(
"DBSRX: incorrect dbid\n"
"Expected dbid 0x000D and R194\n"
"found dbid == %d\n"
"Please see the daughterboard app notes"
) % this->get_rx_id().to_pp_string())
);
//enable only the clocks we need
this->get_iface()->set_clock_enabled(dboard_iface::UNIT_RX, true);
//set the gpio directions and atr controls (identically)
this->get_iface()->set_pin_ctrl(dboard_iface::UNIT_RX, 0x0); // All unused in atr
if (this->get_iface()->get_special_props().soft_clock_divider){
this->get_iface()->set_gpio_ddr(dboard_iface::UNIT_RX, 0x1); // GPIO0 is clock
}
else{
this->get_iface()->set_gpio_ddr(dboard_iface::UNIT_RX, 0x0); // All Inputs
}
//send initial register settings
this->send_reg(0x0, 0x5);
//set defaults for LO, gains, and filter bandwidth
_bandwidth = 33e6;
set_lo_freq(dbsrx_freq_range.start());
BOOST_FOREACH(const std::string &name, dbsrx_gain_ranges.keys()){
set_gain(dbsrx_gain_ranges[name].start(), name);
}
set_bandwidth(33e6); // default bandwidth from datasheet
}
static uhd::dict<std::string, gain_range_t> get_tvrx_gain_ranges(void) {
double rfmax = 0.0, rfmin = FLT_MAX;
BOOST_FOREACH(const std::string range, tvrx_rf_gains_db.keys()) {
double my_max = tvrx_rf_gains_db[range].back(); //we're assuming it's monotonic
double my_min = tvrx_rf_gains_db[range].front(); //if it's not this is wrong wrong wrong
if(my_max > rfmax) rfmax = my_max;
if(my_min < rfmin) rfmin = my_min;
}
double ifmin = tvrx_if_gains_db.front();
double ifmax = tvrx_if_gains_db.back();
return map_list_of
("RF", gain_range_t(rfmin, rfmax, (rfmax-rfmin)/4096.0))
("IF", gain_range_t(ifmin, ifmax, (ifmax-ifmin)/4096.0))
;
}
void usrp2_mboard_impl::rx_codec_set_gain(double gain, const std::string &name){
assert_has(codec_rx_gain_ranges.keys(), name, "codec rx gain name");
_codec_rx_gains[name] = gain;
/*
if(name == "analog") {
_codec_ctrl->set_rx_analog_gain(gain > 0); //just turn it on or off
return;
}
*/
if(name == "digital") {
_codec_ctrl->set_rx_digital_gain(gain);
return;
}
if(name == "digital-fine") {
_codec_ctrl->set_rx_digital_fine_gain(gain);
return;
}
UHD_THROW_PROP_SET_ERROR();
}
/***********************************************************************
* Find USRP N2XX with specified IP address and return type
**********************************************************************/
boost::uint32_t find_usrp(udp_simple::sptr udp_transport, bool check_rev) {
boost::uint32_t hw_rev;
bool found_it = false;
// If the user chooses to not care about the rev, simply check
// for the presence of a USRP N2XX.
boost::uint32_t cmd_id = (check_rev) ? GET_HW_REV_CMD
: USRP2_QUERY;
boost::uint32_t ack_id = (check_rev) ? GET_HW_REV_ACK
: USRP2_ACK;
const usrp2_fw_update_data_t *update_data_in = reinterpret_cast<const usrp2_fw_update_data_t *>(usrp2_update_data_in_mem);
usrp2_fw_update_data_t hw_info_pkt = usrp2_fw_update_data_t();
hw_info_pkt.proto_ver = htonx<boost::uint32_t>(USRP2_FW_PROTO_VERSION);
hw_info_pkt.id = htonx<boost::uint32_t>(cmd_id);
udp_transport->send(boost::asio::buffer(&hw_info_pkt, sizeof(hw_info_pkt)));
//Loop and receive until the timeout
size_t len = udp_transport->recv(boost::asio::buffer(usrp2_update_data_in_mem), UDP_TIMEOUT);
if(len > offsetof(usrp2_fw_update_data_t, data) and ntohl(update_data_in->id) == ack_id) {
hw_rev = ntohl(update_data_in->data.hw_rev);
if(filename_map.has_key(hw_rev)) {
std::cout << boost::format("Found %s.\n\n") % filename_map[hw_rev];
found_it = true;
}
else {
if(check_rev) throw std::runtime_error("Invalid revision found.");
else {
hw_rev = 0;
std::cout << "Found USRP N2XX." << std::endl;
found_it = true;
}
}
}
if(not found_it) throw std::runtime_error("No USRP N2XX found.");
return hw_rev;
}
/***********************************************************************
* Find USRP N2XX with specified IP address and return type
**********************************************************************/
boost::uint32_t find_usrp(udp_simple::sptr udp_transport){
boost::uint32_t hw_rev;
bool found_it = false;
const usrp2_fw_update_data_t *update_data_in = reinterpret_cast<const usrp2_fw_update_data_t *>(usrp2_update_data_in_mem);
usrp2_fw_update_data_t hw_info_pkt = usrp2_fw_update_data_t();
hw_info_pkt.proto_ver = htonx<boost::uint32_t>(USRP2_FW_PROTO_VERSION);
hw_info_pkt.id = htonx<boost::uint32_t>(GET_HW_REV_CMD);
udp_transport->send(boost::asio::buffer(&hw_info_pkt, sizeof(hw_info_pkt)));
//Loop and receive until the timeout
size_t len = udp_transport->recv(boost::asio::buffer(usrp2_update_data_in_mem), UDP_TIMEOUT);
if(len > offsetof(usrp2_fw_update_data_t, data) and ntohl(update_data_in->id) == GET_HW_REV_ACK){
hw_rev = ntohl(update_data_in->data.hw_rev);
if(filename_map.has_key(hw_rev)){
std::cout << boost::format("Found %s.\n\n") % filename_map[hw_rev];
found_it = true;
}
else throw std::runtime_error("Invalid revision found.");
}
if(not found_it) throw std::runtime_error("No USRP N2XX found.");
return hw_rev;
}
/***********************************************************************
* Tuning
**********************************************************************/
double sbx_xcvr::sbx_version3::set_lo_freq(dboard_iface::unit_t unit, double target_freq) {
UHD_LOGV(often) << boost::format(
"SBX tune: target frequency %f Mhz"
) % (target_freq/1e6) << std::endl;
//clip the input
target_freq = sbx_freq_range.clip(target_freq);
//map prescaler setting to mininmum integer divider (N) values (pg.18 prescaler)
static const uhd::dict<int, int> prescaler_to_min_int_div = map_list_of
(0,23) //adf4350_regs_t::PRESCALER_4_5
(1,75) //adf4350_regs_t::PRESCALER_8_9
;
//map rf divider select output dividers to enums
static const uhd::dict<int, adf4350_regs_t::rf_divider_select_t> rfdivsel_to_enum = map_list_of
(1, adf4350_regs_t::RF_DIVIDER_SELECT_DIV1)
(2, adf4350_regs_t::RF_DIVIDER_SELECT_DIV2)
(4, adf4350_regs_t::RF_DIVIDER_SELECT_DIV4)
(8, adf4350_regs_t::RF_DIVIDER_SELECT_DIV8)
(16, adf4350_regs_t::RF_DIVIDER_SELECT_DIV16)
;
double actual_freq, pfd_freq;
double ref_freq = self_base->get_iface()->get_clock_rate(unit);
int R=0, BS=0, N=0, FRAC=0, MOD=0;
int RFdiv = 1;
adf4350_regs_t::reference_divide_by_2_t T = adf4350_regs_t::REFERENCE_DIVIDE_BY_2_DISABLED;
adf4350_regs_t::reference_doubler_t D = adf4350_regs_t::REFERENCE_DOUBLER_DISABLED;
//Reference doubler for 50% duty cycle
// if ref_freq < 12.5MHz enable regs.reference_divide_by_2
if(ref_freq <= 12.5e6) D = adf4350_regs_t::REFERENCE_DOUBLER_ENABLED;
//increase RF divider until acceptable VCO frequency
double vco_freq = target_freq;
while (vco_freq < 2.2e9) {
vco_freq *= 2;
RFdiv *= 2;
}
//use 8/9 prescaler for vco_freq > 3 GHz (pg.18 prescaler)
adf4350_regs_t::prescaler_t prescaler = target_freq > 3e9 ? adf4350_regs_t::PRESCALER_8_9 : adf4350_regs_t::PRESCALER_4_5;
/*
* The goal here is to loop though possible R dividers,
* band select clock dividers, N (int) dividers, and FRAC
* (frac) dividers.
*
* Calculate the N and F dividers for each set of values.
* The loop exits when it meets all of the constraints.
* The resulting loop values are loaded into the registers.
*
* from pg.21
*
* f_pfd = f_ref*(1+D)/(R*(1+T))
* f_vco = (N + (FRAC/MOD))*f_pfd
* N = f_vco/f_pfd - FRAC/MOD = f_vco*((R*(T+1))/(f_ref*(1+D))) - FRAC/MOD
* f_rf = f_vco/RFdiv)
* f_actual = f_rf/2
*/
for(R = 1; R <= 1023; R+=1){
//PFD input frequency = f_ref/R ... ignoring Reference doubler/divide-by-2 (D & T)
pfd_freq = ref_freq*(1+D)/(R*(1+T));
//keep the PFD frequency at or below 25MHz (Loop Filter Bandwidth)
if (pfd_freq > 25e6) continue;
//ignore fractional part of tuning
N = int(std::floor(target_freq/pfd_freq));
//keep N > minimum int divider requirement
if (N < prescaler_to_min_int_div[prescaler]) continue;
for(BS=1; BS <= 255; BS+=1){
//keep the band select frequency at or below 100KHz
//constraint on band select clock
if (pfd_freq/BS > 100e3) continue;
goto done_loop;
}
} done_loop:
//Fractional-N calculation
MOD = 4095; //max fractional accuracy
FRAC = int((target_freq/pfd_freq - N)*MOD);
//Reference divide-by-2 for 50% duty cycle
// if R even, move one divide by 2 to to regs.reference_divide_by_2
if(R % 2 == 0){
T = adf4350_regs_t::REFERENCE_DIVIDE_BY_2_ENABLED;
R /= 2;
}
//actual frequency calculation
actual_freq = double((N + (double(FRAC)/double(MOD)))*ref_freq*(1+int(D))/(R*(1+int(T))));
UHD_LOGV(often)
<< boost::format("SBX Intermediates: ref=%0.2f, outdiv=%f, fbdiv=%f") % (ref_freq*(1+int(D))/(R*(1+int(T)))) % double(RFdiv*2) % double(N + double(FRAC)/double(MOD)) << std::endl
<< boost::format("SBX tune: R=%d, BS=%d, N=%d, FRAC=%d, MOD=%d, T=%d, D=%d, RFdiv=%d"
) % R % BS % N % FRAC % MOD % T % D % RFdiv << std::endl
<< boost::format("SBX Frequencies (MHz): REQ=%0.2f, ACT=%0.2f, VCO=%0.2f, PFD=%0.2f, BAND=%0.2f"
) % (target_freq/1e6) % (actual_freq/1e6) % (vco_freq/1e6) % (pfd_freq/1e6) % (pfd_freq/BS/1e6) << std::endl;
//load the register values
adf4350_regs_t regs;
if ((unit == dboard_iface::UNIT_TX) and (actual_freq == sbx_tx_lo_2dbm.clip(actual_freq)))
regs.output_power = adf4350_regs_t::OUTPUT_POWER_2DBM;
else
regs.output_power = adf4350_regs_t::OUTPUT_POWER_5DBM;
regs.frac_12_bit = FRAC;
regs.int_16_bit = N;
regs.mod_12_bit = MOD;
regs.clock_divider_12_bit = std::max(1, int(std::ceil(400e-6*pfd_freq/MOD)));
regs.feedback_select = adf4350_regs_t::FEEDBACK_SELECT_DIVIDED;
regs.clock_div_mode = adf4350_regs_t::CLOCK_DIV_MODE_RESYNC_ENABLE;
regs.prescaler = prescaler;
regs.r_counter_10_bit = R;
regs.reference_divide_by_2 = T;
regs.reference_doubler = D;
regs.band_select_clock_div = BS;
UHD_ASSERT_THROW(rfdivsel_to_enum.has_key(RFdiv));
regs.rf_divider_select = rfdivsel_to_enum[RFdiv];
//write the registers
//correct power-up sequence to write registers (5, 4, 3, 2, 1, 0)
int addr;
for(addr=5; addr>=0; addr--){
UHD_LOGV(often) << boost::format(
"SBX SPI Reg (0x%02x): 0x%08x"
) % addr % regs.get_reg(addr) << std::endl;
self_base->get_iface()->write_spi(
unit, spi_config_t::EDGE_RISE,
regs.get_reg(addr), 32
);
}
//return the actual frequency
UHD_LOGV(often) << boost::format(
"SBX tune: actual frequency %f Mhz"
) % (actual_freq/1e6) << std::endl;
return actual_freq;
}
/***********************************************************************
* Structors
**********************************************************************/
dbsrx::dbsrx(ctor_args_t args) : rx_dboard_base(args){
//warn user about incorrect DBID on USRP1, requires R193 populated
if (this->get_iface()->get_special_props().soft_clock_divider and this->get_rx_id() == 0x000D)
UHD_MSG(warning) << boost::format(
"DBSRX: incorrect dbid\n"
"Expected dbid 0x0002 and R193\n"
"found dbid == %d\n"
"Please see the daughterboard app notes"
) % this->get_rx_id().to_pp_string();
//warn user about incorrect DBID on non-USRP1, requires R194 populated
if (not this->get_iface()->get_special_props().soft_clock_divider and this->get_rx_id() == 0x0002)
UHD_MSG(warning) << boost::format(
"DBSRX: incorrect dbid\n"
"Expected dbid 0x000D and R194\n"
"found dbid == %d\n"
"Please see the daughterboard app notes"
) % this->get_rx_id().to_pp_string();
//send initial register settings
this->send_reg(0x0, 0x5);
//set defaults for LO, gains, and filter bandwidth
double codec_rate = this->get_iface()->get_codec_rate(dboard_iface::UNIT_RX);
_bandwidth = 0.8*codec_rate/2.0; // default to anti-alias at different codec_rate
////////////////////////////////////////////////////////////////////
// Register properties
////////////////////////////////////////////////////////////////////
this->get_rx_subtree()->create<std::string>("name")
.set("DBSRX");
this->get_rx_subtree()->create<sensor_value_t>("sensors/lo_locked")
.set_publisher(boost::bind(&dbsrx::get_locked, this));
BOOST_FOREACH(const std::string &name, dbsrx_gain_ranges.keys()){
this->get_rx_subtree()->create<double>("gains/"+name+"/value")
.set_coercer(boost::bind(&dbsrx::set_gain, this, _1, name))
.set(dbsrx_gain_ranges[name].start());
this->get_rx_subtree()->create<meta_range_t>("gains/"+name+"/range")
.set(dbsrx_gain_ranges[name]);
}
this->get_rx_subtree()->create<double>("freq/value")
.set_coercer(boost::bind(&dbsrx::set_lo_freq, this, _1));
this->get_rx_subtree()->create<meta_range_t>("freq/range")
.set(dbsrx_freq_range);
this->get_rx_subtree()->create<std::string>("antenna/value")
.set(dbsrx_antennas.at(0));
this->get_rx_subtree()->create<std::vector<std::string> >("antenna/options")
.set(dbsrx_antennas);
this->get_rx_subtree()->create<std::string>("connection")
.set("IQ");
this->get_rx_subtree()->create<bool>("enabled")
.set(true); //always enabled
this->get_rx_subtree()->create<bool>("use_lo_offset")
.set(false);
this->get_rx_subtree()->create<double>("bandwidth/value")
.set_coercer(boost::bind(&dbsrx::set_bandwidth, this, _1));
this->get_rx_subtree()->create<meta_range_t>("bandwidth/range")
.set(dbsrx_bandwidth_range);
//enable only the clocks we need
this->get_iface()->set_clock_enabled(dboard_iface::UNIT_RX, true);
//set the gpio directions and atr controls (identically)
this->get_iface()->set_pin_ctrl(dboard_iface::UNIT_RX, 0x0); // All unused in atr
if (this->get_iface()->get_special_props().soft_clock_divider){
this->get_iface()->set_gpio_ddr(dboard_iface::UNIT_RX, 0x1); // GPIO0 is clock when on USRP1
}
else{
this->get_iface()->set_gpio_ddr(dboard_iface::UNIT_RX, 0x0); // All Inputs
}
//now its safe to set inital freq and bw
this->get_rx_subtree()->access<double>("freq/value")
.set(dbsrx_freq_range.start());
this->get_rx_subtree()->access<double>("bandwidth/value")
.set(2.0*_bandwidth); //_bandwidth in lowpass, convert to complex bandpass
}
/***********************************************************************
* Tuning
**********************************************************************/
double rfx_xcvr::set_lo_freq(
dboard_iface::unit_t unit,
double target_freq
){
UHD_LOGGER_TRACE("RFX") << boost::format(
"RFX tune: target frequency %f MHz"
) % (target_freq/1e6) ;
//clip the input
target_freq = _freq_range.clip(target_freq);
if (_div2[unit]) target_freq *= 2;
//rfx400 rx is a special case with div2 in mixer, so adf4360 must output fundamental
bool is_rx_rfx400 = ((get_rx_id() == 0x0024) && unit != dboard_iface::UNIT_TX);
//map prescalers to the register enums
static const uhd::dict<int, adf4360_regs_t::prescaler_value_t> prescaler_to_enum = map_list_of
(8, adf4360_regs_t::PRESCALER_VALUE_8_9)
(16, adf4360_regs_t::PRESCALER_VALUE_16_17)
(32, adf4360_regs_t::PRESCALER_VALUE_32_33)
;
//map band select clock dividers to enums
static const uhd::dict<int, adf4360_regs_t::band_select_clock_div_t> bandsel_to_enum = map_list_of
(1, adf4360_regs_t::BAND_SELECT_CLOCK_DIV_1)
(2, adf4360_regs_t::BAND_SELECT_CLOCK_DIV_2)
(4, adf4360_regs_t::BAND_SELECT_CLOCK_DIV_4)
(8, adf4360_regs_t::BAND_SELECT_CLOCK_DIV_8)
;
double actual_freq=0, ref_freq = this->get_iface()->get_clock_rate(unit);
int R=0, BS=0, P=0, B=0, A=0;
/*
* The goal here to to loop though possible R dividers,
* band select clock dividers, and prescaler values.
* Calculate the A and B counters for each set of values.
* The loop exits when it meets all of the constraints.
* The resulting loop values are loaded into the registers.
*
* fvco = [P*B + A] * fref/R
* fvco*R/fref = P*B + A = N
*/
for(R = 2; R <= 32; R+=2){
for(auto BS: bandsel_to_enum.keys()){
if (ref_freq/R/BS > 1e6) continue; //constraint on band select clock
for(auto P: prescaler_to_enum.keys()){
//calculate B and A from N
double N = target_freq*R/ref_freq;
B = int(std::floor(N/P));
A = boost::math::iround(N - P*B);
if (B < A or B > 8191 or B < 3 or A > 31) continue; //constraints on A, B
//calculate the actual frequency
actual_freq = double(P*B + A)*ref_freq/R;
if (actual_freq/P > 300e6) continue; //constraint on prescaler output
//constraints met: exit loop
goto done_loop;
}
}
} done_loop:
UHD_LOGGER_TRACE("RFX") << boost::format(
"RFX tune: R=%d, BS=%d, P=%d, B=%d, A=%d, DIV2=%d"
) % R % BS % P % B % A % int(_div2[unit] && (!is_rx_rfx400)) ;
//load the register values
adf4360_regs_t regs;
regs.core_power_level = adf4360_regs_t::CORE_POWER_LEVEL_10MA;
regs.counter_operation = adf4360_regs_t::COUNTER_OPERATION_NORMAL;
regs.muxout_control = adf4360_regs_t::MUXOUT_CONTROL_DLD;
regs.phase_detector_polarity = adf4360_regs_t::PHASE_DETECTOR_POLARITY_POS;
regs.charge_pump_output = adf4360_regs_t::CHARGE_PUMP_OUTPUT_NORMAL;
regs.cp_gain_0 = adf4360_regs_t::CP_GAIN_0_SET1;
regs.mute_till_ld = adf4360_regs_t::MUTE_TILL_LD_ENB;
regs.output_power_level = adf4360_regs_t::OUTPUT_POWER_LEVEL_3_5MA;
regs.current_setting1 = adf4360_regs_t::CURRENT_SETTING1_0_31MA;
regs.current_setting2 = adf4360_regs_t::CURRENT_SETTING2_0_31MA;
regs.power_down = adf4360_regs_t::POWER_DOWN_NORMAL_OP;
regs.prescaler_value = prescaler_to_enum[P];
regs.a_counter = A;
regs.b_counter = B;
regs.cp_gain_1 = adf4360_regs_t::CP_GAIN_1_SET1;
regs.divide_by_2_output = (_div2[unit] && (!is_rx_rfx400)) ? // Special case RFX400 RX Mixer divides by two
adf4360_regs_t::DIVIDE_BY_2_OUTPUT_DIV2 :
adf4360_regs_t::DIVIDE_BY_2_OUTPUT_FUND ;
regs.divide_by_2_prescaler = adf4360_regs_t::DIVIDE_BY_2_PRESCALER_FUND;
regs.r_counter = R;
regs.ablpw = adf4360_regs_t::ABLPW_3_0NS;
regs.lock_detect_precision = adf4360_regs_t::LOCK_DETECT_PRECISION_5CYCLES;
regs.test_mode_bit = 0;
regs.band_select_clock_div = bandsel_to_enum[BS];
//write the registers
std::vector<adf4360_regs_t::addr_t> addrs = list_of //correct power-up sequence to write registers (R, C, N)
(adf4360_regs_t::ADDR_RCOUNTER)
(adf4360_regs_t::ADDR_CONTROL)
(adf4360_regs_t::ADDR_NCOUNTER)
;
for(adf4360_regs_t::addr_t addr: addrs){
this->get_iface()->write_spi(
unit, spi_config_t::EDGE_RISE,
regs.get_reg(addr), 24
);
}
//return the actual frequency
if (_div2[unit]) actual_freq /= 2;
UHD_LOGGER_TRACE("RFX") << boost::format(
"RFX tune: actual frequency %f MHz"
) % (actual_freq/1e6) ;
return actual_freq;
}
/***********************************************************************
* Tuning
**********************************************************************/
double wbx_base::wbx_version4::set_lo_freq(dboard_iface::unit_t unit, double target_freq) {
//clip to tuning range
target_freq = wbx_v4_freq_range.clip(target_freq);
UHD_LOGV(often) << boost::format(
"WBX tune: target frequency %f Mhz"
) % (target_freq/1e6) << std::endl;
/*
* If the user sets 'mode_n=integer' in the tuning args, the user wishes to
* tune in Integer-N mode, which can result in better spur
* performance on some mixers. The default is fractional tuning.
*/
property_tree::sptr subtree = (unit == dboard_iface::UNIT_RX) ? self_base->get_rx_subtree()
: self_base->get_tx_subtree();
device_addr_t tune_args = subtree->access<device_addr_t>("tune_args").get();
bool is_int_n = boost::iequals(tune_args.get("mode_n",""), "integer");
//map prescaler setting to mininmum integer divider (N) values (pg.18 prescaler)
static const uhd::dict<int, int> prescaler_to_min_int_div = map_list_of
(0,23) //adf4351_regs_t::PRESCALER_4_5
(1,75) //adf4351_regs_t::PRESCALER_8_9
;
//map rf divider select output dividers to enums
static const uhd::dict<int, adf4351_regs_t::rf_divider_select_t> rfdivsel_to_enum = map_list_of
(1, adf4351_regs_t::RF_DIVIDER_SELECT_DIV1)
(2, adf4351_regs_t::RF_DIVIDER_SELECT_DIV2)
(4, adf4351_regs_t::RF_DIVIDER_SELECT_DIV4)
(8, adf4351_regs_t::RF_DIVIDER_SELECT_DIV8)
(16, adf4351_regs_t::RF_DIVIDER_SELECT_DIV16)
(32, adf4351_regs_t::RF_DIVIDER_SELECT_DIV32)
(64, adf4351_regs_t::RF_DIVIDER_SELECT_DIV64)
;
double reference_freq = self_base->get_iface()->get_clock_rate(unit);
//The mixer has a divide-by-2 stage on the LO port so the synthesizer
//frequency must 2x the target frequency
double synth_target_freq = target_freq * 2;
//TODO: Document why the following has to be true
bool div_resync_enabled = (target_freq > reference_freq);
adf4351_regs_t::prescaler_t prescaler =
synth_target_freq > 3e9 ? adf4351_regs_t::PRESCALER_8_9 : adf4351_regs_t::PRESCALER_4_5;
adf435x_tuning_constraints tuning_constraints;
tuning_constraints.force_frac0 = is_int_n;
tuning_constraints.band_sel_freq_max = 100e3;
tuning_constraints.ref_doubler_threshold = 12.5e6;
tuning_constraints.int_range = uhd::range_t(prescaler_to_min_int_div[prescaler], 4095);
tuning_constraints.pfd_freq_max = 25e6;
tuning_constraints.rf_divider_range = uhd::range_t(1, 64);
//When divider resync is enabled, a 180 deg phase error is introduced when syncing
//multiple WBX boards. Switching to fundamental mode works arounds this issue.
tuning_constraints.feedback_after_divider = div_resync_enabled;
double synth_actual_freq = 0;
adf435x_tuning_settings tuning_settings = tune_adf435x_synth(
synth_target_freq, reference_freq, tuning_constraints, synth_actual_freq);
//The mixer has a divide-by-2 stage on the LO port so the synthesizer
//actual_freq must /2 the synth_actual_freq
double actual_freq = synth_actual_freq / 2;
//load the register values
adf4351_regs_t regs;
if (unit == dboard_iface::UNIT_RX)
regs.output_power = (actual_freq == wbx_rx_lo_5dbm.clip(actual_freq)) ? adf4351_regs_t::OUTPUT_POWER_5DBM
: adf4351_regs_t::OUTPUT_POWER_2DBM;
else
regs.output_power = (actual_freq == wbx_tx_lo_5dbm.clip(actual_freq)) ? adf4351_regs_t::OUTPUT_POWER_5DBM
: adf4351_regs_t::OUTPUT_POWER_M1DBM;
regs.frac_12_bit = tuning_settings.frac_12_bit;
regs.int_16_bit = tuning_settings.int_16_bit;
regs.mod_12_bit = tuning_settings.mod_12_bit;
regs.clock_divider_12_bit = tuning_settings.clock_divider_12_bit;
regs.feedback_select = tuning_constraints.feedback_after_divider ?
adf4351_regs_t::FEEDBACK_SELECT_DIVIDED :
adf4351_regs_t::FEEDBACK_SELECT_FUNDAMENTAL;
regs.clock_div_mode = div_resync_enabled ?
adf4351_regs_t::CLOCK_DIV_MODE_RESYNC_ENABLE :
adf4351_regs_t::CLOCK_DIV_MODE_FAST_LOCK;
regs.prescaler = prescaler;
regs.r_counter_10_bit = tuning_settings.r_counter_10_bit;
regs.reference_divide_by_2 = tuning_settings.r_divide_by_2_en ?
adf4351_regs_t::REFERENCE_DIVIDE_BY_2_ENABLED :
adf4351_regs_t::REFERENCE_DIVIDE_BY_2_DISABLED;
regs.reference_doubler = tuning_settings.r_doubler_en ?
adf4351_regs_t::REFERENCE_DOUBLER_ENABLED :
adf4351_regs_t::REFERENCE_DOUBLER_DISABLED;
regs.band_select_clock_div = tuning_settings.band_select_clock_div;
UHD_ASSERT_THROW(rfdivsel_to_enum.has_key(tuning_settings.rf_divider));
regs.rf_divider_select = rfdivsel_to_enum[tuning_settings.rf_divider];
regs.ldf = is_int_n ?
adf4351_regs_t::LDF_INT_N :
adf4351_regs_t::LDF_FRAC_N;
//reset the N and R counter
regs.counter_reset = adf4351_regs_t::COUNTER_RESET_ENABLED;
self_base->get_iface()->write_spi(unit, spi_config_t::EDGE_RISE, regs.get_reg(2), 32);
regs.counter_reset = adf4351_regs_t::COUNTER_RESET_DISABLED;
//write the registers
//correct power-up sequence to write registers (5, 4, 3, 2, 1, 0)
int addr;
boost::uint16_t rx_id = self_base->get_rx_id().to_uint16();
std::string board_name = (rx_id == 0x0081) ? "WBX-120" : "WBX";
for(addr=5; addr>=0; addr--){
UHD_LOGV(often) << boost::format(
"%s SPI Reg (0x%02x): 0x%08x"
) % board_name.c_str() % addr % regs.get_reg(addr) << std::endl;
self_base->get_iface()->write_spi(
unit, spi_config_t::EDGE_RISE,
regs.get_reg(addr), 32
);
}
//return the actual frequency
UHD_LOGV(often) << boost::format(
"%s tune: actual frequency %f Mhz"
) % board_name.c_str() % (actual_freq/1e6) << std::endl;
return actual_freq;
}
/***********************************************************************
* TX Get and Set
**********************************************************************/
void xcvr2450::tx_get(const wax::obj &key_, wax::obj &val) {
named_prop_t key = named_prop_t::extract(key_);
//handle the get request conditioned on the key
switch(key.as<subdev_prop_t>()) {
case SUBDEV_PROP_NAME:
val = get_tx_id().to_pp_string();
return;
case SUBDEV_PROP_OTHERS:
val = prop_names_t(); //empty
return;
case SUBDEV_PROP_GAIN:
assert_has(_tx_gains.keys(), key.name, "xcvr tx gain name");
val = _tx_gains[key.name];
return;
case SUBDEV_PROP_GAIN_RANGE:
assert_has(xcvr_tx_gain_ranges.keys(), key.name, "xcvr tx gain name");
val = xcvr_tx_gain_ranges[key.name];
return;
case SUBDEV_PROP_GAIN_NAMES:
val = prop_names_t(xcvr_tx_gain_ranges.keys());
return;
case SUBDEV_PROP_FREQ:
val = _lo_freq;
return;
case SUBDEV_PROP_FREQ_RANGE:
val = xcvr_freq_range;
return;
case SUBDEV_PROP_ANTENNA:
val = _tx_ant;
return;
case SUBDEV_PROP_ANTENNA_NAMES:
val = xcvr_antennas;
return;
case SUBDEV_PROP_CONNECTION:
val = SUBDEV_CONN_COMPLEX_QI;
return;
case SUBDEV_PROP_ENABLED:
val = true; //always enabled
return;
case SUBDEV_PROP_USE_LO_OFFSET:
val = false;
return;
case SUBDEV_PROP_LO_LOCKED:
val = this->get_locked();
return;
case SUBDEV_PROP_BANDWIDTH:
val = 2*_tx_bandwidth; //_tx_bandwidth is low-pass, we want complex double-sided
return;
default:
UHD_THROW_PROP_GET_ERROR();
}
}
/***********************************************************************
* RX Get and Set
**********************************************************************/
void dbsrx::rx_get(const wax::obj &key_, wax::obj &val){
named_prop_t key = named_prop_t::extract(key_);
//handle the get request conditioned on the key
switch(key.as<subdev_prop_t>()){
case SUBDEV_PROP_NAME:
val = get_rx_id().to_pp_string();
return;
case SUBDEV_PROP_OTHERS:
val = prop_names_t(); //empty
return;
case SUBDEV_PROP_GAIN:
assert_has(_gains.keys(), key.name, "dbsrx gain name");
val = _gains[key.name];
return;
case SUBDEV_PROP_GAIN_RANGE:
assert_has(dbsrx_gain_ranges.keys(), key.name, "dbsrx gain name");
val = dbsrx_gain_ranges[key.name];
return;
case SUBDEV_PROP_GAIN_NAMES:
val = prop_names_t(dbsrx_gain_ranges.keys());
return;
case SUBDEV_PROP_FREQ:
val = _lo_freq;
return;
case SUBDEV_PROP_FREQ_RANGE:
val = dbsrx_freq_range;
return;
case SUBDEV_PROP_ANTENNA:
val = std::string("J3");
return;
case SUBDEV_PROP_ANTENNA_NAMES:
val = dbsrx_antennas;
return;
case SUBDEV_PROP_CONNECTION:
val = SUBDEV_CONN_COMPLEX_IQ;
return;
case SUBDEV_PROP_ENABLED:
val = true; //always enabled
return;
case SUBDEV_PROP_USE_LO_OFFSET:
val = false;
return;
case SUBDEV_PROP_SENSOR:
UHD_ASSERT_THROW(key.name == "lo_locked");
val = sensor_value_t("LO", this->get_locked(), "locked", "unlocked");
return;
case SUBDEV_PROP_SENSOR_NAMES:
val = prop_names_t(1, "lo_locked");
return;
case SUBDEV_PROP_BANDWIDTH:
val = 2*_bandwidth; //_bandwidth is low-pass, we want complex double-sided
return;
default: UHD_THROW_PROP_GET_ERROR();
}
}
/***********************************************************************
* Structors
**********************************************************************/
xcvr2450::xcvr2450(ctor_args_t args) : xcvr_dboard_base(args){
spi_reset(); //prepare the spi
_rx_bandwidth = 9.5e6;
_tx_bandwidth = 12.0e6;
//setup the misc max2829 registers
_max2829_regs.mimo_select = max2829_regs_t::MIMO_SELECT_MIMO;
_max2829_regs.band_sel_mimo = max2829_regs_t::BAND_SEL_MIMO_MIMO;
_max2829_regs.pll_cp_select = max2829_regs_t::PLL_CP_SELECT_4MA;
_max2829_regs.rssi_high_bw = max2829_regs_t::RSSI_HIGH_BW_6MHZ;
_max2829_regs.tx_lpf_coarse_adj = max2829_regs_t::TX_LPF_COARSE_ADJ_12MHZ;
_max2829_regs.rx_lpf_coarse_adj = max2829_regs_t::RX_LPF_COARSE_ADJ_9_5MHZ;
_max2829_regs.rx_lpf_fine_adj = max2829_regs_t::RX_LPF_FINE_ADJ_100;
_max2829_regs.rx_vga_gain_spi = max2829_regs_t::RX_VGA_GAIN_SPI_SPI;
_max2829_regs.rssi_output_range = max2829_regs_t::RSSI_OUTPUT_RANGE_HIGH;
_max2829_regs.rssi_op_mode = max2829_regs_t::RSSI_OP_MODE_ENABLED;
_max2829_regs.rssi_pin_fcn = max2829_regs_t::RSSI_PIN_FCN_RSSI;
_max2829_regs.rx_highpass = max2829_regs_t::RX_HIGHPASS_100HZ;
_max2829_regs.tx_vga_gain_spi = max2829_regs_t::TX_VGA_GAIN_SPI_SPI;
_max2829_regs.pa_driver_linearity = max2829_regs_t::PA_DRIVER_LINEARITY_78;
_max2829_regs.tx_vga_linearity = max2829_regs_t::TX_VGA_LINEARITY_78;
_max2829_regs.tx_upconv_linearity = max2829_regs_t::TX_UPCONV_LINEARITY_78;
//send initial register settings
for(boost::uint8_t reg = 0x2; reg <= 0xC; reg++){
this->send_reg(reg);
}
////////////////////////////////////////////////////////////////////
// Register RX properties
////////////////////////////////////////////////////////////////////
this->get_rx_subtree()->create<std::string>("name")
.set(get_rx_id().to_pp_string());
this->get_rx_subtree()->create<sensor_value_t>("sensors/lo_locked")
.publish(boost::bind(&xcvr2450::get_locked, this));
this->get_rx_subtree()->create<sensor_value_t>("sensors/rssi")
.publish(boost::bind(&xcvr2450::get_rssi, this));
BOOST_FOREACH(const std::string &name, xcvr_rx_gain_ranges.keys()){
this->get_rx_subtree()->create<double>("gains/"+name+"/value")
.coerce(boost::bind(&xcvr2450::set_rx_gain, this, _1, name))
.set(xcvr_rx_gain_ranges[name].start());
this->get_rx_subtree()->create<meta_range_t>("gains/"+name+"/range")
.set(xcvr_rx_gain_ranges[name]);
}
this->get_rx_subtree()->create<double>("freq/value")
.coerce(boost::bind(&xcvr2450::set_lo_freq, this, _1))
.set(double(2.45e9));
this->get_rx_subtree()->create<meta_range_t>("freq/range")
.set(xcvr_freq_range);
this->get_rx_subtree()->create<std::string>("antenna/value")
.subscribe(boost::bind(&xcvr2450::set_rx_ant, this, _1))
.set(xcvr_antennas.at(0));
this->get_rx_subtree()->create<std::vector<std::string> >("antenna/options")
.set(xcvr_antennas);
this->get_rx_subtree()->create<std::string>("connection")
.set("IQ");
this->get_rx_subtree()->create<bool>("enabled")
.set(true); //always enabled
this->get_rx_subtree()->create<bool>("use_lo_offset")
.set(false);
this->get_rx_subtree()->create<double>("bandwidth/value")
.coerce(boost::bind(&xcvr2450::set_rx_bandwidth, this, _1)) //complex bandpass bandwidth
.set(2.0*_rx_bandwidth); //_rx_bandwidth in lowpass, convert to complex bandpass
this->get_rx_subtree()->create<meta_range_t>("bandwidth/range")
.set(xcvr_rx_bandwidth_range);
////////////////////////////////////////////////////////////////////
// Register TX properties
////////////////////////////////////////////////////////////////////
this->get_tx_subtree()->create<std::string>("name")
.set(get_tx_id().to_pp_string());
this->get_tx_subtree()->create<sensor_value_t>("sensors/lo_locked")
.publish(boost::bind(&xcvr2450::get_locked, this));
BOOST_FOREACH(const std::string &name, xcvr_tx_gain_ranges.keys()){
this->get_tx_subtree()->create<double>("gains/"+name+"/value")
.coerce(boost::bind(&xcvr2450::set_tx_gain, this, _1, name))
.set(xcvr_tx_gain_ranges[name].start());
this->get_tx_subtree()->create<meta_range_t>("gains/"+name+"/range")
.set(xcvr_tx_gain_ranges[name]);
}
this->get_tx_subtree()->create<double>("freq/value")
.coerce(boost::bind(&xcvr2450::set_lo_freq, this, _1))
.set(double(2.45e9));
this->get_tx_subtree()->create<meta_range_t>("freq/range")
.set(xcvr_freq_range);
this->get_tx_subtree()->create<std::string>("antenna/value")
.subscribe(boost::bind(&xcvr2450::set_tx_ant, this, _1))
.set(xcvr_antennas.at(1));
this->get_tx_subtree()->create<std::vector<std::string> >("antenna/options")
.set(xcvr_antennas);
this->get_tx_subtree()->create<std::string>("connection")
.set("QI");
this->get_tx_subtree()->create<bool>("enabled")
.set(true); //always enabled
this->get_tx_subtree()->create<bool>("use_lo_offset")
.set(true);
this->get_tx_subtree()->create<double>("bandwidth/value")
.coerce(boost::bind(&xcvr2450::set_tx_bandwidth, this, _1)) //complex bandpass bandwidth
.set(2.0*_tx_bandwidth); //_tx_bandwidth in lowpass, convert to complex bandpass
this->get_tx_subtree()->create<meta_range_t>("bandwidth/range")
.set(xcvr_tx_bandwidth_range);
//enable only the clocks we need
this->get_iface()->set_clock_enabled(dboard_iface::UNIT_TX, true);
//set the gpio directions and atr controls (identically)
this->get_iface()->set_pin_ctrl(dboard_iface::UNIT_TX, TXIO_MASK);
this->get_iface()->set_pin_ctrl(dboard_iface::UNIT_RX, RXIO_MASK);
this->get_iface()->set_gpio_ddr(dboard_iface::UNIT_TX, TXIO_MASK);
this->get_iface()->set_gpio_ddr(dboard_iface::UNIT_RX, RXIO_MASK);
}
