/***************************************************************************//**
* @brief Writes data into a register.
*
* @param dev - The device structure.
* @param register_address - Address of the register.
* Example:
* AD5755_DREG_WR_DAC
* AD5755_DREG_WR_GAIN
* AD5755_DREG_WR_GAIN_ALL
* AD5755_DREG_WR_OFFSET
* AD5755_DREG_WR_OFFSET_ALL
* AD5755_DREG_WR_CLR_CODE
* AD5755_DREG_WR_CTRL_REG
*
* @param channel - Channel option.
* Example: AD5755_DAC_A
* AD5755_DAC_B
* AD5755_DAC_C
* AD5755_DAC_D
* @param register_value - Data value to write.
*
* @return None.
*******************************************************************************/
uint16_t ad5755_set_register_value(struct ad5755_dev *dev,
uint8_t register_address,
uint8_t channel,
uint16_t register_value)
{
uint8_t buff[4] = {0, 0, 0, 0};
uint32_t command = 0;
uint16_t status_reg = 0;
command = AD5755_ISR_WRITE |
AD5755_ISR_DUT_AD1(dev->p_ad5755_st->pin_ad1state) |
AD5755_ISR_DUT_AD0(dev->p_ad5755_st->pin_ad0state) |
AD5755_ISR_DREG(register_address) |
AD5755_ISR_DAC_AD(channel)|
AD5755_ISR_DATA(register_value);
buff[0] = (command & 0xFF0000) >> 16;
buff[1] = (command & 0x00FF00) >> 8;
buff[2] = (command & 0x0000FF) >> 0;
if(dev->p_ad5755_st->enable_packet_error_check) {
buff[3] = ad5755_check_crc(buff, 3);
}
if(dev->p_ad5755_st->stat_readbit == 0) {
spi_write_and_read(dev->spi_desc,
buff,
3 + dev->p_ad5755_st->enable_packet_error_check);
} else {
spi_write_and_read(dev->spi_desc,
buff,
3 + dev->p_ad5755_st->enable_packet_error_check);
status_reg = (buff[1] << 8) + buff[2];
}
return status_reg;
}
/***************************************************************************//**
* @brief Reads the value of a register.
*
* @param registerAddress - Address of the register.
* Example:
* AD5755_RD_DATA_REG(x)
* AD5755_RD_CTRL_REG(x)
* AD5755_RD_GAIN_REG(x)
* AD5755_RD_OFFSET_REG(x)
* AD5755_RD_CODE_REG(x)
* AD5755_RD_SR_CTRL_REG(x)
* AD5755_RD_STATUS_REG
* AD5755_RD_MAIN_CTRL_REG
* AD5755_RD_Dc_DC_CTRL_REG
* x = any of AD5755_DAC_A, .. AD5755_DAC_D
*
* @return regValue - Value of the register.
*******************************************************************************/
long AD5755_GetRegisterValue(unsigned char registerAddress)
{
unsigned char buffer[4] = {0, 0, 0, 0};
unsigned long command = 0;
long regValue = 0;
unsigned char crc = 0;
command = AD5755_ISR_READ |
AD5755_ISR_DUT_AD1(AD5755_st.pinAD1state) |
AD5755_ISR_DUT_AD0(AD5755_st.pinAD0state) |
AD5755_ISR_RD(registerAddress);
buffer[0] = (command & 0xFF0000) >> 16;
buffer[1] = (command & 0x00FF00) >> 8;
buffer[2] = (command & 0x0000FF) >> 0;
if(AD5755_st.enablePacketErrorCheck)
{
buffer[3] = AD5755_CheckCrc(buffer, 3);
}
SPI_Write(AD5755_SLAVE_ID,
buffer,
3 + AD5755_st.enablePacketErrorCheck);
command = AD5755_ISR_WRITE |
AD5755_ISR_DUT_AD1(AD5755_st.pinAD1state) |
AD5755_ISR_DUT_AD0(AD5755_st.pinAD0state) |
AD5755_ISR_NOP;
buffer[0] = (command & 0xFF0000) >> 16;
buffer[1] = (command & 0x00FF00) >> 8;
buffer[2] = (command & 0x0000FF) >> 0;
if(AD5755_st.enablePacketErrorCheck)
{
buffer[3] = AD5755_CheckCrc(buffer, 3);
}
SPI_Read(AD5755_SLAVE_ID,
buffer,
3 + AD5755_st.enablePacketErrorCheck);
regValue = ((unsigned short)buffer[1] << 8) + buffer[2];
/* Check the CRC. */
if(AD5755_st.enablePacketErrorCheck)
{
crc = AD5755_CheckCrc(&buffer[1], 3);
if(crc != AD5755_CRC_CHECK_CODE)
{
regValue = -1;
}
}
return regValue;
}
/***************************************************************************//**
* @brief Reads the value of a register.
*
* @param dev - The device structure.
* @param register_address - Address of the register.
* Example:
* AD5755_RD_DATA_REG(x)
* AD5755_RD_CTRL_REG(x)
* AD5755_RD_GAIN_REG(x)
* AD5755_RD_OFFSET_REG(x)
* AD5755_RD_CODE_REG(x)
* AD5755_RD_SR_CTRL_REG(x)
* AD5755_RD_STATUS_REG
* AD5755_RD_MAIN_CTRL_REG
* AD5755_RD_Dc_DC_CTRL_REG
* x = any of AD5755_DAC_A, .. AD5755_DAC_D
*
* @return regValue - Value of the register.
*******************************************************************************/
int32_t ad5755_get_register_value(struct ad5755_dev *dev,
uint8_t register_address)
{
uint8_t buffer[4] = {0, 0, 0, 0};
uint32_t command = 0;
int32_t reg_value = 0;
uint8_t crc = 0;
command = AD5755_ISR_READ |
AD5755_ISR_DUT_AD1(dev->p_ad5755_st->pin_ad1state) |
AD5755_ISR_DUT_AD0(dev->p_ad5755_st->pin_ad0state) |
AD5755_ISR_RD(register_address);
buffer[0] = (command & 0xFF0000) >> 16;
buffer[1] = (command & 0x00FF00) >> 8;
buffer[2] = (command & 0x0000FF) >> 0;
if(dev->p_ad5755_st->enable_packet_error_check) {
buffer[3] = ad5755_check_crc(buffer, 3);
}
spi_write_and_read(dev->spi_desc,
buffer,
3 + dev->p_ad5755_st->enable_packet_error_check);
command = AD5755_ISR_WRITE |
AD5755_ISR_DUT_AD1(dev->p_ad5755_st->pin_ad1state) |
AD5755_ISR_DUT_AD0(dev->p_ad5755_st->pin_ad0state) |
AD5755_ISR_NOP;
buffer[0] = (command & 0xFF0000) >> 16;
buffer[1] = (command & 0x00FF00) >> 8;
buffer[2] = (command & 0x0000FF) >> 0;
if(dev->p_ad5755_st->enable_packet_error_check) {
buffer[3] = ad5755_check_crc(buffer, 3);
}
spi_write_and_read(dev->spi_desc,
buffer,
3 + dev->p_ad5755_st->enable_packet_error_check);
reg_value = ((uint16_t)buffer[1] << 8) + buffer[2];
/* Check the CRC. */
if(dev->p_ad5755_st->enable_packet_error_check) {
crc = ad5755_check_crc(&buffer[1], 3);
if(crc != AD5755_CRC_CHECK_CODE) {
reg_value = -1;
}
}
return reg_value;
}
/***************************************************************************//**
* @brief Writes data into a register.
*
* @param registerAddress - Address of the register.
* Example:
* AD5755_DREG_WR_DAC
* AD5755_DREG_WR_GAIN
* AD5755_DREG_WR_GAIN_ALL
* AD5755_DREG_WR_OFFSET
* AD5755_DREG_WR_OFFSET_ALL
* AD5755_DREG_WR_CLR_CODE
* AD5755_DREG_WR_CTRL_REG
*
* @param channel - Channel option.
* Example: AD5755_DAC_A
* AD5755_DAC_B
* AD5755_DAC_C
* AD5755_DAC_D
* @param registerValue - Data value to write.
*
* @return None.
*******************************************************************************/
unsigned short AD5755_SetRegisterValue(unsigned char registerAddress,
unsigned char channel,
unsigned short registerValue)
{
unsigned char buff[4] = {0, 0, 0, 0};
unsigned long command = 0;
unsigned short statusReg = 0;
command = AD5755_ISR_WRITE |
AD5755_ISR_DUT_AD1(AD5755_st.pinAD1state) |
AD5755_ISR_DUT_AD0(AD5755_st.pinAD0state) |
AD5755_ISR_DREG(registerAddress) |
AD5755_ISR_DAC_AD(channel)|
AD5755_ISR_DATA(registerValue);
buff[0] = (command & 0xFF0000) >> 16;
buff[1] = (command & 0x00FF00) >> 8;
buff[2] = (command & 0x0000FF) >> 0;
if(AD5755_st.enablePacketErrorCheck)
{
buff[3] = AD5755_CheckCrc(buff, 3);
}
if(AD5755_st.statReadBit == 0)
{
SPI_Write(AD5755_SLAVE_ID,
buff,
3 + AD5755_st.enablePacketErrorCheck);
}
else
{
SPI_Read(AD5755_SLAVE_ID,
buff,
3 + AD5755_st.enablePacketErrorCheck);
statusReg = (buff[1] << 8) + buff[2];
}
return statusReg;
}
