void
ahci_enable_intrs(struct ahci_softc *sc)
{
/* clear interrupts */
AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS));
/* enable interrupts */
AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE);
}
static void
ahci_setup_port(struct ahci_softc *sc, int i)
{
struct ahci_channel *achp;
achp = &sc->sc_channels[i];
AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh);
AHCI_WRITE(sc, AHCI_P_CLBU(i), 0);
AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis);
AHCI_WRITE(sc, AHCI_P_FBU(i), 0);
}
void
ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp)
{
u_int32_t is, tfd;
struct ata_channel *chp = &achp->ata_channel;
struct ata_xfer *xfer = chp->ch_queue->active_xfer;
int slot;
is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel));
AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is);
AHCIDEBUG_PRINT(("ahci_intr_port %s port %d is 0x%x CI 0x%x\n", AHCINAME(sc),
chp->ch_channel, is, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))),
DEBUG_INTR);
if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS |
AHCI_P_IX_OFS | AHCI_P_IX_UFS)) {
slot = (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))
& AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT;
if ((achp->ahcic_cmds_active & (1 << slot)) == 0)
return;
/* stop channel */
ahci_channel_stop(sc, chp, 0);
if (slot != 0) {
printf("ahci_intr_port: slot %d\n", slot);
panic("ahci_intr_port");
}
if (is & AHCI_P_IX_TFES) {
tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel));
chp->ch_error =
(tfd & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT;
chp->ch_status = (tfd & 0xff);
} else {
static void
awin_ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp)
{
bus_size_t dma_reg = AHCI_P_AWIN_DMA(chp->ch_channel);
uint32_t dma = AHCI_READ(sc, dma_reg);
dma &= ~0xff00;
dma |= 0x4400;
AHCI_WRITE(sc, dma_reg, dma);
}
int
ahci_reset(struct ahci_softc *sc)
{
int i;
/* reset controller */
AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR);
/* wait up to 1s for reset to complete */
for (i = 0; i < 1000; i++) {
delay(1000);
if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0)
break;
}
if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) {
aprint_error("%s: reset failed\n", AHCINAME(sc));
return -1;
}
/* enable ahci mode */
AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_AE);
return 0;
}
int
ahci_intr(void *v)
{
struct ahci_softc *sc = v;
u_int32_t is;
int i, r = 0;
while ((is = AHCI_READ(sc, AHCI_IS))) {
AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is),
DEBUG_INTR);
r = 1;
AHCI_WRITE(sc, AHCI_IS, is);
for (i = 0; i < AHCI_MAX_PORTS; i++)
if (is & (1 << i))
ahci_intr_port(sc, &sc->sc_channels[i]);
}
return r;
}
