/*
* AIC3204 init
*
* Route codec from LINE IN to LINE OUT
*/
void aic3204_init(Uint8 rate, Int8 micGain)
{
/* Configure AIC3204 */
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 1, 0x01 ); // Reset codec
EZDSP5535_waitusec(1000); // Wait 1ms after reset
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 1, 0x08 ); // Disable crude AVDD generation from DVDD
AIC3204_rset( 2, 0x01 ); // Enable Analog Blocks, use LDO power
AIC3204_rset( 123,0x05 ); // Force reference to power up in 40ms
// EZDSP5535_waitusec(40000); // Wait at least 40ms
AIC3204_rset( 0, 0x00 ); // Select page 0
/* PLL and Clocks config and Power Up */
AIC3204_rset( 27, 0x0d ); // BCLK and WCLK are set as o/p; AIC3204(Master)
AIC3204_rset( 28, 0x00 ); // Data ofset = 0
AIC3204_rset( 4, 0x03 ); // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK
AIC3204_rset( 6, 0x07 ); // PLL setting: J=7
AIC3204_rset( 7, 0x06 ); // PLL setting: HI_BYTE(D=1680)
AIC3204_rset( 8, 0x90 ); // PLL setting: LO_BYTE(D=1680)
// For 32 bit clocks per frame in Master mode ONLY
// BCLK=DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs
// MCLK = 12MHz(fangyuang, 2012-06-22)
AIC3204_rset( 30, 0x88 );
AIC3204_rset( 5, 0x91 ); // PLL setting: Power up PLL, P=1 and R=1
// EZDSP5535_waitusec(10000); // Wait for PLL to come up
AIC3204_rset( 13, 0x00 ); // Hi_Byte(DOSR) for DOSR = 128 decimal or 0x0080 DAC oversamppling
AIC3204_rset( 14, 0x80 ); // Lo_Byte(DOSR) for DOSR = 128 decimal or 0x0080
AIC3204_rset( 20, 0x80 ); // AOSR for AOSR = 128 decimal or 0x0080 for decimation filters 1 to 6
/* sampling rate = CLOCK/(NADC*MADC) */
AIC3204_rset( 11, 0x80+rate); // Power up NDAC and set NDAC value to rate
AIC3204_rset( 12, 0x87 ); // Power up MDAC and set MDAC value to 7
AIC3204_rset( 18, 0x87 ); // Power up NADC and set NADC value to 7
AIC3204_rset( 19, 0x80+rate); // Power up MADC and set MADC value to rate
AIC3204_rset( 64, 0x02 ); // Left vol=right vol
AIC3204_rset( 65, 0x00 ); // Left DAC gain to 0dB VOL; Right tracks Left
AIC3204_rset( 63, 0xd4 ); // Power up left,right data paths and set channel
AIC3204_rset( 81, 0xc0 ); // Powerup Left and Right ADC
AIC3204_rset( 82, 0x00 ); // Unmute Left and Right ADC, fine gain=0dB
AIC3204_rset( 83, 0x20 ); // Left ADC gain, -12dB~+20dB, 01100111~00101000, stepsize 0.5dB
AIC3204_rset( 84, 0x20 ); // Right ADC gain, -12dB~+20dB, 01100111~00101000, stepsize 0.5dB
/* DAC ROUTING and Power Up */
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 12, 0x08 ); // LDAC AFIR routed to HPL
AIC3204_rset( 13, 0x08 ); // RDAC AFIR routed to HPR
AIC3204_rset( 16, 0x00 ); // Unmute HPL , 0dB gain
AIC3204_rset( 17, 0x00 ); // Unmute HPR , 0dB gain
AIC3204_rset( 9 , 0x30 ); // Power up HPL,HPR
// EZDSP5535_waitusec(100 ); // Wait
/* ADC ROUTING and Power Up */
AIC3204_rset( 52, 0x30 ); // STEREO 1 Jack
// IN2_L to LADC_P through 40 kohm
AIC3204_rset( 55, 0x30 ); // IN2_R to RADC_P through 40 kohmm
AIC3204_rset( 54, 0x03 ); // CM_1 (common mode) to LADC_M through 40 kohm
AIC3204_rset( 57, 0xc0 ); // CM_1 (common mode) to RADC_M through 40 kohm
AIC3204_rset( 59, micGain );// MIC_PGA_L 0~47.5dB, 0.5dB stepsize
AIC3204_rset( 60, micGain );// MIC_PGA_R 0~47.5dB, 0.5dB stepsize
}
void AIC3204_Init(void)
{
/* Define sampling rate parameters */
unsigned char pll_dh, pll_dl, madc, mdac, nadc, ndac;
/* Initialize BSL */
USBSTK5515_init();
/* Configure Serial Bus */
SYS_EXBUSSEL |= 0x0100; // Configure Serial bus 0 for I2S0
/* Set Sampling Rate */
if(fs == AIC3204_FS_44_1KHZ)
{
// PLL D = 560
pll_dh = 0x02;
pll_dl = 0x30;
// MDAC & MACC = 3
madc = 0x03;
mdac = 0x03;
// NDAC & NADC = 5
nadc = 0x05;
ndac = 0x05;
}
else // 8, 16, 24, 32, 48, 96 KHz
{
// PLL D = 1680
pll_dh = 0x06;
pll_dl = 0x90;
switch(fs) {
case AIC3204_FS_8KHZ:
madc = 0x0C;
mdac = 0x0C;
break;
case AIC3204_FS_16KHZ:
madc = 0x06;
mdac = 0x06;
break;
case AIC3204_FS_24KHZ:
madc = 0x04;
mdac = 0x04;
break;
case AIC3204_FS_32KHZ:
madc = 0x03;
mdac = 0x03;
break;
case AIC3204_FS_48KHZ:
madc = 0x02;
mdac = 0x02;
break;
case AIC3204_FS_96KHZ:
madc = 0x01;
mdac = 0x01;
break;
}
// NDAC & NADC = 7
nadc = 0x07;
ndac = 0x07;
}
/* Configure AIC3204 */
AIC3204_rset( 0, 0 ); // Select page 1
AIC3204_rset( 1, 1 ); // Reset codec
AIC3204_rset( 0, 1 ); // Point to page 1
AIC3204_rset( 1, 8 ); // Disable crude AVDD generation from DVDD
AIC3204_rset( 2, 1 ); // Enable Analog Blocks, use LDO power
AIC3204_rset( 0, 0 );
/* PLL and Clocks config and Power Up */
AIC3204_rset(27, 0x0D); // BCLK and WCLK is set as o/p to AIC3204(Master)
AIC3204_rset(28, 0x00); // Data ofset = 0
AIC3204_rset(4, 3); // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK
AIC3204_rset(6, 0x07); // Set PLL J
AIC3204_rset(7, pll_dh); // PLL setting: D HI_BYTE(5:0)
AIC3204_rset(8, pll_dl); // PLL setting: D LO_BYTE(7:0)
AIC3204_rset(30, 0x88); // For 32 bit clocks per frame in Master mode ONLY
// BCLK=DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs
AIC3204_rset(5, 0x91); //PLL setting: Power up PLL, P=1 and R=1
AIC3204_rset(13, 0x00); // DOSR Hi_Byte(1:0) = 0
AIC3204_rset(14, 0x80); // DOSR Lo_Byte(7:0) = 128
AIC3204_rset(20, 0x80); // AOSR (7:0) = 128
AIC3204_rset(11, 0x80 | ndac); // Power up NDAC and set NDAC value
AIC3204_rset(12, 0x80 | mdac); // Power up MDAC and set MDAC value
AIC3204_rset(18, 0x80 | nadc); // Power up NADC and set NADC value
AIC3204_rset(19, 0x80 | madc); // Power up MADC and set MADC value
/* DAC ROUTING and Power Up */
AIC3204_rset( 0, 1 ); // Select page 1
AIC3204_rset( 0x0c, 8 ); // LDAC AFIR routed to HPL
AIC3204_rset( 0x0d, 8 ); // RDAC AFIR routed to HPR
AIC3204_rset( 0, 0 ); // Select page 0
AIC3204_rset( 64, 2 ); // Left vol=right vol
AIC3204_rset( 65, 0 ); // Left DAC gain to 0dB VOL; Right tracks Left
AIC3204_rset( 63, 0xd4 ); // Power up left,right data paths and set channel
AIC3204_rset( 0, 1 ); // Select page 1
AIC3204_rset( 0x10, 0 ); // Unmute HPL , 0dB gain
AIC3204_rset( 0x11, 0 ); // Unmute HPR , 0dB gain
AIC3204_rset( 9, 0x30 ); // Power up HPL,HPR
AIC3204_rset( 0, 0 ); // Select page 0
USBSTK5515_wait( 100 ); // wait
/* ADC ROUTING and Power Up */
AIC3204_rset( 0, 1 ); // Select page 1
AIC3204_rset( 0x33, 0x00 );// Disable MICBIAS
AIC3204_rset( 0x34, 0x10 );// STEREO 1 Jack
// IN2_L to LADC_P through 10 kohm
AIC3204_rset( 0x37, 0x10 );// IN2_R to RADC_P through 10 kohm
AIC3204_rset( 0x36, 0x40 );// CM_1 (common mode) to LADC_M through 10 kohm
AIC3204_rset( 0x39, 0x40 );// CM_1 (common mode) to RADC_M through 10 kohm
AIC3204_rset( 0x3b, 0 ); // MIC_PGA_L unmute
AIC3204_rset( 0x3c, 0 ); // MIC_PGA_R unmute
AIC3204_rset( 0, 0 ); // Select page 0
AIC3204_rset( 0x51, 0xc0 );// Powerup Left and Right ADC
AIC3204_rset( 0x52, 0 ); // Unmute Left and Right ADC
AIC3204_rset( 0, 0 );
USBSTK5515_wait( 100 ); // Wait
}
void AIC3204_config(Uint8 sampling_freq)
{
/* Configure AIC3204 */
AIC3204_rset( 0, 0 ); // Select page 0
AIC3204_rset( 1, 1 ); // Reset codec
AIC3204_rset( 0, 1 ); // Select page 1
AIC3204_rset( 1, 8 ); // Disable crude AVDD generation from DVDD
AIC3204_rset( 2, 1 ); // Enable Analog Blocks, use LDO power
AIC3204_rset( 0, 0 ); // Select page 0
/* PLL and Clocks config and Power Up */
AIC3204_rset( 27, 0x0d ); // BCLK and WCLK is set as o/p to AIC3204(Master)
AIC3204_rset( 28, 0x00 ); // Data ofset = 0
AIC3204_rset( 4, 3 ); // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK
AIC3204_rset( 6, 7 ); // PLL setting: J=7
AIC3204_rset( 7, 0x06 ); // PLL setting: HI_BYTE(D=1680)
AIC3204_rset( 8, 0x90 ); // PLL setting: LO_BYTE(D=1680)
AIC3204_rset( 30, 0x88 ); // For 32 bit clocks per frame in Master mode ONLY
// BCLK=DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs
AIC3204_rset( 5, sampling_freq); // PLL setting: Power up PLL, P=1 and R=1
AIC3204_rset( 13, 0 ); // Hi_Byte(DOSR) for DOSR = 128 decimal or 0x0080 DAC oversamppling
AIC3204_rset( 14, 0x80 ); // Lo_Byte(DOSR) for DOSR = 128 decimal or 0x0080
AIC3204_rset( 20, 0x80 ); // AOSR for AOSR = 128 decimal or 0x0080 for decimation filters 1 to 6
AIC3204_rset( 11, 0x82 ); // Power up NDAC and set NDAC value to 2
AIC3204_rset( 12, 0x87 ); // Power up MDAC and set MDAC value to 7
AIC3204_rset( 18, 0x87 ); // Power up NADC and set NADC value to 7
AIC3204_rset( 19, 0x82 ); // Power up MADC and set MADC value to 2
/* DAC ROUTING and Power Up */
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 12, 0x08 ); // LDAC AFIR routed to HPL
AIC3204_rset( 13, 0x08 ); // RDAC AFIR routed to HPR
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 64, 0x02 ); // Left vol=right vol
AIC3204_rset( 65, 0x00 ); // Left DAC gain to 0dB VOL; Right tracks Left
AIC3204_rset( 63, 0xd4 ); // Power up left,right data paths and set channel
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 16, 0x00 ); // Unmute HPL , 0dB gain
AIC3204_rset( 17, 0x00 ); // Unmute HPR , 0dB gain
AIC3204_rset( 9, 0x30 ); // Power up HPL,HPR
AIC3204_rset( 0, 0x00 ); // Select page 0
USBSTK5515_wait( 500 ); // Wait
/* ADC ROUTING and Power Up */
AIC3204_rset( 0, 1 ); // Select page 1
AIC3204_rset( 0x34, 0x30 ); // STEREO 1 Jack
// IN2_L to LADC_P through 40 kohm
AIC3204_rset( 0x37, 0x30 ); // IN2_R to RADC_P through 40 kohmm
AIC3204_rset( 0x36, 3 ); // CM_1 (common mode) to LADC_M through 40 kohm
AIC3204_rset( 0x39, 0xc0 ); // CM_1 (common mode) to RADC_M through 40 kohm
AIC3204_rset( 0x3b, 0 ); // MIC_PGA_L unmute
AIC3204_rset( 0x3c, 0 ); // MIC_PGA_R unmute
AIC3204_rset( 0, 0 ); // Select page 0
AIC3204_rset( 0x51, 0xc0 ); // Powerup Left and Right ADC
AIC3204_rset( 0x52, 0 ); // Unmute Left and Right ADC
AIC3204_rset( 0, 0 );
USBSTK5515_wait( 200 ); // Wait
/* I2S settings */
I2S0_SRGR = 0x0;
I2S0_CR = 0x8010; // 16-bit word, slave, enable I2C
I2S0_ICMR = 0x3f; // Enable interrupts
}
/* ------------------------------------------------------------------------ *
* *
* AIC3204 Loop *
* Output input from STEREO IN 1 through the HEADPHONE jack *
* *
* ------------------------------------------------------------------------ */
Int16 aic3204_loop_stereo_in1( )
{
/* Pre-generated sine wave data, 16-bit signed samples */
Int16 j, i = 0;
Int16 sample, data1, data2, data3, data4;
/* ------------------------------------------------------------------------ *
* *
* Configure AIC3204 *
* CODEC_CLKIN = PLL CLK *
* CODEC_CLKIN = NADC * MADC * AOSR * ADCFS *
* PLL_CLK = PLL_CLKIN * R * J.D / P *
* PLL_CLKIN = BCLK = 1.536MHz *
* ADCFS = 48KHz *
* *
* ------------------------------------------------------------------------ */
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 1, 0x01 ); // Reset codec
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 1, 0x08 ); // Disable crude AVDD generation from DVDD
AIC3204_rset( 2, 0x00 ); // Enable Analog Blocks
// PLL and Clocks config and Power Up
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 27, 0x00 ); // BCLK and WCLK is set as i/p to AIC3204(Slave)
AIC3204_rset( 4, 0x07 ); // PLL setting: PLLCLK <- BCLK and CODEC_CLKIN <-PLL CLK
AIC3204_rset( 6, 0x20 ); // PLL setting: J = 32
AIC3204_rset( 7, 0 ); // PLL setting: HI_BYTE(D)
AIC3204_rset( 8, 0 ); // PLL setting: LO_BYTE(D)
// For 48 KHz sampling
AIC3204_rset( 5, 0x92 ); // PLL setting: Power up PLL, P=1 and R=2
AIC3204_rset( 13, 0x00 ); // Hi_Byte(DOSR) for DOSR = 128 decimal or 0x0080 DAC oversamppling
AIC3204_rset( 14, 0x80 ); // Lo_Byte(DOSR) for DOSR = 128 decimal or 0x0080
AIC3204_rset( 20, 0x80 ); // AOSR for AOSR = 128 decimal or 0x0080 for decimation filters 1 to 6
AIC3204_rset( 11, 0x84 ); // Power up NDAC and set NDAC value to 4
AIC3204_rset( 12, 0x82 ); // Power up MDAC and set MDAC value to 2
AIC3204_rset( 18, 0x84 ); // Power up NADC and set NADC value to 4
AIC3204_rset( 19, 0x82 ); // Power up MADC and set MADC value to 2
// DAC ROUTING and Power Up
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 12, 0x08 ); // LDAC AFIR routed to HPL
AIC3204_rset( 13, 0x08 ); // RDAC AFIR routed to HPR
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 64, 0x02 ); // Left vol=right vol
AIC3204_rset( 65, 0x00 ); // Left DAC gain to 0dB VOL; Right tracks Left
AIC3204_rset( 63, 0xd4 ); // Power up left,right data paths and set channel
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 16, 0x00 ); // Unmute HPL , 0dB gain
AIC3204_rset( 17, 0x00 ); // Unmute HPR , 0dB gain
AIC3204_rset( 9, 0x30 ); // Power up HPL,HPR
AIC3204_rset( 0, 0x00 ); // Select page 0
EVM5515_wait( 500 ); // Wait
// ADC ROUTING and Power Up
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 52, 0x30 ); // STEREO 1 Jack
// IN2_L to LADC_P through 40 kohm
AIC3204_rset( 55, 0x30 ); // IN2_R to RADC_P through 40 kohmm
AIC3204_rset( 54, 0x03 ); // CM_1 (common mode) to LADC_M through 40 kohm
AIC3204_rset( 57, 0xC0 ); // CM_1 (common mode) to RADC_M through 40 kohm
AIC3204_rset( 59, 0x0f ); // MIC_PGA_L unmute
AIC3204_rset( 60, 0x0f ); // MIC_PGA_R unmute
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 81, 0xc0 ); // Powerup Left and Right ADC
AIC3204_rset( 82, 0x00 ); // Unmute Left and Right ADC
AIC3204_rset( 0, 0x00 );
EVM5515_wait( 200 ); // Wait
/* I2S settings */
I2S2_SRGR = 0x0015;
I2S2_ICMR = 0x0028; // Enable interrupts
I2S2_CR = 0x8012; // 16-bit word, Master, enable I2C
/* Play Tone */
for ( i = 0 ; i < 5 ; i++ )
{
for ( j = 0 ; j < 1000 ; j++ )
{
for ( sample = 0 ; sample < 48 ; sample++ )
{
/* Read Digital audio */
while((Rcv & I2S2_IR) == 0); // Wait for receive interrupt to be pending
data3 = I2S2_W0_MSW_R; // 16 bit left channel received audio data
data4 = I2S2_W1_MSW_R; // 16 bit right channel received audio data
/* Write Digital audio */
while((Xmit & I2S2_IR) == 0); // Wait for receive interrupt to be pending
I2S2_W0_MSW_W = data3; // 16 bit left channel transmit audio data
I2S2_W1_MSW_W = data4; // 16 bit right channel transmit audio data
}
}
}
/* Disble I2S */
I2S0_CR = 0x00;
return 0;
}
void aic3204_disable(void)
{
AIC3204_rset( 1, 1 ); // Reset codec
// USBSTK5505_GPIO_setOutput( GPIO26, 0 ); // Put AIC3204 into reset
I2S2_CR = 0x00;
}
/* ------------------------------------------------------------------------ *
* *
* AIC3204 Loop *
* Output input from STEREO IN 1 through the HEADPHONE jack *
* *
* ------------------------------------------------------------------------ */
Int16 aic3204_loop_stereo_in1( )
{
/* Pre-generated sine wave data, 16-bit signed samples */
Int16 sample, data1, data2, data4, i, data3, data3o, acc;
/* Configure AIC3204 */
AIC3204_rset( 0, 0 ); // Select page 0
AIC3204_rset( 1, 1 ); // Reset codec
AIC3204_rset( 0, 1 ); // Select page 1
AIC3204_rset( 1, 8 ); // Disable crude AVDD generation from DVDD
AIC3204_rset( 2, 1 ); // Enable Analog Blocks, use LDO power
AIC3204_rset( 0, 0 ); // Select page 0
/* PLL and Clocks config and Power Up */
AIC3204_rset( 27, 0x0d ); // BCLK and WCLK is set as o/p to AIC3204(Master)
AIC3204_rset( 28, 0x00 ); // Data ofset = 0
AIC3204_rset( 4, 3 ); // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK
AIC3204_rset( 6, 7 ); // PLL setting: J=7
AIC3204_rset( 7, 0x06 ); // PLL setting: HI_BYTE(D=1680)
AIC3204_rset( 8, 0x90 ); // PLL setting: LO_BYTE(D=1680)
AIC3204_rset( 30, 0x88 ); // For 32 bit clocks per frame in Master mode ONLY
// BCLK=DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs
AIC3204_rset( 5, 0x91 ); // PLL setting: Power up PLL, P=1 and R=1
AIC3204_rset( 13, 0 ); // Hi_Byte(DOSR) for DOSR = 128 decimal or 0x0080 DAC oversamppling
AIC3204_rset( 14, 0x80 ); // Lo_Byte(DOSR) for DOSR = 128 decimal or 0x0080
AIC3204_rset( 20, 0x80 ); // AOSR for AOSR = 128 decimal or 0x0080 for decimation filters 1 to 6
AIC3204_rset( 11, 0x82 ); // Power up NDAC and set NDAC value to 2
AIC3204_rset( 12, 0x87 ); // Power up MDAC and set MDAC value to 7
AIC3204_rset( 18, 0x87 ); // Power up NADC and set NADC value to 7
AIC3204_rset( 19, 0x82 ); // Power up MADC and set MADC value to 2
/* DAC ROUTING and Power Up */
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 12, 0x08 ); // LDAC AFIR routed to HPL
AIC3204_rset( 13, 0x08 ); // RDAC AFIR routed to HPR
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 64, 0x02 ); // Left vol=right vol
AIC3204_rset( 65, 0x00 ); // Left DAC gain to 0dB VOL; Right tracks Left
AIC3204_rset( 63, 0xd4 ); // Power up left,right data paths and set channel
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 16, 0x00 ); // Unmute HPL , 0dB gain
AIC3204_rset( 17, 0x00 ); // Unmute HPR , 0dB gain
AIC3204_rset( 9, 0x30 ); // Power up HPL,HPR
AIC3204_rset( 0, 0x00 ); // Select page 0
USBSTK5515_wait( 500 ); // Wait
/* ADC ROUTING and Power Up */
AIC3204_rset( 0, 1 ); // Select page 1
AIC3204_rset( 0x34, 0x30 ); // STEREO 1 Jack
// IN2_L to LADC_P through 40 kohm
AIC3204_rset( 0x37, 0x30 ); // IN2_R to RADC_P through 40 kohmm
AIC3204_rset( 0x36, 3 ); // CM_1 (common mode) to LADC_M through 40 kohm
AIC3204_rset( 0x39, 0xc0 ); // CM_1 (common mode) to RADC_M through 40 kohm
AIC3204_rset( 0x3b, 0 ); // MIC_PGA_L unmute
AIC3204_rset( 0x3c, 0 ); // MIC_PGA_R unmute
AIC3204_rset( 0, 0 ); // Select page 0
AIC3204_rset( 0x51, 0xc0 ); // Powerup Left and Right ADC
AIC3204_rset( 0x52, 0 ); // Unmute Left and Right ADC
AIC3204_rset( 0, 0 );
USBSTK5515_wait( 200 ); // Wait
/* I2S settings */
I2S0_SRGR = 0x0;
I2S0_CR = 0x8010; // 16-bit word, slave, enable I2C
I2S0_ICMR = 0x3f; // Enable interrupts
/* Take it boy */
while ( 1 )
{
for ( sample = 0 ; sample < 48 ; sample++ )
{
/* Read Digital audio */
while((Rcv & I2S0_IR) == 0);// Wait for interrupt pending flag
data3 = I2S0_W0_MSW_R; // 16 bit left channel received audio data
data1 = I2S0_W0_LSW_R;
data4 = I2S0_W1_MSW_R; // 16 bit right channel received audio data
data2 = I2S0_W1_LSW_R;
// void SampleFilter_init(SampleFilter* f);
// void SampleFilter_put(SampleFilter* f, Int16 data3);
// Int16 SampleFilter_get(SampleFilter* f);
while((Xmit & I2S0_IR) == 0);// Wait for interrupt pending flag
I2S0_W0_MSW_W = data3; // 16 bit left channel transmit audio data
I2S0_W0_LSW_W = 0;
I2S0_W1_MSW_W = data4; // 16 bit right channel transmit audio data
I2S0_W1_LSW_W = 0;
}
}
/* Disble I2S */
//I2S0_CR = 0x00;
return 0;
}
/* ------------------------------------------------------------------------ *
* *
* AIC3204 Tone *
* Output a 1 kHz tone through the STEREO OUT jack *
* *
* ------------------------------------------------------------------------ */
Int16 aic3204_tone_stereo_out( )
{
/* Pre-generated sine wave data, 16-bit signed samples */
Int16 sinetable[48] = {
0x0000, 0x10b4, 0x2120, 0x30fb, 0x3fff, 0x4dea, 0x5a81, 0x658b,
0x6ed8, 0x763f, 0x7ba1, 0x7ee5, 0x7ffd, 0x7ee5, 0x7ba1, 0x76ef,
0x6ed8, 0x658b, 0x5a81, 0x4dea, 0x3fff, 0x30fb, 0x2120, 0x10b4,
0x0000, 0xef4c, 0xdee0, 0xcf06, 0xc002, 0xb216, 0xa57f, 0x9a75,
0x9128, 0x89c1, 0x845f, 0x811b, 0x8002, 0x811b, 0x845f, 0x89c1,
0x9128, 0x9a76, 0xa57f, 0xb216, 0xc002, 0xcf06, 0xdee0, 0xef4c
};
Int16 j, i = 0;
Int16 sample;
/* ------------------------------------------------------------------------ *
* *
* Configure AIC3204 *
* CODEC_CLKIN = PLL CLK *
* CODEC_CLKIN = NADC * MADC * AOSR * ADCFS *
* PLL_CLK = PLL_CLKIN * R * J.D / P *
* PLL_CLKIN = BCLK = 1.536MHz *
* ADCFS = 48KHz *
* *
* ------------------------------------------------------------------------ */
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 1, 0x01 ); // Reset codec
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 1, 0x08 ); // Disable crude AVDD generation from DVDD
AIC3204_rset( 2, 0x00 ); // Enable Analog Blocks
// PLL and Clocks config and Power Up
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 27, 0x00 ); // BCLK and WCLK is set as i/p to AIC3204(Slave)
AIC3204_rset( 4, 0x07 ); // PLL setting: PLLCLK <- BCLK and CODEC_CLKIN <-PLL CLK
AIC3204_rset( 6, 0x20 ); // PLL setting: J = 32
AIC3204_rset( 7, 0 ); // PLL setting: HI_BYTE(D)
AIC3204_rset( 8, 0 ); // PLL setting: LO_BYTE(D)
// For 48 KHz sampling
AIC3204_rset( 5, 0x92 ); // PLL setting: Power up PLL, P=1 and R=2
AIC3204_rset( 13, 0x00 ); // Hi_Byte(DOSR) for DOSR = 128 decimal or 0x0080 DAC oversamppling
AIC3204_rset( 14, 0x80 ); // Lo_Byte(DOSR) for DOSR = 128 decimal or 0x0080
AIC3204_rset( 20, 0x80 ); // AOSR for AOSR = 128 decimal or 0x0080 for decimation filters 1 to 6
AIC3204_rset( 11, 0x84 ); // Power up NDAC and set NDAC value to 4
AIC3204_rset( 12, 0x82 ); // Power up MDAC and set MDAC value to 2
AIC3204_rset( 18, 0x84 ); // Power up NADC and set NADC value to 4
AIC3204_rset( 19, 0x82 ); // Power up MADC and set MADC value to 2
// DAC ROUTING and Power Up
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 14, 0x08 ); // LDAC AFIR routed to LOL
AIC3204_rset( 15, 0x08 ); // RDAC AFIR routed to LOR
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 64, 0x02 ); // Left vol=right vol
AIC3204_rset( 65, 0x00 ); // Left DAC gain to 0dB VOL; Right tracks Left
AIC3204_rset( 63, 0xd4 ); // Power up left,right data paths and set channel
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 18, 0x00 ); // Unmute LOL , 0dB gain
AIC3204_rset( 19, 0x00 ); // Unmute LOR , 0dB gain
AIC3204_rset( 9, 0x0C ); // Power up LOL,LOR
AIC3204_rset( 0, 0x00 ); // Select page 0
EVM5515_wait( 500 ); // Wait
// ADC ROUTING and Power Up
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 52, 0x0C ); // STEREO 1 Jack
// IN2_L to LADC_P through 40 kohm
AIC3204_rset( 55, 0x0C ); // IN2_R to RADC_P through 40 kohmm
AIC3204_rset( 54, 0x03 ); // CM_1 (common mode) to LADC_M through 40 kohm
AIC3204_rset( 57, 0xC0 ); // CM_1 (common mode) to RADC_M through 40 kohm
AIC3204_rset( 59, 0x00 ); // MIC_PGA_L unmute
AIC3204_rset( 60, 0x00 ); // MIC_PGA_R unmute
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 81, 0xc0 ); // Powerup Left and Right ADC
AIC3204_rset( 82, 0x00 ); // Unmute Left and Right ADC
AIC3204_rset( 0, 0x00 );
EVM5515_wait( 200 ); // Wait
/* I2S settings */
I2S2_SRGR = 0x0015;
I2S2_ICMR = 0x0028; // Enable interrupts
I2S2_CR = 0x8012; // 16-bit word, Master, enable I2C
/* Play Tone */
for ( i = 0 ; i < 5 ; i++ )
{
for ( j = 0 ; j < 1000 ; j++ )
{
for ( sample = 0 ; sample < 48 ; sample++ )
{
I2S2_W0_MSW_W = (sinetable[sample]) ;
I2S2_W0_LSW_W = 0;
I2S2_W1_MSW_W = (sinetable[sample]) ;
I2S2_W1_LSW_W = 0;
while((Xmit & I2S2_IR) == 0); // Wait for interrupt
}
}
}
/* Disble I2S */
I2S0_CR = 0x00;
return 0;
}
