int
iavc_b1dma_detect(iavc_softc_t *sc)
{
AMCC_WRITE(sc, AMCC_MCSR, 0);
DELAY(10*1000);
AMCC_WRITE(sc, AMCC_MCSR, 0x0f000000);
DELAY(10*1000);
AMCC_WRITE(sc, AMCC_MCSR, 0);
DELAY(42*1000);
AMCC_WRITE(sc, AMCC_RXLEN, 0);
AMCC_WRITE(sc, AMCC_TXLEN, 0);
sc->sc_csr = 0;
AMCC_WRITE(sc, AMCC_INTCSR, sc->sc_csr);
if (AMCC_READ(sc, AMCC_INTCSR) != 0)
return 1;
AMCC_WRITE(sc, AMCC_RXPTR, 0xffffffff);
AMCC_WRITE(sc, AMCC_TXPTR, 0xffffffff);
if ((AMCC_READ(sc, AMCC_RXPTR) != 0xfffffffc) ||
(AMCC_READ(sc, AMCC_TXPTR) != 0xfffffffc))
return 2;
AMCC_WRITE(sc, AMCC_RXPTR, 0);
AMCC_WRITE(sc, AMCC_TXPTR, 0);
if ((AMCC_READ(sc, AMCC_RXPTR) != 0) ||
(AMCC_READ(sc, AMCC_TXPTR) != 0))
return 3;
iavc_write_port(sc, 0x10, 0x00);
iavc_write_port(sc, 0x07, 0x00);
iavc_write_port(sc, 0x02, 0x02);
iavc_write_port(sc, 0x03, 0x02);
if (((iavc_read_port(sc, 0x02) & 0xfe) != 0x02) ||
(iavc_read_port(sc, 0x03) != 0x03))
return 4;
iavc_write_port(sc, 0x02, 0x00);
iavc_write_port(sc, 0x03, 0x00);
if (((iavc_read_port(sc, 0x02) & 0xfe) != 0x00) ||
(iavc_read_port(sc, 0x03) != 0x01))
return 5;
return (0); /* found */
}
int iavc_handle_intr(iavc_softc_t *sc)
{
u_int32_t status;
u_int32_t newcsr;
if (!sc->sc_dma) {
while (iavc_rx_full(sc))
iavc_handle_rx(sc);
return 0;
}
status = AMCC_READ(sc, AMCC_INTCSR);
if ((status & ANY_S5933_INT) == 0)
return 0;
newcsr = sc->sc_csr | (status & ALL_INT);
if (status & TX_TC_INT) newcsr &= ~EN_TX_TC_INT;
if (status & RX_TC_INT) newcsr &= ~EN_RX_TC_INT;
AMCC_WRITE(sc, AMCC_INTCSR, newcsr);
sc->sc_intr = 1;
if (status & RX_TC_INT) {
u_int32_t rxlen;
bus_dmamap_sync(sc->dmat, sc->rx_map, 0, sc->rx_map->dm_mapsize,
BUS_DMASYNC_POSTREAD);
if (sc->sc_recv1 == 0) {
sc->sc_recv1 = *(u_int32_t*)(sc->sc_recvbuf);
rxlen = (sc->sc_recv1 + 3) & ~3;
AMCC_WRITE(sc, AMCC_RXPTR, sc->rx_map->dm_segs[0].ds_addr);
AMCC_WRITE(sc, AMCC_RXLEN, rxlen ? rxlen : 4);
} else {
iavc_handle_rx(sc);
sc->sc_recv1 = 0;
AMCC_WRITE(sc, AMCC_RXPTR, sc->rx_map->dm_segs[0].ds_addr);
AMCC_WRITE(sc, AMCC_RXLEN, 4);
}
}
if (status & TX_TC_INT) {
bus_dmamap_sync(sc->dmat, sc->tx_map, 0, sc->tx_map->dm_mapsize,
BUS_DMASYNC_POSTWRITE);
sc->sc_csr &= ~EN_TX_TC_INT;
iavc_start_tx(sc);
}
AMCC_WRITE(sc, AMCC_INTCSR, sc->sc_csr);
sc->sc_intr = 0;
return 0;
}
void iavc_handle_intr(iavc_softc_t *sc)
{
u_int32_t status;
u_int32_t newcsr;
if (!sc->sc_dma) {
while (iavc_rx_full(sc))
iavc_handle_rx(sc);
return;
}
status = AMCC_READ(sc, AMCC_INTCSR);
if ((status & ANY_S5933_INT) == 0)
return;
newcsr = sc->sc_csr | (status & ALL_INT);
if (status & TX_TC_INT) newcsr &= ~EN_TX_TC_INT;
if (status & RX_TC_INT) newcsr &= ~EN_RX_TC_INT;
AMCC_WRITE(sc, AMCC_INTCSR, newcsr);
sc->sc_intr = TRUE;
if (status & RX_TC_INT) {
u_int32_t rxlen;
if (sc->sc_recvlen == 0) {
sc->sc_recvlen = *((u_int32_t*)(&sc->sc_recvbuf[0]));
rxlen = (sc->sc_recvlen + 3) & ~3;
AMCC_WRITE(sc, AMCC_RXPTR, vtophys(&sc->sc_recvbuf[4]));
AMCC_WRITE(sc, AMCC_RXLEN, rxlen);
} else {
iavc_handle_rx(sc);
sc->sc_recvlen = 0;
AMCC_WRITE(sc, AMCC_RXPTR, vtophys(&sc->sc_recvbuf[0]));
AMCC_WRITE(sc, AMCC_RXLEN, 4);
}
}
if (status & TX_TC_INT) {
sc->sc_csr &= ~EN_TX_TC_INT;
iavc_start_tx(sc);
}
AMCC_WRITE(sc, AMCC_INTCSR, sc->sc_csr);
sc->sc_intr = FALSE;
}
