void ADC_SetScale(bool scale)
{
if(ADC_SCALE_1V2 == scale) {
ANA_REG_AND(ADC_CS, ~ADC_SCALE_BIT);
} else if(ADC_SCALE_3V == scale) {
ANA_REG_OR(ADC_CS, ADC_SCALE_BIT);
} else
pr_err("adc scale %d not support\n", scale);
}
PUBLIC void CHIP_PHY_ResetHWFlag (uint32 val)
{
// Reset the analog die register
ANA_REG_AND (ANA_HWRST_STATUS, ~0xFFF);
ANA_REG_OR (ANA_HWRST_STATUS, (val&0xFFF));
// Reset the HW_RST
CHIP_REG_AND (CHIP_PHY_GetHwRstAddr (), ~0xFFFF);
CHIP_REG_OR (CHIP_PHY_GetHwRstAddr (), (val&0xFFFF));
}
void ADC_Init(void)
{
uint32_t i;
ANA_REG_OR(ANA_APB_ARM_RST, ADC_RST_BIT);
for(i = 0; i < 0xff; i++);
ANA_REG_AND(ANA_APB_ARM_RST, ~ADC_RST_BIT);
ANA_REG_OR(ANA_APB_CLK_EN, ADC_EB | CLK_AUXAD_EN | CLK_AUXADC_EN);
ANA_REG_OR(ADC_CTRL, ADC_EN_BIT);
ANA_REG_OR(ADC_CTRL, ADC_MODE_12B);
}
int sprd_clean_rtc(void)
{
int err;
ANA_REG_AND(ANA_RTC_INT_EN, ~(RTC_INT_ALL_MSK)); // disable all interrupt
ANA_REG_OR(ANA_APB_CLK_EN, AGEN_RTC_EN | AGEN_RTC_RTC_EN); //enable rtc device
CLEAR_RTC_INT(RTC_INT_ALL_MSK);
sprd_rtc_set_sec(0);
sprd_rtc_set_alarm_sec(0);
printf("now time sec %lu\n", sprd_rtc_get_sec());
printf("now alarm sec %lu\n", sprd_rtc_get_alarm_sec());
return 0;
}
int32_t ADC_GetValues(adc_channel id, bool scale, uint8_t num, int32_t *p_buf)
{
int32_t count;
uint8_t i;
/* clear int */
ANA_REG_OR(ADC_INT_CLR, ADC_IRQ_CLR_BIT);
/* choose channel */
ADC_SetCs(id);
/* set ADC scale */
ADC_SetScale(scale);
/* set read numbers run ADC soft channel */
if (num < 1) {
return -1;
}
ANA_REG_MSK_OR(ADC_CTRL, BIT_SW_CH_RUN_NUM(num), SW_CH_NUM_MSK);
ANA_REG_OR(ADC_CTRL, SW_CH_ON_BIT);
/* wait adc complete */
count = 1000;
while(!(ANA_REG_GET(ADC_INT_SRC)&ADC_IRQ_RAW_BIT) && count--) {
for (i = 0; i < 0xFF; i++);
}
if (count <= 0) {
pr_warning("WARNING: ADC_GetValue timeout....\n");
return -1;
}
for (i = 0; i < num; i++) {
p_buf[i] = ANA_REG_GET(ADC_DAT) & ADC_DATA_MSK;
}
ANA_REG_AND(ADC_CTRL, ~SW_CH_ON_BIT); // turn off adc soft channel
return 0;
}
void init_ldo_sleep_gr(void)
{
ANA_REG_OR(ANA_REG_GLB_LDO_DCDC_PD_RTCSET, (BIT_LDO_RF1_PD_RTCSET | BIT_DCDC_WRF_PD_RTCSET));
ANA_REG_AND(ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, (~(BIT_LDO_RF1_PD_RTCSET | BIT_DCDC_WRF_PD_RTCSET)));
ANA_REG_OR(ANA_REG_GLB_LDO_PD_CTRL, (BIT_DCDC_WPA_PD));
/**********************************************
* Following is AP LDO A DIE Sleep Control *
*********************************************/
ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL0,
BIT_SLP_IO_EN |
BIT_SLP_DCDC_OTP_PD_EN |
//BIT_SLP_DCDCGEN_PD_EN |
//BIT_SLP_DCDCWPA_PD_EN |
//BIT_SLP_DCDCWRF_PD_EN |
BIT_SLP_DCDCARM_PD_EN |
BIT_SLP_LDOEMMCCORE_PD_EN |
BIT_SLP_LDOEMMCIO_PD_EN |
BIT_SLP_LDORF2_PD_EN |
//BIT_SLP_LDORF1_PD_EN |
BIT_SLP_LDORF0_PD_EN |
BIT_SLP_LDOVDD25_PD_EN |
//BIT_SLP_LDOVDD28_PD_EN |
//BIT_SLP_LDOVDD18_PD_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL1,
BIT_SLP_LDO_PD_EN |
BIT_SLP_LDOLPREF_PD_EN |
BIT_SLP_LDOCLSG_PD_EN |
BIT_SLP_LDOUSB_PD_EN |
BIT_SLP_LDOCAMMOT_PD_EN |
BIT_SLP_LDOCAMIO_PD_EN |
BIT_SLP_LDOCAMD_PD_EN |
BIT_SLP_LDOCAMA_PD_EN |
BIT_SLP_LDOSIM2_PD_EN |
//BIT_SLP_LDOSIM1_PD_EN |
//BIT_SLP_LDOSIM0_PD_EN |
BIT_SLP_LDOSD_PD_EN |
BIT_SLP_LDOAVDD18_PD_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL2,
//BIT_SLP_DCDC_BG_LP_EN |
//BIT_SLP_DCDCCORE_LP_EN |
//BIT_SLP_DCDCMEM_LP_EN |
//BIT_SLP_DCDCARM_LP_EN |
//BIT_SLP_DCDCGEN_LP_EN |
//BIT_SLP_DCDCWPA_LP_EN |
//BIT_SLP_DCDCWRF_LP_EN |
//BIT_SLP_LDOEMMCCORE_LP_EN |
//BIT_SLP_LDOEMMCIO_LP_EN |
//BIT_SLP_LDORF2_LP_EN |
//BIT_SLP_LDORF1_LP_EN |
//BIT_SLP_LDORF0_LP_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL3,
//BIT_SLP_BG_LP_EN |
//BIT_SLP_LDOVDD25_LP_EN |
//BIT_SLP_LDOVDD28_LP_EN |
//BIT_SLP_LDOVDD18_LP_EN |
//BIT_SLP_LDOCLSG_LP_EN |
//BIT_SLP_LDOUSB_LP_EN |
//BIT_SLP_LDOCAMMOT_LP_EN |
//BIT_SLP_LDOCAMIO_LP_EN |
//BIT_SLP_LDOCAMD_LP_EN |
//BIT_SLP_LDOCAMA_LP_EN |
//BIT_SLP_LDOSIM2_LP_EN |
//BIT_SLP_LDOSIM1_LP_EN |
//BIT_SLP_LDOSIM0_LP_EN |
//BIT_SLP_LDOSD_LP_EN |
//BIT_SLP_LDOAVDD18_LP_EN |
0
);
/****************************************
* Following is CP LDO Sleep Control *
****************************************/
ANA_REG_SET(ANA_REG_GLB_LDO1828_XTL_CTL,
//BIT_LDO_VDD18_EXT_XTL2_EN |
//BIT_LDO_VDD18_EXT_XTL1_EN |
//BIT_LDO_VDD18_EXT_XTL0_EN |
//BIT_LDO_VDD18_XTL2_EN |
//BIT_LDO_VDD18_XTL1_EN |
//BIT_LDO_VDD18_XTL0_EN |
//BIT_LDO_VDD28_EXT_XTL2_EN |
//BIT_LDO_VDD28_EXT_XTL1_EN |
//BIT_LDO_VDD28_EXT_XTL0_EN |
//BIT_LDO_VDD28_XTL2_EN |
//BIT_LDO_VDD28_XTL1_EN |
//BIT_LDO_VDD28_XTL0_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
BIT_LDO_XTL_EN |
//BIT_LDO_RF1_EXT_XTL2_EN |
//BIT_LDO_RF1_EXT_XTL1_EN |
//BIT_LDO_RF1_EXT_XTL0_EN |
//BIT_LDO_RF1_XTL2_EN |
//BIT_LDO_RF1_XTL1_EN |
//BIT_LDO_RF1_XTL0_EN |
//BIT_LDO_RF0_EXT_XTL2_EN |
//BIT_LDO_RF0_EXT_XTL1_EN |
//BIT_LDO_RF0_EXT_XTL0_EN |
BIT_LDO_RF0_XTL2_EN |
BIT_LDO_RF0_XTL1_EN |
BIT_LDO_RF0_XTL0_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
//BIT_LDO_VDD25_EXT_XTL2_EN |
//BIT_LDO_VDD25_EXT_XTL1_EN |
//BIT_LDO_VDD25_EXT_XTL0_EN |
BIT_LDO_VDD25_XTL2_EN |
BIT_LDO_VDD25_XTL1_EN |
BIT_LDO_VDD25_XTL0_EN |
//BIT_LDO_RF2_EXT_XTL2_EN |
//BIT_LDO_RF2_EXT_XTL1_EN |
//BIT_LDO_RF2_EXT_XTL0_EN |
BIT_LDO_RF2_XTL2_EN |
BIT_LDO_RF2_XTL1_EN |
BIT_LDO_RF2_XTL0_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
//BIT_LDO_AVDD18_EXT_XTL2_EN |
//BIT_LDO_AVDD18_EXT_XTL1_EN |
//BIT_LDO_AVDD18_EXT_XTL0_EN |
//BIT_LDO_AVDD18_XTL2_EN |
//BIT_LDO_AVDD18_XTL1_EN |
//BIT_LDO_AVDD18_XTL0_EN |
//BIT_LDO_SIM2_EXT_XTL2_EN |
//BIT_LDO_SIM2_EXT_XTL1_EN |
//BIT_LDO_SIM2_EXT_XTL0_EN |
//BIT_LDO_SIM2_XTL2_EN |
//BIT_LDO_SIM2_XTL1_EN |
//BIT_LDO_SIM2_XTL0_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
//BIT_DCDC_BG_EXT_XTL2_EN |
//BIT_DCDC_BG_EXT_XTL1_EN |
//BIT_DCDC_BG_EXT_XTL0_EN |
BIT_DCDC_BG_XTL2_EN |
BIT_DCDC_BG_XTL1_EN |
BIT_DCDC_BG_XTL0_EN |
//BIT_BG_EXT_XTL2_EN |
//BIT_BG_EXT_XTL1_EN |
//BIT_BG_EXT_XTL0_EN |
//BIT_BG_XTL2_EN |
//BIT_BG_XTL1_EN |
//BIT_BG_XTL0_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN4,
//BIT_DCDC_WRF_XTL2_EN |
//BIT_DCDC_WRF_XTL1_EN |
//BIT_DCDC_WRF_XTL0_EN |
//BIT_DCDC_WPA_XTL2_EN |
//BIT_DCDC_WPA_XTL1_EN |
//BIT_DCDC_WPA_XTL0_EN |
BIT_DCDC_MEM_XTL2_EN |
BIT_DCDC_MEM_XTL1_EN |
BIT_DCDC_MEM_XTL0_EN |
BIT_DCDC_GEN_XTL2_EN |
BIT_DCDC_GEN_XTL1_EN |
BIT_DCDC_GEN_XTL0_EN |
BIT_DCDC_CORE_XTL2_EN |
BIT_DCDC_CORE_XTL1_EN |
BIT_DCDC_CORE_XTL0_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN5,
//BIT_DCDC_WRF_EXT_XTL2_EN |
//BIT_DCDC_WRF_EXT_XTL1_EN |
//BIT_DCDC_WRF_EXT_XTL0_EN |
//BIT_DCDC_WPA_EXT_XTL2_EN |
//BIT_DCDC_WPA_EXT_XTL1_EN |
//BIT_DCDC_WPA_EXT_XTL0_EN |
//BIT_DCDC_MEM_EXT_XTL2_EN |
//BIT_DCDC_MEM_EXT_XTL1_EN |
//BIT_DCDC_MEM_EXT_XTL0_EN |
//BIT_DCDC_GEN_EXT_XTL2_EN |
//BIT_DCDC_GEN_EXT_XTL1_EN |
//BIT_DCDC_GEN_EXT_XTL0_EN |
//BIT_DCDC_CORE_EXT_XTL2_EN |
//BIT_DCDC_CORE_EXT_XTL1_EN |
//BIT_DCDC_CORE_EXT_XTL0_EN |
0
);
/************************************************
* Following is AP/CP LDO D DIE Sleep Control *
*************************************************/
CHIP_REG_SET(REG_PMU_APB_XTL0_REL_CFG,
BIT_XTL0_AP_SEL |
BIT_XTL0_CP0_SEL |
BIT_XTL0_CP1_SEL |
BIT_XTL0_CP2_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_XTL1_REL_CFG,
BIT_XTL1_AP_SEL |
BIT_XTL1_CP0_SEL |
BIT_XTL1_CP1_SEL |
BIT_XTL1_CP2_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_XTL2_REL_CFG,
BIT_XTL2_AP_SEL |
BIT_XTL2_CP0_SEL |
BIT_XTL2_CP1_SEL |
BIT_XTL2_CP2_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_XTLBUF0_REL_CFG,
BIT_XTLBUF0_CP2_SEL |
BIT_XTLBUF0_CP1_SEL |
BIT_XTLBUF0_CP0_SEL |
BIT_XTLBUF0_AP_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_XTLBUF1_REL_CFG,
BIT_XTLBUF1_CP2_SEL |
BIT_XTLBUF1_CP1_SEL |
BIT_XTLBUF1_CP0_SEL |
BIT_XTLBUF1_AP_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_MPLL_REL_CFG,
//BIT_MPLL_REF_SEL |
//BIT_MPLL_CP2_SEL |
//BIT_MPLL_CP1_SEL |
//BIT_MPLL_CP0_SEL |
BIT_MPLL_AP_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_DPLL_REL_CFG,
//BIT_DPLL_REF_SEL |
BIT_DPLL_CP2_SEL |
BIT_DPLL_CP1_SEL |
BIT_DPLL_CP0_SEL |
BIT_DPLL_AP_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_TDPLL_REL_CFG,
//BIT_TDPLL_REF_SEL |
BIT_TDPLL_CP2_SEL |
BIT_TDPLL_CP1_SEL |
BIT_TDPLL_CP0_SEL |
BIT_TDPLL_AP_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_WPLL_REL_CFG,
//BIT_WPLL_REF_SEL |
//BIT_WPLL_CP2_SEL |
//BIT_WPLL_CP1_SEL |
BIT_WPLL_CP0_SEL |
//BIT_WPLL_AP_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_CPLL_REL_CFG,
//BIT_CPLL_REF_SEL |
BIT_CPLL_CP2_SEL |
BIT_CPLL_CP1_SEL |
//BIT_CPLL_CP0_SEL |
//BIT_CPLL_AP_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_CA7_TOP_CFG,
BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN |
BITS_PD_CA7_TOP_PWR_ON_DLY(8) |
BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(2) |
BITS_PD_CA7_TOP_ISO_ON_DLY(4) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_CA7_C0_CFG,
BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN |
BITS_PD_CA7_C0_PWR_ON_DLY(8) |
BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(6) |
BITS_PD_CA7_C0_ISO_ON_DLY(2) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_CA7_C1_CFG,
BIT_PD_CA7_C1_FORCE_SHUTDOWN |
BITS_PD_CA7_C1_PWR_ON_DLY(8) |
BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(4) |
BITS_PD_CA7_C1_ISO_ON_DLY(2) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_CA7_C2_CFG,
BIT_PD_CA7_C2_FORCE_SHUTDOWN |
BITS_PD_CA7_C2_PWR_ON_DLY(8) |
BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(4) |
BITS_PD_CA7_C2_ISO_ON_DLY(2) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_CA7_C3_CFG,
BIT_PD_CA7_C3_FORCE_SHUTDOWN |
BITS_PD_CA7_C3_PWR_ON_DLY(8) |
BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(4) |
BITS_PD_CA7_C3_ISO_ON_DLY(2) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_AP_SYS_CFG,
BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN |
BITS_PD_AP_SYS_PWR_ON_DLY(8) |
BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(0) |
BITS_PD_AP_SYS_ISO_ON_DLY(6) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_MM_TOP_CFG,
BIT_PD_MM_TOP_FORCE_SHUTDOWN |
BITS_PD_MM_TOP_PWR_ON_DLY(8) |
BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(0) |
BITS_PD_MM_TOP_ISO_ON_DLY(4) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_GPU_TOP_CFG,
BIT_PD_GPU_TOP_FORCE_SHUTDOWN |
BITS_PD_GPU_TOP_PWR_ON_DLY(8) |
BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(0) |
BITS_PD_GPU_TOP_ISO_ON_DLY(4) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_PUB_SYS_CFG,
BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN |
BITS_PD_PUB_SYS_PWR_ON_DLY(8) |
BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(0) |
BITS_PD_PUB_SYS_ISO_ON_DLY(6) |
0
);
CHIP_REG_SET(REG_PMU_APB_XTL_WAIT_CNT,
BITS_XTL1_WAIT_CNT(0x39) |
BITS_XTL0_WAIT_CNT(0x39) |
0
);
CHIP_REG_SET(REG_PMU_APB_XTLBUF_WAIT_CNT,
BITS_XTLBUF1_WAIT_CNT(7) |
BITS_XTLBUF0_WAIT_CNT(7) |
0
);
CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT1,
BITS_WPLL_WAIT_CNT(7) |
BITS_TDPLL_WAIT_CNT(7) |
BITS_DPLL_WAIT_CNT(7) |
BITS_MPLL_WAIT_CNT(7) |
0
);
CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT2,
BITS_WIFIPLL2_WAIT_CNT(7) |
BITS_WIFIPLL1_WAIT_CNT(7) |
BITS_CPLL_WAIT_CNT(7) |
0
);
ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM,
BITS_SLP_IN_WAIT_DCDCARM(9) |
BITS_SLP_OUT_WAIT_DCDCARM(8) |
0
);
}
void CHG_TurnOn (void)
{
ANA_REG_AND (ANA_CHGR_CTL0,~CHGR_PD_BIT);
}
