uint32_t
tea_stm (ARMul_State * state, ARMword address, ARMword reg_map)
{
int i;
for (i = 0; i < 16; i++) {
if (reg_map & (1 << i)) {
if (i == 15) {
ARMul_WriteWord (state, address,
state->Reg[i] + 4);
}
else {
ARMul_WriteWord (state, address,
state->Reg[i]);
}
if (state->abortSig != LOW) {
state->trap = TRAP_DATA_ABORT;
//if (state->is_XScale) {
if (!state->abort_model) {
return (0);
}
else {
break;
}
}
address += 4;
}
}
if (state->trap != TRAP_DATA_ABORT) {
address -= 4;
}
return (address);
}
uint32_t
tea_stm_user (ARMul_State * state, ARMword address, ARMword reg_map)
{
int i;
for (i = 0; i < 16; i++) {
if (reg_map & (1 << i)) {
if (i == 15) {
ARMul_WriteWord (state, address,
state->Reg[i] + 4);
}
else {
if (((state->Mode == FIQ26MODE
|| state->Mode == FIQ32MODE)
&& (i >= 8)) || (i >= 13)) {
ARMul_WriteWord (state, address,
state->
RegBank[USERBANK]
[i]);
}
else {
ARMul_WriteWord (state, address,
state->Reg[i]);
}
}
if (state->abortSig != LOW) {
state->trap = TRAP_DATA_ABORT;
//if (state->is_XScale) {
if (!state->abort_model) {
return (0);
}
else {
break;
}
}
address += 4;
}
}
if (state->trap != TRAP_DATA_ABORT) {
address -= 4;
}
return (address);
}
SIM_RC
sim_create_inferior (SIM_DESC sd ATTRIBUTE_UNUSED,
struct bfd * abfd,
char * const *argv,
char * const *env)
{
int argvlen = 0;
int mach;
char **arg;
init ();
if (abfd != NULL)
{
ARMul_SetPC (state, bfd_get_start_address (abfd));
mach = bfd_get_mach (abfd);
}
else
{
ARMul_SetPC (state, 0); /* ??? */
mach = 0;
}
#ifdef MODET
if (abfd != NULL && (bfd_get_start_address (abfd) & 1))
SETT;
#endif
switch (mach)
{
default:
(*sim_callback->printf_filtered)
(sim_callback,
"Unknown machine type '%d'; please update sim_create_inferior.\n",
mach);
/* fall through */
case 0:
/* We wouldn't set the machine type with earlier toolchains, so we
explicitly select a processor capable of supporting all ARMs in
32bit mode. */
ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_v6_Prop);
break;
case bfd_mach_arm_XScale:
ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_v6_Prop);
break;
case bfd_mach_arm_iWMMXt2:
case bfd_mach_arm_iWMMXt:
{
extern int SWI_vector_installed;
ARMword i;
if (! SWI_vector_installed)
{
/* Intialise the hardware vectors to zero. */
if (! SWI_vector_installed)
for (i = ARMul_ResetV; i <= ARMFIQV; i += 4)
ARMul_WriteWord (state, i, 0);
/* ARM_WriteWord will have detected the write to the SWI vector,
but we want SWI_vector_installed to remain at 0 so that thumb
mode breakpoints will work. */
SWI_vector_installed = 0;
}
}
ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_iWMMXt_Prop);
break;
case bfd_mach_arm_ep9312:
ARMul_SelectProcessor (state, ARM_v4_Prop | ARM_ep9312_Prop);
break;
case bfd_mach_arm_5:
if (bfd_family_coff (abfd))
{
/* This is a special case in order to support COFF based ARM toolchains.
The COFF header does not have enough room to store all the different
kinds of ARM cpu, so the XScale, v5T and v5TE architectures all default
to v5. (See coff_set_flags() in bdf/coffcode.h). So if we see a v5
machine type here, we assume it could be any of the above architectures
and so select the most feature-full. */
ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop);
break;
}
/* Otherwise drop through. */
case bfd_mach_arm_5T:
ARMul_SelectProcessor (state, ARM_v5_Prop);
break;
case bfd_mach_arm_5TE:
ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop);
break;
case bfd_mach_arm_4:
case bfd_mach_arm_4T:
ARMul_SelectProcessor (state, ARM_v4_Prop);
break;
case bfd_mach_arm_3:
case bfd_mach_arm_3M:
ARMul_SelectProcessor (state, ARM_Lock_Prop);
break;
case bfd_mach_arm_2:
case bfd_mach_arm_2a:
ARMul_SelectProcessor (state, ARM_Fix26_Prop);
break;
}
memset (& info, 0, sizeof (info));
INIT_DISASSEMBLE_INFO (info, stdout, op_printf);
info.read_memory_func = sim_dis_read;
info.arch = bfd_get_arch (abfd);
info.mach = bfd_get_mach (abfd);
info.endian_code = BFD_ENDIAN_LITTLE;
if (info.mach == 0)
info.arch = bfd_arch_arm;
disassemble_init_for_target (& info);
if (argv != NULL)
{
/* Set up the command line by laboriously stringing together
the environment carefully picked apart by our caller. */
/* Free any old stuff. */
if (state->CommandLine != NULL)
{
free (state->CommandLine);
state->CommandLine = NULL;
}
/* See how much we need. */
for (arg = argv; *arg != NULL; arg++)
argvlen += strlen (*arg) + 1;
/* Allocate it. */
state->CommandLine = malloc (argvlen + 1);
if (state->CommandLine != NULL)
{
arg = argv;
state->CommandLine[0] = '\0';
for (arg = argv; *arg != NULL; arg++)
{
strcat (state->CommandLine, *arg);
strcat (state->CommandLine, " ");
}
}
}
if (env != NULL)
{
/* Now see if there's a MEMSIZE spec in the environment. */
while (*env)
{
if (strncmp (*env, "MEMSIZE=", sizeof ("MEMSIZE=") - 1) == 0)
{
char *end_of_num;
/* Set up memory limit. */
state->MemSize =
strtoul (*env + sizeof ("MEMSIZE=") - 1, &end_of_num, 0);
}
env++;
}
}
return SIM_RC_OK;
}
