Static void ar9287_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c, struct ieee80211_channel *extc) { const struct ar9287_eeprom *eep = sc->sc_eep; const struct ar9287_modal_eep_header *modal = &eep->modalHeader; uint32_t reg, offset; int i; AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon); for (i = 0; i < AR9287_MAX_CHAINS; i++) { offset = i * 0x1000; AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0 + offset, modal->antCtrlChain[i]); reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0 + offset); reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, modal->iqCalICh[i]); reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, modal->iqCalQCh[i]); AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg); reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset); reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, modal->bswMargin[i]); reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB, modal->bswAtten[i]); AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg); reg = AR_READ(sc, AR_PHY_RXGAIN + offset); reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, modal->rxTxMarginCh[i]); reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, modal->txRxAttenCh[i]); AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg); } reg = AR_READ(sc, AR_PHY_SETTLING); #ifndef IEEE80211_NO_HT if (extc != NULL) reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40); else #endif reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling); AR_WRITE(sc, AR_PHY_SETTLING, reg); reg = AR_READ(sc, AR_PHY_DESIRED_SZ); reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize); AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg); reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff); reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff); reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn); reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn); AR_WRITE(sc, AR_PHY_RF_CTL4, reg); reg = AR_READ(sc, AR_PHY_RF_CTL3); reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn); AR_WRITE(sc, AR_PHY_RF_CTL3, reg); reg = AR_READ(sc, AR_PHY_CCA(0)); reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62); AR_WRITE(sc, AR_PHY_CCA(0), reg); reg = AR_READ(sc, AR_PHY_EXT_CCA0); reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62); AR_WRITE(sc, AR_PHY_EXT_CCA0, reg); reg = AR_READ(sc, AR9287_AN_RF2G3_CH0); reg = RW(reg, AR9287_AN_RF2G3_DB1, modal->db1); reg = RW(reg, AR9287_AN_RF2G3_DB2, modal->db2); reg = RW(reg, AR9287_AN_RF2G3_OB_CCK, modal->ob_cck); reg = RW(reg, AR9287_AN_RF2G3_OB_PSK, modal->ob_psk); reg = RW(reg, AR9287_AN_RF2G3_OB_QAM, modal->ob_qam); reg = RW(reg, AR9287_AN_RF2G3_OB_PAL_OFF, modal->ob_pal_off); AR_WRITE(sc, AR9287_AN_RF2G3_CH0, reg); AR_WRITE_BARRIER(sc); DELAY(100); reg = AR_READ(sc, AR9287_AN_RF2G3_CH1); reg = RW(reg, AR9287_AN_RF2G3_DB1, modal->db1); reg = RW(reg, AR9287_AN_RF2G3_DB2, modal->db2); reg = RW(reg, AR9287_AN_RF2G3_OB_CCK, modal->ob_cck); reg = RW(reg, AR9287_AN_RF2G3_OB_PSK, modal->ob_psk); reg = RW(reg, AR9287_AN_RF2G3_OB_QAM, modal->ob_qam); reg = RW(reg, AR9287_AN_RF2G3_OB_PAL_OFF, modal->ob_pal_off); AR_WRITE(sc, AR9287_AN_RF2G3_CH1, reg); AR_WRITE_BARRIER(sc); DELAY(100); reg = AR_READ(sc, AR_PHY_RF_CTL2); reg = RW(reg, AR_PHY_TX_END_DATA_START, modal->txFrameToDataStart); reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn); AR_WRITE(sc, AR_PHY_RF_CTL2, reg); reg = AR_READ(sc, AR9287_AN_TOP2); reg = RW(reg, AR9287_AN_TOP2_XPABIAS_LVL, modal->xpaBiasLvl); AR_WRITE(sc, AR9287_AN_TOP2, reg); AR_WRITE_BARRIER(sc); DELAY(100); }
void ar9280_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c, struct ieee80211_channel *extc) { static const uint32_t chainoffset[] = { 0x0000, 0x2000, 0x1000 }; const struct ar5416_eeprom *eep = sc->eep; const struct ar5416_modal_eep_header *modal; uint32_t reg, offset; uint8_t txRxAtten; int i; modal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(c)]; AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon); for (i = 0; i < AR9280_MAX_CHAINS; i++) { if (sc->rxchainmask == 0x5 || sc->txchainmask == 0x5) offset = chainoffset[i]; else offset = i * 0x1000; AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0 + offset, modal->antCtrlChain[i]); reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0 + offset); reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, modal->iqCalICh[i]); reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, modal->iqCalQCh[i]); AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg); if (sc->eep_rev >= AR_EEP_MINOR_VER_3) { reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset); reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, modal->bswMargin[i]); reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB, modal->bswAtten[i]); reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, modal->xatten2Margin[i]); reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB, modal->xatten2Db[i]); AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg); } if (sc->eep_rev >= AR_EEP_MINOR_VER_3) txRxAtten = modal->txRxAttenCh[i]; else /* Workaround for ROM versions < 14.3. */ txRxAtten = IEEE80211_IS_CHAN_2GHZ(c) ? 23 : 44; reg = AR_READ(sc, AR_PHY_RXGAIN + offset); reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAtten); reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, modal->rxTxMarginCh[i]); AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg); } if (IEEE80211_IS_CHAN_2GHZ(c)) { reg = AR_READ(sc, AR_AN_RF2G1_CH0); reg = RW(reg, AR_AN_RF2G1_CH0_OB, modal->ob); reg = RW(reg, AR_AN_RF2G1_CH0_DB, modal->db); AR_WRITE(sc, AR_AN_RF2G1_CH0, reg); AR_WRITE_BARRIER(sc); DELAY(100); reg = AR_READ(sc, AR_AN_RF2G1_CH1); reg = RW(reg, AR_AN_RF2G1_CH1_OB, modal->ob_ch1); reg = RW(reg, AR_AN_RF2G1_CH1_DB, modal->db_ch1); AR_WRITE(sc, AR_AN_RF2G1_CH1, reg); AR_WRITE_BARRIER(sc); DELAY(100); } else { reg = AR_READ(sc, AR_AN_RF5G1_CH0); reg = RW(reg, AR_AN_RF5G1_CH0_OB5, modal->ob); reg = RW(reg, AR_AN_RF5G1_CH0_DB5, modal->db); AR_WRITE(sc, AR_AN_RF5G1_CH0, reg); AR_WRITE_BARRIER(sc); DELAY(100); reg = AR_READ(sc, AR_AN_RF5G1_CH1); reg = RW(reg, AR_AN_RF5G1_CH1_OB5, modal->ob_ch1); reg = RW(reg, AR_AN_RF5G1_CH1_DB5, modal->db_ch1); AR_WRITE(sc, AR_AN_RF5G1_CH1, reg); AR_WRITE_BARRIER(sc); DELAY(100); } reg = AR_READ(sc, AR_AN_TOP2); if ((sc->flags & ATHN_FLAG_USB) && IEEE80211_IS_CHAN_5GHZ(c)) { /* * Hardcode the output voltage of x-PA bias LDO to the * lowest value for UB94 such that the card doesn't get * too hot. */ reg = RW(reg, AR_AN_TOP2_XPABIAS_LVL, 0); } else reg = RW(reg, AR_AN_TOP2_XPABIAS_LVL, modal->xpaBiasLvl); if (modal->flagBits & AR5416_EEP_FLAG_LOCALBIAS) reg |= AR_AN_TOP2_LOCALBIAS; else reg &= ~AR_AN_TOP2_LOCALBIAS; AR_WRITE(sc, AR_AN_TOP2, reg); AR_WRITE_BARRIER(sc); DELAY(100); reg = AR_READ(sc, AR_PHY_XPA_CFG); if (modal->flagBits & AR5416_EEP_FLAG_FORCEXPAON) reg |= AR_PHY_FORCE_XPA_CFG; else reg &= ~AR_PHY_FORCE_XPA_CFG; AR_WRITE(sc, AR_PHY_XPA_CFG, reg); reg = AR_READ(sc, AR_PHY_SETTLING); reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling); AR_WRITE(sc, AR_PHY_SETTLING, reg); reg = AR_READ(sc, AR_PHY_DESIRED_SZ); reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize); AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg); reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff); reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff); reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn); reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn); AR_WRITE(sc, AR_PHY_RF_CTL4, reg); reg = AR_READ(sc, AR_PHY_RF_CTL3); reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn); AR_WRITE(sc, AR_PHY_RF_CTL3, reg); reg = AR_READ(sc, AR_PHY_CCA(0)); reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62); AR_WRITE(sc, AR_PHY_CCA(0), reg); reg = AR_READ(sc, AR_PHY_EXT_CCA0); reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62); AR_WRITE(sc, AR_PHY_EXT_CCA0, reg); if (sc->eep_rev >= AR_EEP_MINOR_VER_2) { reg = AR_READ(sc, AR_PHY_RF_CTL2); reg = RW(reg, AR_PHY_TX_END_DATA_START, modal->txFrameToDataStart); reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn); AR_WRITE(sc, AR_PHY_RF_CTL2, reg); } #ifndef IEEE80211_NO_HT if (sc->eep_rev >= AR_EEP_MINOR_VER_3 && extc != NULL) { /* Overwrite switch settling with HT-40 value. */ reg = AR_READ(sc, AR_PHY_SETTLING); reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40); AR_WRITE(sc, AR_PHY_SETTLING, reg); } #endif if (sc->eep_rev >= AR_EEP_MINOR_VER_19) { reg = AR_READ(sc, AR_PHY_CCK_TX_CTRL); reg = RW(reg, AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK, MS(modal->miscBits, AR5416_EEP_MISC_TX_DAC_SCALE_CCK)); AR_WRITE(sc, AR_PHY_CCK_TX_CTRL, reg); } if (AR_SREV_9280_20(sc) && sc->eep_rev >= AR_EEP_MINOR_VER_20) { reg = AR_READ(sc, AR_AN_TOP1); if (eep->baseEepHeader.dacLpMode && (IEEE80211_IS_CHAN_2GHZ(c) || !eep->baseEepHeader.dacHiPwrMode_5G)) reg |= AR_AN_TOP1_DACLPMODE; else reg &= ~AR_AN_TOP1_DACLPMODE; AR_WRITE(sc, AR_AN_TOP1, reg); AR_WRITE_BARRIER(sc); DELAY(100); reg = AR_READ(sc, AR_PHY_FRAME_CTL); reg = RW(reg, AR_PHY_FRAME_CTL_TX_CLIP, MS(modal->miscBits, AR5416_EEP_MISC_TX_CLIP)); AR_WRITE(sc, AR_PHY_FRAME_CTL, reg); reg = AR_READ(sc, AR_PHY_TX_PWRCTRL9); reg = RW(reg, AR_PHY_TX_DESIRED_SCALE_CCK, eep->baseEepHeader.desiredScaleCCK); AR_WRITE(sc, AR_PHY_TX_PWRCTRL9, reg); } AR_WRITE_BARRIER(sc); }